DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
The current application has a few species (a few embodiments: a first embodiment is shown in Figs. 1-7, a second embodiment is shown in Fig. 8, and a third embodiment is shown in Fig. 9).
Original Claims 1-3 of the application are directed to the first embodiment and
are examined on merits herein.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following must be shown or the features cancelled from the claim(s):
“the bit-line contact pad formed in the first region”, e.g., in the first region of the substrate, as Claim 1 recites.
No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of its inconsistency:
Paragraphs 0007 through 0033 of the published application US 2024/0429163 teach that Figs. 1 through 4 describe the same semiconductor device comprised a substrate, a logic circuit - incorporating a page buffer circuit - disposed over the substrate, and a memory cell region disposed above the logic circuit. This disposition is shown in Figs. 1 through 4. However, paragraphs 0047-0049 of the published application, referring to Fig. 4 as a schematic diagram illustrating structures of Fig. 1, teach that a page buffer circuit 22 includes a transistor TR having a junction in an active region of the substrate; this teaching means that at least a part of the logic circuit is located within the substrate, not on the substrate.
Paragraph 0047, referring to Fig. 4, states that the page buffer circuit is disposed in a lower layer of the bit lines. However, at least paragraph 0007 teaches that bit lines are disposed over a memory cell array, while the memory cell array is disposed over the logic circuit incorporating a page buffer circuit; and as such, the page buffer circuit cannot be disposed in a lower layer of the bit lines.
Appropriate corrections are required without introduction of a new matter.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-3 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
In re Claim 1: Lines 3-4 of Claim 1 recite: “a logic circuit stacked on the substrate that includes a page buffer circuit”. The recitation is unclear, since leads to a question: What includes a page buffer circuit – a logic circuit or a substrate?
Appropriate correction is required to clarify the claimed subject matter.
For this Office Action, based on the specification of the application, including Fig. 4, the above-cited recitation was interpreted as: “a logic circuit, including a page buffer circuit, is mainly located on the substrate”. This interpretation also addresses an issue of inconsistency explained in the objection to the specification, bringing correspondence between a claim limitation and Fig. 4 of the application.
In re Claim 1: Line 7 of Claim 1 recites: “a bit-line contact pad formed in the first region”. The recitation is unclear, since line 2 of Claim 1 teaches that a first region is a region of the substrate, while the specification of the application, including drawings, does not teach that a bit-line contact pad formed in the substrate.
Appropriate correction is required to clarify the claim language.
For this Office Action, the cited limitation was interpreted as: “a bit-line contact pad formed over the first region”.
In re Claim 3: Line 6 of Claim 3 recites: “electrically coupled to a junction region of the transistor”. The recitation is rejected for a lack of antecedent basis, since “a junction region of the transistor” was cited by Claim 1 on which Claim 3 depends.
For this Office Action, the cited limitation was interpreted as: “electrically coupled to the junction region of the transistor”.
In re Claim 2: Claim 2 is rejected under 35 U.S.C. 112(b) due to dependency on Claim 1.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
As far as the claims are understood, Claims 1-3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Oh et al. (US 2019/0115357).
In re Claim 1, Oh teaches a semiconductor device comprising (Figs. 1, 3, 5):
a substrate 10 (paragraph 0039) in which a first region (which is connected to bit lines BL, paragraph 0071) and a second region (not connected to bit lines) are defined;
a logic circuit 20 (as in Fig. 3, paragraph 0039, but shown as 200 in Fig. 1, paragraph 0021) stacked on the substrate 10 that includes a page buffer circuit 220 (as in Fig. 1, paragraph 0026);
a memory cell array 30 (Fig. 3, paragraph 0039, or 100 in Fig. 1, paragraph 0021, or MB in Fig. 5, paragraph 0045) stacked on the logic circuit 20 (in Figs. 3 and 5, or 200 in Fig. 1);
a bit line BLb (Fig. 5, paragraph 0071) formed over the memory cell array MB;
a bit-line contact pad 21D (Fig. 5, paragraph 0048) formed in the first region that electrically connects the bit line BLb to the page buffer circuit (paragraph 0048); and
a plurality of connection patterns 21B, 21A (paragraph 0048) formed below the bit-line contact pad 21D in a vertical direction, wherein
the bit line BLb and the bit-line contact pad 21D are electrically coupled to a junction region of a transistor TR of the page buffer circuit through the plurality of connection patterns (paragraph 0048).
In re Claim 2, Oh teaches the semiconductor device according to Claim 1 as cited above and wherein (Fig. 8) the bit-line contact pad 21D is formed in a rectangular island shape when viewed from the vertical direction (paragraph 0015).
In re Claim 3, Oh teaches the semiconductor device according to Claim 1 as cited above, wherein the plurality of connection patterns includes (Fig. 5):
a first connection pattern 21B formed below the bit-line contact pad 21D; and
a second connection pattern 21A, formed below the first connection pattern 21B, that is electrically coupled to a junction region of the transistor TR.
Conclusion
Any inquiry concerning this communication should be directed to GALINA G YUSHINA whose telephone number is 571-270-7440. The Examiner can normally be reached between 8 AM - 7 PM Pacific Time (Flexible).
Examiner interviews are available. To schedule an interview, Applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s Supervisor, Lynne Gurley can be reached on 571-272-1670.
The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300; a fax phone number of Galina Yushina is 571-270-8440.
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/GALINA G YUSHINA/Primary Patent Examiner, Art Unit 2811, TC 2800,
United States Patent and Trademark Office
E-mail: galina.yushina@USPTO.gov
Phone: 571-270-7440
Date: 09/18/26
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