DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of the invention of Group I, drawn to claims 1-12, in the reply filed on 28 September 2026 is acknowledged. Claims 13-20, directed to a nonelected invention, have been withdrawn
Claim Objections
Claims 1, 2, 5, 7, and 11 are objected to because of the following minor informalities:
Regarding claims 1 and 11, the claims recite “…a plurality of connection pillars, wherein each of the connection pillars...” This should be corrected to “…a plurality of connection pillars, wherein each of the plurality of connection pillars...” The claims also recite “… on a corresponding step...” If this corresponding step is meant to be one of the plurality of steps comprising the stack structure, this should read “…on a corresponding one of the plurality of steps...” Appropriate correction is required.
Regarding claim 2, the claim recites “…wherein the etch stop layer comprises a plurality of etch stop portions, the etch stop portion is provided on each of the steps, and the plurality of etch stop portions are disposed as being spaced apart from each other.” Here there is no antecedent basis for the etch stop portion or for the steps. The antecedent basis could be corrected by changing these limitations to “ one of the plurality of etch stop portions is provided on each of the plurality of steps…” Also, there is a grammatical problem with the limitation “the plurality of etch stop portions are disposed as being spaced apart from each other.” The word plurality is singular; therefore, a plurality cannot be spaced apart from each other, as there are no other pluralities. A suggested way to fix this grammar is by changing the language to require that each one of the etch stop portions comprised by the plurality of etch stop portions is spaced apart from the other etch stop portions comprised by the plurality of etch stop portions; however, this wording is awkward. Additionally, the wording “disposed as being spaced apart from each other” is not idiomatic. The Applicant is encouraged to consider other ways of wording this claim limitation to clearly convey the spacing requirement while also retaining proper antecedent basis. Appropriate correction is required.
Regarding claim 5, the claim recites “a first insulation layer, wherein a material of the first insulation layer is different from that of the etch stop layer.” The word “that” is a demonstrative pronoun in this context. In order to particularly point out and distinctly claim an invention, claim language should include nouns with proper antecedent basis rather than pronouns. If the phrase “that of the etch stop layer” means “the insulation material comprised by the etch stop layer,” then the claim should be amended to clearly reflect this meaning. Appropriate correction is required.
Regarding claim 7, as does claim 5, this claim recites “…wherein a material of the second insulation layer is the same as that of the etch stop layer.” Here also, the claim should point out and distinctly claim aspects of the invention without using the pronoun “that.” For the sake of precision and clarity use nouns with proper antecedent basis. If “that of the etch stop layer” means “the insulation material comprised by the etch stop layer,” then the claim should be amended to clearly reflect this meaning. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-12 are rejected under 35 U.S.C. 112(b), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, regards as the invention.
Regarding claim 1 and claim 11, the claim recites “a stack structure comprising a gate layer and a dielectric layer disposed alternately and comprising a plurality of steps.” The metes and bounds of “a plurality of steps” comprised by a single gate layer stacked with a single dielectric layer are unclear and thus render the claim indefinite. It is not clear how a stack of two layers can comprise a plurality of steps. This limitation is inconsistent with the drawings included in the disclosure, which clearly show that the plurality of steps comprises a plurality of gate layers and a plurality of dielectric layers. For purposes of examination, it will be assumed that there is plurality of gate layers, as well as a plurality of dielectric layers comprising the plurality of steps.
Regarding claims 2-10, these claims depend on claim 1 and so include all the limitations of claim 1; therefore, claims 2-10 are also indefinite.
Regarding claim 12, this claim depends on claim 11 and so includes all the limitations of claim 11; therefore, claim 12 is also indefinite.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
.
Claims 1-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hwang et al. US 20200152654.
Note: all figures of Hwang from 1-5 are relevant to the same embodiment of the three-dimensional memory. Figure 1 is the whole memory structure viewed from above [0011]. Figures 2A, 2B, and 2C are cross-sectional views taken along different lines [0012], while figures 3A-5B illustrate various enlarged views from figures 2A-2C [0013-0015].
Regarding claim 1, Hwang discloses a three-dimensional memory, comprising:
a stack structure comprising a gate layer and a dielectric layer disposed alternately and comprising a plurality of steps (figure 2B shows a 3D memory comprising a stack structure ST [0026] that comprises a gate electrode layer EL and a dielectric layer ILD [0026] and comprising a plurality of stepwise portions [0029-0030]);
an etch stop layer disposed on the plurality of steps (see figure 2B, where etch stop layer ES is disposed on a plurality of steps [0033]);
a protective layer covering the stack structure and the etch stop layer (figure 2B shows that a protective layer, comprising layers 55 and 60 as well as the top-most layer of IDL, covers the stack structure [0060]); and
a plurality of connection pillars, wherein each of the connection pillars penetrates through the protective layer and the etch stop layer on a corresponding step and is connected with the gate layer of the corresponding step (figure 2B shows that a plurality of connection pillars CPLG penetrate through the protective layer and the etch stop layer and connect with a gate layer EL on a corresponding step) .
Regarding claim 2, Hwang discloses the three-dimensional memory of claim 1, wherein
the etch stop layer comprises a plurality of etch stop portions (paragraph [0036] and figures 4A-4C disclose that the etch stop layer ES may have a discontinuous interface S within it, which may be a void or a seam, separating the etch stop layer sublayer 45 into two portions),
the etch stop portion is provided on each of the steps (as shown in figure 2B, the etch stop portions of 45 are provided on each of the plurality of steps), and
the plurality of etch stop portions are disposed as being spaced apart from each other (keeping in mind the interpretation of this claim discussed in the claim objection and in the 112(b) rejection, figures 2B and 4A-4C show that the etch stop portions are spaced apart from each other by the discontinuous interface S on each of the plurality of steps).
Regarding claim 3, Hwang discloses the three-dimensional memory of claim 1, wherein
the etch stop layer is a continuous film layer covering the plurality of steps (the etch stop layer ES comprises a continuous film layer in the direction of the surfaces of the step structures, conformally covering the step structure [0033]).
Regarding claim 4, Hwang discloses the three-dimensional memory of claim 3, wherein
the etch stop layer comprises an insulation material (paragraph [0035] discloses that layer 45, a part of etch stop layer ES, is a dielectric layer and thus comprises an insulating material).
Regarding claim 5, Hwang discloses the three-dimensional memory of claim 2, further comprising:
an isolation structure penetrating through the stack structure and the protective layer and comprising a first insulation layer (paragraph [0063] and figure 2C disclose an isolation structure SS3 that penetrates through the stack structure ST and the protective layer parts 60 and 55 and comprising a first insulation layer, the sidewall spacer SP [0064])
wherein a material of the first insulation layer is different from that of the etch stop layer (paragraph [0065] states that the sidewall spacer SP includes a dielectric material different from the etch stop layer 45).
Regarding claim 6, Hwang discloses the three-dimensional memory of claim 5, wherein
the isolation structure further comprises a filling layer (paragraph [0064] discloses that isolation layer SS3 may include the filling layer, common source plug CSP), and
the first insulation layer is located between the filling layer and the stack structure (paragraph [0064] discloses that the first insulation layer, sidewall spacer layer SP, is located between the filling layer CSP and the stack structure ST).
Regarding claim 7, Hwang discloses the three-dimensional memory of claim 2, further comprising:
an isolation structure penetrating through the stack structure and the protective layer and comprising a second insulation layer (paragraph [0061] discloses an isolation structure SS1 that penetrates through the stack structure ST and the protective layer parts 60 and 55 and comprising a second insulation layer, insulation layer 41, as illustrated in figure 5A), wherein
a material of the second insulation layer is the same as that of the etch stop layer (the material of the second insulation layer 41 is the same as that of the insulation layer 41 included in the etch stop layer as described in paragraph [0042]).
Regarding claim 8, Hwang discloses the three-dimensional memory of claim 7, wherein
the isolation structure further comprises a filling layer (paragraph [0064] discloses that isolation layer SS1 may include the filling layer, common source plug CSP), and
the second insulation layer is located between the filling layer and the stack structure (see figure 5A, where the second insulation layer 41 is located between the filling layer CSP and the stack structure, which comprises layers ILD and EL)
Regarding claim 9, Hwang discloses the three-dimensional memory of claim 8, wherein the isolation structure further comprises a third insulation layer located between the filling layer and the second insulation layer (see figure 5A, which discloses a third insulation layer SP located between the filling layer CSP and the second insulation layer 41).
Regarding claim 10, Hwang discloses the three-dimensional memory of claim 1, wherein a thickness of the etch stop layer is greater than a thickness of the gate layer (paragraph [0035] explicitly states that the thickness of the etch stop pattern 45 may be greater than the thickness of the gate electrodes EL; therefore, since layer 45, a sublayer of the etch stop layer, is thicker than the gate electrode, then the whole of the etch stop layer ES must also be thicker than the gate electrode.)
Regarding claim 11, Hwang discloses a three-dimensional memory, comprising:
a stack structure comprising a gate layer and a dielectric layer disposed alternately and comprising a plurality of steps (figure 2B shows a 3D memory comprising a stack structure ST [0026] that comprises a gate electrode layer EL and a dielectric layer IDL [0026] disposed alternately and comprising a plurality of stepwise portions [0029-0030]);
an insulation layer disposed on the plurality of steps (layer ES is an insulation layer comprising dielectric insulating layers 45, HL, and 41 [0034]);
a protective layer covering the stack structure and the insulation layer (figure 2B shows that a protective layer, comprising layers 55 and 60 as well as the top-most layer of IDL, covers the stack structure and the insulation layer ES [0060]); and
a plurality of connection pillars (figure 2B shows a plurality of connection pillars CPLG), wherein
each of the connection pillars penetrates through the protective layer and the insulation layer on a corresponding step and is connected with the gate layer of the corresponding step (figure 2B shows that each of the plurality of connection pillars CPLG penetrate through the protective layer 55 and 60 and the insulation layer and connect with a gate layer EL on a corresponding step).
Regarding claim 12, Hwang discloses the three-dimensional memory of claim 11, wherein
the insulation layer is a continuous film layer covering the plurality of steps (the insulation layer ES comprises a continuous film layer in the direction of the surfaces of the step structures, conformally covering the plurality of steps [0033]), and wherein
a thickness of the insulation layer is greater than a thickness of the gate layer (paragraph [0035] explicitly states that the thickness of the etch stop pattern 45 may be greater than the thickness of the gate electrodes EL; therefore, since layer 45, a sublayer of the insulation layer, is thicker than the gate electrode, then the whole of the insulation layer ES must also be thicker than the gate electrode.).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Wang et al. US 20220173040 discloses a similar 3D memory device with a protective layer disposed on the stack structure.
Lee et al. US 9419013 discloses a similar 3D memory device with an etch stop layer disposed on the stack structure.
Hojo et al. US 10700089 discloses a similar 3D memory having a stack of gate and dielectric layers with a step structure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KATRINA M H WALJESKI-MOSES whose telephone number is (571)272-0731. The examiner can normally be reached Mon- Fri 7:30 am- 5 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached at (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KATRINA WALJESKI-MOSES/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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