Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 09/04/2024, 02/14/2025 and 04/27/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Double Patenting
A rejection based on double patenting of the “same invention” type finds its support in the language of 35 U.S.C. 101 which states that “whoever invents or discovers any new and useful process... may obtain a patent therefor...” (Emphasis added). Thus, the term “same invention,” in this context, means an invention drawn to identical subject matter. See Miller v. Eagle Mfg. Co., 151 U.S. 186 (1894); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Ockert, 245 F.2d 467, 114 USPQ 330 (CCPA 1957).
A statutory type (35 U.S.C. 101) double patenting rejection can be overcome by canceling or amending the claims that are directed to the same invention so they are no longer coextensive in scope. The filing of a terminal disclaimer cannot overcome a double patenting rejection based upon 35 U.S.C. 101.
Claims 3, 2, 4, 10, 13, 12, 14, 19 and 20 provisionally rejected under 35 U.S.C. 101 as claiming the same invention as that of claims 1, 2, 4, 6, 7, 8, 10, 12 and 13 of copending Application No. 18/469,496 (reference application). This is a provisional statutory double patenting rejection since the claims directed to the same invention have not in fact been patented.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 10-14 and 20 are rejected under 35 U.S.C. 102(a)(1) as being unpatentable over US20220139911A1; Wei et al.; (hereinafter “Wei”).
Regarding Claim 1, Wei teaches a field effect transistor (FET) structure (Figure 1, nano-FET), comprising:
a gate structure (#372, Figure 4E of Wei annotated), disposed between a first vertical source/drain (S/D) structure (#414-1) and a second vertical S/D structure (#414-2), the gate structure comprising a channel structure (#475) and a vertical metal gate structure (#372), the channel structure comprising a plurality of vertically-stacked, horizontal channels (#475-1-#475-3, channels) connecting the first vertical S/D structure to the second vertical S/D structure horizontally through the vertical metal gate structure that at least partially surrounds the plurality of horizontal channels (#475-1 connects adjacent #414-1 and #414-2 through #372, wherein #372 partially surrounds #475-1); and
a backside inter-layer dielectric (ILD) layer (#380) disposed below the vertical metal gate structure (#372); and
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wherein a first thickness (#T3, Figure 4E of Wei annotated) of the vertical metal gate structure below a bottom channel (#475-1) of the plurality of horizontal channels is larger than a second thickness (#T2) of the vertical metal gate structure between adjacent channels (#475-2-#475-3) of the plurality of horizontal channels.
Regarding Claim 2, Wei teaches the FET structure as described in claim 1, wherein Wei further teaches a third thickness (#T1, Figure 4E of Wei annotated) of the vertical metal gate structure (#372) above a top channel of the plurality of vertically-stacked, horizontal channels (#475-3) is larger than the second thickness (#T2) of the vertical metal gate structure between adjacent channels (#475-2-#475-3) of the plurality of vertically-stacked, horizontal channels.
Regarding Claim 3, Wei teaches the FET structure as described in claim 1, wherein Wei further teaches a backside contact structure (#483, Figure 4E of Wei annotated) electrically coupled to the vertical metal gate structure (#372) through the backside ILD layer (#380) or through the backside ILD layer and a shallow trench isolation (STI) layer.
Regarding Claim 4, Wei teaches the FET structure as described in claim 1, wherein Wei further teaches the backside contact structure (#483, Figure 4E of Wei annotated) is electrically coupled to a backside metallization structure (#482) disposed below the backside ILD (#380).
Regarding Claim 10, Wei teaches the FET structure as described in claim 1, wherein Wei further teaches a backside S/D via (#383, Figure 3S, [0114]) connected to the first vertical S/D structure (#366) through the backside ILD layer (#380).
Regarding Claim 11, Wei teaches a method for fabricating a field effect transistor (FET) structure (Figures 2A-B, [0018]), the method comprising:
providing a gate structure (#372, Figure 4E of Wei annotated), disposed between a first vertical source/drain (S/D) structure (#414-1) and a second vertical S/D structure (#414-2), the gate structure comprising a channel structure (#475) and a vertical metal gate structure (#372), the channel structure comprising a plurality of vertically-stacked, horizontal channels (#475-1-#475-3) connecting the first vertical S/D structure to the second vertical S/D structure horizontally through the vertical metal gate structure that at least partially surrounds the plurality of horizontal channels (#475-1 connects adjacent #414-1 and #414-2 through #372, wherein #372 partially surrounds #475-1); and
providing a backside inter-layer dielectric (ILD) layer (#380) disposed below the vertical metal gate structure (#372),
wherein a first thickness (#T3, Figure 4E of Wei annotated) of the vertical metal gate structure below a bottom channel (#475-1) of the plurality of horizontal channels is larger than a second thickness (#T2) of the vertical metal gate structure between adjacent channels (#475-2-#475-3) of the plurality of horizontal channels.
Regarding Claim 12, Wei teaches the method as described in claim 11, wherein Wei further teaches a third thickness (#T1, Figure 4E of Wei annotated) of the vertical metal gate structure (#372) above a top channel of the plurality of vertically-stacked, horizontal channels (#475-3) is larger than the second thickness (#T2) of the vertical metal gate structure between adjacent channels (#475-2-#475-3) of the plurality of vertically-stacked, horizontal channels.
Regarding Claim 13, Wei teaches the method as described in claim 11, wherein Wei further teaches a backside contact structure (#483, Figure 4E of Wei annotated) electrically coupled to the vertical metal gate structure (#372) through the backside ILD layer (#380) or through the backside ILD layer and a shallow trench isolation (STI) layer.
Regarding Claim 14, Wei teaches the method as described in claim 13, wherein Wei further teaches the backside contact structure (#483, Figure 4E of Wei annotated) is electrically coupled to a backside metallization structure (#482) disposed below the backside ILD (#380).
Regarding Claim 20, Wei teaches the method as described in claim 11, wherein Wei further teaches a backside S/D via (#383, Figure 3S, [0114]) connected to the first vertical S/D structure (#366) through the backside ILD layer (#380).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 5-8, 15-17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Wei in view of US20210375761A1; Chang et al.; (hereinafter “Chang”).
Regarding Claim 5, Wei teaches the FET structure as described in claim 4.
Wei does not explicitly teach the FET structure is a component of a standard cell having a left cell boundary and right cell boundary separated from each other in the first horizontal direction and having a top cell boundary and a bottom cell boundary separated from each other in a second horizontal direction, and wherein the backside metallization structure comprises a pair of conductors that extend in the first horizontal direction from the left cell boundary to the right cell boundary and that are separated
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from each other in the second horizontal direction.
However, Chang teaches a nano-FET ([0013]), wherein the FET structure (Figure 33B of Chang annotated, [0017]) is a component of a standard cell having a left cell boundary (#LB, left boundary) and right cell boundary (#RB, right boundary) separated from each other in the first horizontal direction (#LB-#RB are separated in direction #D1) and having a top cell boundary (#TB, top boundary) and a bottom cell boundary (#BB, bottom boundary) separated from each other in a second horizontal direction (#TB-#BB are separated in direction #D2), and wherein a backside metallization structure (#135P) comprises a pair of conductors (#135P/VDD/VSS, power rails) that extend in the first horizontal direction (#D1) from the left cell boundary (#LB) to the right cell boundary (#RB) and that are separated from each other in the second horizontal direction (#135P/VDD & #135P/VSS are separated in direction #D2).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Wei with the teaching of Chang by known methods to yield predictable results (providing a standard cell structure). See MPEP 2143(I)(A).
Regarding Claim 6, Wei in view of Chang teaches the FET structure as described in claim 5, wherein Wei further teaches the pair of conductors are located between the top cell boundary and the bottom cell boundary in the second horizontal direction (See rejection of claim 5, Figure 33B of Chang annotated, power rails #135P/VDD and #135P/VSS dispose between of boundary regions #TP and #BB in direction #D2).
Regarding Claim 7, Wei in view of Chang teaches the FET structure as described in claim 5, wherein Wei further teaches a first conductor of the pair of conductors straddles the top cell boundary and a second conductor of the pair of conductors straddles the bottom cell boundary (See rejection of claim 5, Figure 33B of Chang annotated, [0119] of Chang, power rails #135P/VDD/VSS dispose on each end of boundary regions #TP and #BB).
Regarding Claim 8, Wei in view of Chang teaches the FET structure as described in claim 5, wherein Wei further teaches the first horizontal direction is orthogonal to the second horizontal direction (See rejection of claim 5, Figure 33B of Chang annotated, #D1-D2 are orthogonal).
Regarding Claim 15, Wei teaches the method as described in claim 14.
Wei does not explicitly teach the FET structure is a component of a standard cell having a left cell boundary and right cell boundary separated from each other in the first horizontal direction and having a top cell boundary and a bottom cell boundary separated from each other in a second horizontal direction, and wherein the backside metallization structure comprises a pair of conductors that extend in the first horizontal direction from the left cell boundary to the right cell boundary and that are separated from each other in the second horizontal direction.
However, Chang teaches a method of forming a nano-FET ([0013]), wherein the FET structure (Figure 33B of Chang annotated, [0017]) is a component of a standard cell having a left cell boundary (#LB, left boundary) and right cell boundary (#RB, right boundary) separated from each other in the first horizontal direction (#LB-#RB are separated in direction #D1) and having a top cell boundary (#TB, top boundary) and a bottom cell boundary (#BB, bottom boundary) separated from each other in a second horizontal direction (#TB-#BB are separated in direction #D2), and wherein a backside metallization structure (#135P) comprises a pair of conductors (#135P/VDD/VSS, power rails) that extend in the first horizontal direction (#D1) from the left cell boundary (#LB) to the right cell boundary (#RB) and that are separated from each other in the second horizontal direction (#135P/VDD & #135P/VSS are separated in direction #D2).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Wei with the teaching of Chang by known methods to yield predictable results (providing a standard cell structure). See MPEP 2143(I)(A).
Regarding Claim 16, Wei in view of Chang teaches the method as described in claim 15, wherein Wei further teaches providing the pair of conductors are located between the top cell boundary and the bottom cell boundary in the second horizontal direction (See rejection of claim 15, Figure 33B of Chang annotated, power rails #135P/VDD and #135P/VSS dispose between of boundary regions #TP and #BB in direction #D2).
Regarding Claim 17, Wei in view of Chang teaches the method as described in claim 15, wherein Wei further teaches providing the pair of conductors comprises providing a first conductor of the pair of conductors straddling the top cell boundary and providing a second conductor of the pair of conductors straddling the bottom cell boundary (See rejection of claim 15, Figure 33B of Chang annotated, [0119] of Chang, power rails #135P/VDD/VSS dispose on each end of boundary regions #TP and #BB).
Regarding Claim 19, Wei teaches the method as described in claim 13, wherein Wei further teaches providing the backside contact structure electrically coupled to the vertical metal gate structure through the backside ILD layer or through the backside ILD layer and the STI layer (Figures 4A-E, see rejection of claim 13) comprises:
etching the backside ILD layer to expose a dielectric layer of the vertical metal gate structure below the bottom channel of the plurality of horizontal channels (Figure 4A, opening #479 is etched to expose gate dielectric material #374 below channel #475-1);
performing a metallization process to create the backside contact structure electrically coupled to the vertical metal gate structure below the bottom channel of the plurality of horizontal channels (Figure 4B, [0125], opening #479 is filled with conductive material #378 to form backside gate contact #483).
Wei does not explicitly teach etching the dielectric layer to expose a gate electrode of the vertical metal gate structure below the bottom channel of the plurality of horizontal channels.
However, Chang teaches etching a dielectric layer (#100, gate dielectric layer, Figure 31D) to expose a gate electrode (#102, gate electrodes) of the vertical metal gate structure (#103B, gate structure) below the bottom channel (#54A) of the plurality of vertically-stacked, horizontal channels (backside gate via #164 extends through gate dielectric #100 to contact gate electrode #102).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Wei with the teaching of Chang, as it would be a simple substitution of one known element (backside gate contact of Wei) for another (backside gate via of Chang) in comparable devices to obtain predictable results (provide backside gate contact structure). See MPEP 2143(I)(B).
Claim 9 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Wei in view of US20240112984A1; Li et al.; (hereinafter “Li”).
Regarding Claim 9, Wei teaches the FET structure as described in claim 3.
Wei does not teach the backside contact structure comprises a backside gate isolation tiedown.
However, Li teaches a FET structure ([0003]), comprising the backside contact structure (#130, Figure 18C, via-to-backside power rail gate contact) comprises a backside gate isolation tiedown ([0079], #130 provides gate tied down to gate #135).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Wei with the teaching of Li to electrically isolate abutted cells, minimize area loss and increase device performance according to Li, [0050].
Regarding Claim 18, Wei teaches the method as described in claim 13.
Wei does not teach the backside contact structure comprises a backside gate isolation tiedown.
However, Li teaches a method of forming a FET structure ([0023]), comprising the backside contact structure (#130, Figure 18C, via-to-backside power rail gate contact) comprises a backside gate isolation tiedown ([0079], #130 provides gate tied down to gate #135).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Wei with the teaching of Li to electrically isolate abutted cells, minimize area loss and increase device performance according to Li, [0050].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US20180197784A1 – Figures 1-12
US20220223626A1 – Figures 3A or 5A-B
US20240170535A1 – Figures 2A-B & 3G
US20210384310A1 – Figures 2-3
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHRISTINE S KIM can be reached on (571)272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TIEN TRAN/Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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