DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 1 is objected to because of the following informalities: Claim 1 recites in the 6th line of the claim “a first acquisition integrated circuit a first output integrated circuit”, it will be understood as “a first acquisition integrated circuit, a first output integrated circuit” with a comma between “circuit” and “a first output”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites in the 14th line of the claim “to one or more integrated circuits of the ECaMS.”. There is insufficient antecedent basis for this limitation in the claim. The claim recites “a first acquisition integrated circuit”, “a second acquisition integrated circuit”, “a first output integrated circuit”, and a “second output integrated circuit”. It is unclear whether the claim is reciting a connection with a separate “integrated circuit” of the ECaMS, one of the “acquisition integrated circuits”, or one of the “output integrated circuits”, or one of the acquisition integrated circuits and output integrated circuits. Claims 2-20 depend on claim 1 and are therefore rejected.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-8 and 10-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Skertic et al (US 2020/0204400 hereinafter “Skertic”).
In regards to claim 1:
Skertic teaches a method for modifying an Engine Control and Monitoring System, ECaMS, for an engine (referred to by Skertic as FADEC “full authority digital engine controller”), the method comprising: identifying a provisioning deficit (the need for additional electronic control modules 208) in the ECaMS, wherein the ECaMS comprises a first processor node (204) and a second processor node (206): the first processor node comprising a first acquisition integrated circuit, a first output integrated circuit, and a first processor; and the second processor node comprising a second acquisition integrated circuit, a second output integrated circuit, and a second processor (Figure 2B shows a block diagram with each node having a processing unit and Figure 4 shows an example of how data is acquired and output), wherein the first acquisition integrated circuit is connected directly to the second acquisition integrated circuit (Shown in Figure 2B); and connecting an expansion unit (DIO) to the ECaMS, wherein the expansion unit comprises one or more expansion unit integrated circuits (Paragraph [0042] recites “Each DIO node may process signals, such as analog and/or digital signals, from engine sensors, and may provide control signals to operate actuators.”), said one or more expansion unit integrated circuits being connected to one or more integrated circuits of the ECaMS (Shown in Figure 5).
In regards to claim 2:
Skertic teaches the ECaMS further comprises a third processor node (208) and a fourth processor node (208): the third processor node comprising a third acquisition integrated circuit, a third output integrated circuit, and a third processor; and the fourth processor node comprising a fourth acquisition integrated circuit, a fourth output integrated circuit, and a fourth processor (Skertic teaches additional electronic control modules 208 can be added in Paragraph [0027]), wherein the first acquisition integrated circuit, second acquisition integrated circuit, third acquisition integrated circuit and fourth acquisition integrated circuit are connected via a ring network (Paragraph [0008] recites the nodes being in a ring network).
In regards to claim 3:
Skertic teaches the expansion unit is connected to the ECaMS as a spur to the ring network (Shown in Figure 5, DIO 516/518/568/520/570 are shown as a spur), such that the connecting of the expansion unit to the ECaMS comprises connecting one or more expansion unit integrated circuits to one or more integrated circuits within a single processor node of the ECaMS (Shown in Figure 5 the connection of the DIO to a CN).
In regards to claim 4:
Skertic teaches the connecting comprises connecting one or more expansion unit acquisition integrated circuits to one or more acquisition integrated circuits within the single processor node of the ECaMS (Shown in Figure 5 the connection of the DIO to a CN).
In regards to claim 5:
Skertic teaches the connecting comprises connecting one or more expansion unit output integrated circuits to one or more output integrated circuits within the single processor node of the ECaMS (Shown in Figure 5 the connection of the DIO to a CN).
In regards to claim 6:
Skertic teaches the expansion unit is connected to the ECaMS as a node within the ring network, such that the connecting of the expansion unit to the ECaMS comprises connecting the one or more expansion unit integrated circuits to integrated circuits within two processor nodes of the ECaMS (Shown in Figure 5).
In regards to claim 7:
Skertic teaches the method of claim 6, wherein the connecting comprises connecting one or more expansion unit acquisition integrated circuits to acquisition integrated circuits within the two processor node of the ECaMS.
In regards to claim 8:
Skertic teaches the connecting comprises connecting one or more expansion unit output integrated circuits to output integrated circuits within the two processor node of the ECaMS.
In regards to claim 10:
Skertic teaches the method further comprises: connecting the expansion unit to at least one sensor unit such that, in use, the expansion unit is configured to receive sensor data from the at least one sensor unit; and/or connecting the expansion unit to a processor unit such that, in use, the expansion unit is configured to receive discrete input/output signals and/or bi-directional data transmissions from the processor unit (Paragraph [0042] recites “Each DIO node may process signals, such as analog and/or digital signals, from engine sensors, and may provide control signals to operate actuators.”).
In regards to claim 11:
Skertic teaches the expansion unit is configured to receive sensor data generated by the at least one sensor unit, and to transmit data packets to the processor nodes of the ECaMS (Paragraph [0042]).
In regards to claim 12:
Skertic teaches 12. The method of claim 11, wherein the processor node connected to the expansion unit is configured to include a node identifier of itself in the data packets (Paragraph [0043] recites “For example, a CN may store blockchain data received from a DIO node, such as data identifying a manufacturer, a date of manufacture, a serial number, a qualification history (e.g., date of qualification), built-in-test data such as health data, a public key, a preceding hash (e.g., a hash previously generated), or any other data in a corresponding “unit level” blockchain.”).
In regards to claim 13:
Skertic teaches connecting the expansion unit to at least one output unit such that, in use, the expansion unit is configured to transmit data to the at least one output unit (Figure 5 shows DIO 520 connected to CN 510 and DIO 570).
In regards to claim 14:
Skertic teaches the output unit is a data collection unit (Paragraph [0042] recites “In some examples, a CN controls one or more DIO nodes. For example, the CN may send data to, and receive data from, a DIO node.”).
In regards to claim 15:
Skertic teaches the ECaMS is an Electrical Engine Controller, EEC (Paragraph [0002] recites “Aerospace control systems may include a full authority digital engine controller (“FADEC”) that includes an electronic engine controller (“EEC”) or engine control unit (“ECU”).”).
In regards to claim 16:
Skertic teaches a first portion of the processor nodes comprising at least one processor node provides control functionality, and a second portion of the processor nodes comprising at least one processor node provides protection functionality (Paragraph [0027] recites “A control node 204 may be, for example, a FADEC. In some examples, one or more of ESMs 208 may be a hardware security module (HSM) or a trusted protection module (TSM). Each control node 204, concentrator node 206, and multiple ESMs 208 may include one or more processing units 210, 212, 214.”).
In regards to claim 18:
Skertic teaches the integrated circuits include one or more of: Application Specific Integrated Circuits, ASICs; System on a Chips, SoCs; Complex Programmable Logic Devices, CPLDs; and Application Specific Standard Products, ASSPs (Paragraph [0027] recites the integrated circuit to be an Application Specific Integrated Circuits).
In regards to claim 19:
Skertic teaches the method is performed while the ECaMS is installed on an engine (Paragraph [0009] recites the controlling of a machine that is an engine).
In regards to claim 20:
Skertic teaches the engine is: an aeronautical gas turbine engine; a marine diesel engine; an automotive petrol engine; or a marine gas turbine engine (Paragraph [0009] recites the engine being an aeronautical gas turbine engine).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Skertic in view of Debenedetti et al (US 2021/0036962 hereinafter “Debenetti”).
In regards to claim 9:
Skertic teaches the ring network is a dual ring network comprising an anticlockwise ring.
Skertic does not teach a clockwise ring.
Debenetti teaches a clockwise network ring (Paragraph [0033]).
It would have been obvious to one of ordinary skill in the art at the time of filing of the application to have the network ring of Skertic to have a clockwise ring as taught by Debetti in order to have information flow in both directions.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES JAY KIM whose telephone number is (571)270-7610. The examiner can normally be reached M-F 9-5 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Logan Kraft can be reached at (571) 270-5065. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAMES J KIM/Examiner, Art Unit 3747 /HUNG Q NGUYEN/Primary Examiner, Art Unit 3747
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