DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, and 10-20 are rejected under 35 U.S.C. 103 as being unpatentable over Skertic et al (US 2020/0159941 hereinafter “Skertic”) in view of Gonnering et al (US 4,896,288 hereinafter “Gonnering”).
In regards to claim 1:
Skertic teaches an Engine Control and Monitoring System, ECaMS, for an engine, wherein the ECaMS comprises a first processor node (204) and a second processor node (206): the first processor node comprising a first acquisition integrated circuit (to receive data as described in Paragraph [0025]), a first output integrated circuit (to transmit data as described in Paragraph [0025]), and a first processor (processing unit 208, shown in Figure 2); and the second processor node (206) comprising a second acquisition integrated circuit (transceiver device 209 as described in Paragraphs [0026] – [0027]), a second output integrated circuit (transceiver device 209 as described in Paragraphs [0026] – [0027]), and a second processor (processing unit 210), wherein the first acquisition integrated circuit is connected directly to the second acquisition integrated circuit (Shown in Figure 2 for allowing direct communication between the control node 204 and the engine health monitoring node 206); wherein the ECaMS comprises a plurality of integrated circuits, the plurality of integrated circuits including the acquisition and output integrated circuits of the first and second processor nodes (Paragraph [0030] describes that one or more control nodes and one or more engine health monitoring nodes can be linked with sensor data from bus 312).
Skertic does not teach identifying a provisioning deficit in the ECaMS, connecting an expansion unit to the ECaMS and wherein the expansion unit comprises one or more expansion unit integrated circuits, the one or more expansion unit integrated circuits being connected to one or more of the plurality of integrated circuits of the ECaMS.
Gonnering teaches identifying a provisioning deficit.
It would have been obvious to one of ordinary skill in the art at the time of filing of the application to add an expansion unit to the system of Skertic as taught by Gonnering in order to bridge any insufficiencies of Skertic. Wherein Gonnering recites “Specifically, in instances where the number of input and output lines on the device I/O interface 24 is insufficient to provide the necessary low-speed input and control signals for the piece of manufacturing equipment, one or more device expansion modules such as module 18 may be connected to the expansion bus” (Col 3, Lines 34-57). Although Skertic does not teach that one is first noticing a provisioning deficit to implement additional circuits, Skertic does teach that additional circuits for additional sensor data can exist in a system (Paragraph [0030]). Gonnering teaches that one of ordinary skill in the art can determine that a provisioning deficit can exist. In the instant case, when additional sensors are added to the system of Skertic, a provisioning deficit will naturally arise due to additional sensor data, wherein a single processing node can not compute an infinite amount of data in a timely manner. Such that as additional data is received, more nodes that receive said additional data and process said data must be added.
In regards to claim 10:
Skertic teaches connecting the expansion unit to at least one sensor unit such that, in use, the expansion unit is configured to receive sensor data from the at least one sensor unit; and/or connecting the expansion unit to a processor unit such that, in use, the expansion unit is configured to receive discrete input/output signals and/or bi-directional data transmissions from the processor unit (described in Paragraphs [0028] – [0030]).
In regards to claim 11:
Skertic teaches the expansion unit is configured to receive sensor data generated by the at least one sensor unit, and to transmit data packets to the processor nodes of the ECaMS (Shown in Figure 3 and described in Paragraphs [0028] – [0030]).
In regards to claim 12:
Skertic teaches the processor node connected to the expansion unit is configured to include a node identifier of itself in the data packets (Paragraphs [0048] – [0056] recites identification and password encryption for data identifying itself).
In regards to claim 13:
Skertic teaches connecting the expansion unit to at least one output unit such that, in use, the expansion unit is configured to transmit data to the at least one output unit (operation of the nodes and how they output data is described in Paragraphs [0026] – [0030]).
In regards to claim 14:
Skertic teaches the output unit is a data collection unit, wherein sensor data is collected.
In regards to claim 15:
Skertic teaches the ECaMS is an Electrical Engine Controller, EEC (Paragraph [0002]).
In regards to claim 16:
Skertic teaches a first portion of the processor nodes comprising at least one processor node provides control functionality, and a second portion of the processor nodes comprising at least one processor node provides protection functionality (Paragraphs [0048] – [0056] recites password protection functionality done by the processor).
In regards to claim 17:
Skertic the first portion of the processor nodes are segmented from the second portion of the processor nodes, and wherein the expansion unit is connected to either the first portion of the processor nodes or the second portion of the processor nodes.
In regards to claim 18:
Skertic teaches the integrated circuits include one or more of: Application Specific Integrated Circuits, ASICs; System on a Chips, SoCs; Complex Programmable Logic Devices, CPLDs; and Application Specific Standard Products, ASSPs (Paragraph [0041]).
In regards to claim 19:
Skertic teaches the method is performed while the ECaMS is installed on an engine (104).
In regards to claim 20:
Skertic teaches the engine is: an aeronautical gas turbine engine (Paragraph [0021]).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Skertic and Gonnering as applied to claim 1 above, and further in view of Kretschmann et al (US 8,769,158 hereinafter “Kretschmann”).
In regards to claim 2:
Skertic teaches the ECaMS further comprises a third processor node and a fourth processor node: the third processor node comprising a third acquisition integrated circuit, a third output integrated circuit, and a third processor; and the fourth processor node comprising a fourth acquisition integrated circuit, a fourth output integrated circuit, and a fourth processor (Paragraph 30 recites additional nodes to receive additional sensor data from sensors 314, 316, 318, 320, 322, 324), wherein the first acquisition integrated circuit, second acquisition integrated circuit, third acquisition integrated circuit and fourth acquisition integrated circuit are connected via an avionics network or a suitable network (Paragraph 30 recites the nodes are connected via a network).
Skertic does not specify the network to be a ring network.
Kretschmann teaches a ring network.
It would have been obvious to one of ordinary skill in the art at the time of filing of the application for the network of Skertic to be a ring network as taught by Kretschmann in order to have nodes connected to one another and allowing data to travel to one another.
Claims 3-8 are rejected under 35 U.S.C. 103 as being unpatentable over Skertic, Gonnering and Kretschmann as applied to claim 2 above, and further in view of Skertic et al (US 2020/0204400 hereinafter “Skertic ‘400”).
In regards to claim 3:
Skertic teaches the expansion unit is connected to the ECaMS via the ring network, such that the connecting of the expansion unit to the ECaMS comprises connecting one or more expansion unit integrated circuits to one or more integrated circuits within a single processor node of the ECaMS (Kretschmann shows multiple nodes and belonging to a bank of nodes, and the system having a plurality of banking nodes shown in Figures 4-9).
Skertic does not specify the expansion is connected as a spur.
Skertic ‘400 teaches nodes (526, 566, 518, 568, 520, 570) that are connected to a ring network as a spur.
It would have been obvious to one of ordinary skill in the art at the time of filing of the application for the expansion unit of Skertic to be a spur as taught by Skertic ‘400 in order to have a main control node connected in isolation to an expansion unit node (Shown in Figure 5 of Skertic ‘400). Having a spur node allows sensors that are relative to a group of nodes allows data that pertains to a specific node and further have separate encryptions for specific nodes (Paragraphs [0040] – [0050] of Skertic ‘400).
In regards to claim 4:
Skertic teaches the connecting comprises connecting one or more expansion unit acquisition integrated circuits to one or more acquisition integrated circuits within the single processor node of the ECaMS (Kretschmann shows multiple expansion slots for adding additional nodes in Figure 4-9).
In regards to claim 5:
Skertic teaches the connecting comprises connecting one or more expansion unit output integrated circuits to one or more output integrated circuits within the single processor node of the ECaMS, wherein this is how ring networks operate with outputs of nodes being connected to other nodes and an example of expansion units having outputs connected to an integrated circuit is shown in Figure 5 of Skertic ‘400.
In regards to claim 6:
Skertic teaches the expansion unit is connected to the ECaMS as a node within the ring network.
Skertic does not specify the connecting of the expansion unit to the ECaMS comprises connecting the one or more expansion unit integrated circuits to integrated circuits within two processor nodes of the ECaMS.
Skertic teaches an expansion unit (DIO node) integrated into a ring network within two processor nodes.
It would have been obvious to one of ordinary skill in the art at the time of filing of the application for the expansion unit to be integrated to the ring network within two processor nodes as taught by Skertic ‘400 wherein in a ring network processor nodes are connected to one another, and when an expansion unit node is connected to a processor node, and the ring network has another processor node connected in a ring, the expansion node will be within two processor nodes (Shown in Figure 5 of Skertic ‘400).
In regards to claim 7:
Skertic teaches the connecting comprises connecting one or more expansion unit acquisition integrated circuits to acquisition integrated circuits within the two processor node of the ECaMS (Shown in Figure 5 of Skertic ‘400).
In regards to claim 8:
Skertic teaches the connecting comprises connecting one or more expansion unit output integrated circuits to output integrated circuits within the two processor node of the ECaMS (Shown in Figure 5 of Skertic ‘400).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Skertic, Gonnering and Kretschmann as applied to claim 2 above, and further in view of Debenedetti et al (US 2021/0036962 hereinafter “Debenetti”).
In regards to claim 9:
Skertic does not specify the ring network is a dual ring network comprising a clockwise ring and anticlockwise ring.
Debenetti teaches a clockwise and counter-clockwise network ring (Paragraph [0033]).
It would have been obvious to one of ordinary skill in the art at the time of filing of the application to have the network ring of Skertic to have a clockwise ring as taught by Debetti in order to have information flow in both directions.
Response to Arguments
Applicant’s arguments, see pages 6-8 of Remarks, filed 7/14/2026, with respect to the rejection(s) of claim(s) 1-20 under 35 USC 102(a)(1) and 35 USC 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of newly found prior art.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES JAY KIM whose telephone number is (571)270-7610. The examiner can normally be reached M-F 9-5 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Logan Kraft can be reached at (571) 270-5065. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAMES J KIM/Examiner, Art Unit 3747 /HUNG Q NGUYEN/Primary Examiner, Art Unit 3747
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