Prosecution Insights
Last updated: October 24, 2026
Application No. 18/825,173

THREE-DIMENSIONAL SEMICONDUCTOR DEVICES

Non-Final OA §112
Filed
Sep 05, 2024
Priority
Nov 09, 2023 — RE 10-2023-0154185
Examiner
CHOWDHARY, NIMARTA KAUR
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
100%
Grant Probability
Favorable
1-2
OA Rounds
9m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 100% — above average
100%
Career Allowance Rate
5 granted / 5 resolved
+32.0% vs TC avg
Minimal +0% lift
Without
With
+0.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
35 currently pending
Career history
38
Total Applications
across all art units

Statute-Specific Performance

§101
1.0%
-39.0% vs TC avg
§103
39.8%
-0.2% vs TC avg
§102
27.6%
-12.4% vs TC avg
§112
30.6%
-9.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 5 resolved cases

Office Action

§112
DETAILED ACTION Priority Claim Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. IDS All references provided in the IDS have been considered. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.— The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. Claims 14-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Regarding Independent Claim 14, Claim 14, line 2-4 and 8-10 recite: ” bit lines disposed on a substrate, each of the bit lines extending primarily in a first direction, and the bit lines being spaced apart from each other in a second direction that is perpendicular to the first direction;” and “first extension portions electrically connected to the first and second transistor, respectively, each of the first extension portions extending primarily in a third direction that is perpendicular to the first and second directions;”, respectively. As written, the first, second, and third directions appear to be interchangeable and in conflict with the specification, ¶ [0063] and drawings (Fig. 3, Fig. 53, and Fig. 54), rendering the claim scope indefinite (for example, in Fig. 54, the bit lines are extending primarily in a first direction, but in order for this to be true, the “D3” direction is to be considered the “first direction”, which is in conflict with ¶ [0063] of the disclosure and introduces ambiguity). The “first” direction is taken to be in the vertical direction extending from the upper planar surface of the substrate, while the second and third directions are taken to be the two horizontal directions sharing an endpoint with the first direction. Appropriate correction is required. Claims 15-18 are rejected by virtue of their dependency on Claim 14. Claim 14, line 5 recites: “a first transistor, a capacitor, and a second transistor sequentially disposed in the second direction.” It is unclear what is meant by “sequentially disposed”. It has been interpreted to mean that from left to right (or vice versa) on the same planar surface, there is a transistor/capacitor/transistor sequence. Claims 15-18 are rejected by virtue of their dependency on Claim 14. Allowable Subject Matter Claims 1-13, 19-20 are allowed. Re: Independent Claim 1 (and its dependent claim(s) 2-13), the prior art of record do not disclose or suggest, in combination with all other limitations in the claim: Lee (US 20220199621 A1), the closest prior art of record, discloses: A semiconductor device, comprising: first and second bit lines each disposed on a substrate, and the first and second bit lines being spaced apart from each other in a second direction that is parallel to the upper surface of the substrate; a word line including: first extension portions disposed between the first and second bit lines, a second extension portion first and second channels each extending through the first extension portions of the word line; and a capacitor including: a first capacitor electrode electrically connected to the first channel; a dielectric pattern disposed on a surface of the first capacitor electrode; and a second capacitor electrode disposed on a surface of the dielectric pattern, the second capacitor electrode being electrically connected to the second channel. Lee and other prior art made of record does not explicitly disclose or suggest: each of the first and second bit lines extending primarily in a first direction that is perpendicular to an upper surface of the substrate, each of the first extension portions extending primarily in a third direction that is parallel to the upper surface of the substrate and intersecting the second direction; and a second extension portion extending primarily in the second direction at a same level as the first extension portions and being connected to the first extension portions. It would not be obvious to a POSITA to modify the device and specific orientations of the first and second bit lines and the first and second extension portions to make the invention as claimed. Dependent Claims 2-13 incorporate the allowable subject of Independent Claim 1, and are therefore allowable. Re: Independent Claim 19 (and its dependent Claim 20), independent Claim 19 includes the allowable subject matter that is disclosed in Independent Claim 1, and is therefore allowable. Claim(s) 14 (and dependent Claims 15-18) would be allowable if rewritten or amended to overcome the rejection under 35 U.S.C 112 (b). No new prior art has been applied to claims 14-20 as best understood. Re: Independent Claim 14 (and its dependent Claim 15-20), independent Claim 14 includes the allowable subject matter that is disclosed in Independent Claim 1, and may be allowed upon overcoming the 112b rejection. As allowable subject matter has been indicated, applicant's reply must either comply with all formal requirements or specifically traverse each requirement not complied with. See 37 CFR 1.111(b) and MPEP § 707.07(a). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to NIMARTA KAUR CHOWDHARY whose telephone number is (571)272-7679. The examiner can normally be reached usually Monday - Thursday, 6:45 AM - 4:45 PM (EST). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at (571) 270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NIMARTA KAUR CHOWDHARY/Examiner, Art Unit 2898 /Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
Read full office action

Prosecution Timeline

Sep 05, 2024
Application Filed
Oct 01, 2026
Non-Final Rejection mailed — §112
Oct 20, 2026
Interview Requested

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12772909
CHIP PACKAGING METHOD, CHIP PACKAGING MODULE, AND EMBEDDED SUBSTRATE CHIP PACKAGING STRUCTURE
2y 11m to grant Granted Oct 20, 2026
Patent 12760443
SILICON CARBIDE HETEROJUNCTION NORMALLY-OFF HIGH-ELECTRON-MOBILITY TRANSISTOR AND METHOD FOR PREPARING THE SAME
2y 10m to grant Granted Oct 13, 2026
Patent 12666589
MEMORY CELL, MEMORY, AND METHOD OF MANUFACTURING THE SAME
1y 3m to grant Granted Jun 23, 2026
Study what changed to get past this examiner. Based on 3 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
100%
Grant Probability
99%
With Interview (+0.0%)
2y 10m (~9m remaining)
Median Time to Grant
Low
PTA Risk
Based on 5 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month