Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5, 9-10 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Oh et al. (US 2023/0132272, hereinafter Oh)
With respect to claim 1, Oh discloses a semiconductor device (Fig. 3) comprising: a lower insulator (130); a plurality of lower pads (150) provided in the lower insulator; an upper insulator (140) provided on the lower insulator; and
a plurality of upper pads (160) provided on the plurality of lower pads in the upper insulator (Fig. 3), wherein a second pad that is included in the plurality of upper pads is disposed on a first pad that is included in the plurality of lower pads (there are multiple upper pads 160 , any one of them can be a second pad and there are multiple lower pads 150, a corresponding lower pad can be a first pad– upper pads are disposed on lower pads).
In the same embodiment Oh does not explicitly disclose that the structure of the second pad is different from a structure of the first pad.
In another embodiment, Oh discloses that a structure of the second pad is different from a structure of the first pad (Para 0007-0008; 0038 and 0041; width of lower and upper pads is different).Therefore, it would have been obvious to one of an ordinary skilled in the art at the time of invention to modify Oh’s first embodiment by having disclosure from the second embodiment in order to address different current requirements of a semiconductor device.
With respect to claim 2, Oh discloses wherein a shape of the second pad in plan view is non-congruent with a shape of the first pad in plan view (Para 0038 and 0041).
With respect to claim 3, Oh discloses wherein an area of the second pad in plan view is different from an area of the first pad in plan view (Para 0038 and 0041 – different areas for lower and upper pads).
With respect to claim 5, Oh discloses wherein a thickness of the second pad is
different from a thickness of the first pad (Para 0071-0072 – under BRI , width can be thickness).
With respect to claim 9, Oh discloses wherein a semiconductor device comprising: a lower wafer (510 & 130 – Para 0112) that includes a lower insulator (130 ), and a plurality of lower pads (150) provided in the lower insulator (Fig. 3); and an upper wafer (top 100 & 140 – Para 0104) that includes an upper insulator (140) provided on the lower insulator (Fig. 3), and a plurality of upper pads (160) provided on the plurality of lower pads in the upper insulator (Fig. 3), wherein a second pad that is included in the plurality of upper pads is disposed on a first pad that is included in the plurality of lower pads (there are multiple upper pads 160 , any one of them can be a second pad and there are multiple lower pads 150, a corresponding lower pad can be a first pad– upper pads are disposed on lower pads).
In the same embodiment Oh does not explicitly disclose that a structure of the second pad is different from a structure of the first pad.
In another embodiment, Oh discloses that the structure of the second pad is different from a structure of the first pad (Para 0007-0008; 0038 and 0041; width of lower and upper pads is different). Therefore, it would have been obvious to one of an ordinary skilled in the art at the time of invention to modify Oh’s first embodiment by having disclosure from the second embodiment in order to address different current requirements of a semiconductor device.
With respect to claim 10, Oh discloses wherein the lower wafer further includes a lower substrate (510) provided below the lower insulator (510 is below 130), and the upper wafer further includes an upper substrate (100) provided on the upper insulator (140).
With respect to claim 13, Oh discloses a method of manufacturing a semiconductor device (Para 0028), comprising: forming a lower insulator (130 of Fig. 3) on a lower substrate (510 – Para 0112) of a lower wafer (510 & 130); forming a plurality of lower pads (150) in the lower insulator; forming an upper insulator (140) on an upper substrate (100) of an upper wafer (100 & 140); forming a plurality of upper pads (160) in the upper insulator; and bonding the lower wafer and the upper wafer to dispose the upper insulator on the lower insulator and dispose the plurality of upper pads on the plurality of lower pads (Para 0112 and 0114), wherein a second pad that is included in the plurality of upper pads is disposed on a first pad that is included in the plurality of lower pads (there are multiple upper pads 160, any one of them can be a second pad and there are multiple lower pads 150, a corresponding lower pad can be a first pad– upper pads are disposed on lower pads).
In the same embodiment Oh does not explicitly disclose that a structure of the second pad is different from a structure of the first pad.
In another embodiment, Oh discloses that a structure of the second pad is different from a structure of the first pad (Para 0007-0008; 0038 and 0041; width of lower and upper pads is different). Therefore, it would have been obvious to one of an ordinary skilled in the art at the time of invention to modify Oh’s first embodiment by having disclosure from the second embodiment in order to address different current requirements of a semiconductor device.
Claims 4, 6-7 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Oh in view of Lattard (US 2019/0279965, hereinafter Lattard).
With respect to claim 4, Oh does not explicitly disclose wherein a shape of the second pad in plan view is congruent with a shape of the first pad in plan view, and an orientation of the second pad in plan view is different from an orientation of the first pad in plan view.
In an analogous art, Lattard discloses wherein a shape of the second pad in plan view is congruent with a shape of the first pad in plan view (Para 0068; 0081), and an orientation of the second pad in plan view is different from an orientation of the first pad in plan view (Para 0004; 0081 and 0097). Therefore, it would have been obvious to one of an ordinary skilled in the art at the time of invention to modify Oh’s first embodiment by having Lattard’s disclosure in order to improve the contact area of a semiconductor device.
With respect to claims 6, and 14, Oh does not explicitly disclose wherein a joint area of the first pad and the second pad is equal to or larger than 40% of an area of the first pad in plan view and/or is equal to or larger than 40% of an area of the second pad in plan view.
In an analogous art, Lattard discloses wherein a joint area of the first pad and the second pad is equal to or larger than 40% of an area of the first pad in plan view and/or is equal to or larger than 40% of an area of the second pad in plan view (Para 0061; 0063 and 0081 -0082 and 0093; total area of the first pad and the second pad is greater than 40% of the first pad or the second pad in plan view) . Therefore, it would have been obvious to one of an ordinary skilled in the art at the time of invention to modify Oh’s first embodiment by having Lattard’s disclosure in order to bridge different layouts of a semiconductor device.
With respect to claim 7, Oh does not explicitly disclose wherein a pitch between the upper pads is different from a pitch between the lower pads.
In an analogous art, Lattard discloses wherein a pitch between the upper pads is different from a pitch between the lower pads (Para 0012; and 0054). Therefore, it would have been obvious to one of an ordinary skilled in the art at the time of invention to modify Oh’s first embodiment by having Lattard’s disclosure in order to bridge different layouts of a semiconductor device.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Oh in view of Oh (US 2022/0068844, hereinafter Oh II).
With respect to claim 8, Oh does not explicitly disclose wherein a memory cell array provided in the upper insulator; and a control circuit provided in the lower insulator and configured to control the memory cell array.
In an analogous art, Oh II discloses wherein a memory cell array provided in the upper insulator (para 0030); and a control circuit provided in the lower insulator and configured to control the memory cell array (para 0032 and 0038). Therefore, it would have been obvious to one of an ordinary skilled in the art at the time of invention to modify Oh’s first embodiment by having Oh II’s disclosure in order to improve the storage capability of a memory device.
Claims 11 is rejected under 35 U.S.C. 103 as being unpatentable over Oh in view of Kanakamedala (US 2020/0251443, hereinafter Kanakamedala).
With respect to claim 11, Oh does not explicitly disclose wherein a state of a warpage of the upper substrate is different from a state of a warpage of the lower substrate.
In an analogous art, Kanakamedala discloses wherein a state of a warpage of the upper substrate is different from a state of a warpage of the lower substrate (Para 0048 and 0062). Therefore, it would have been obvious to one of an ordinary skilled in the art at the time of invention to modify Oh’s first embodiment by having Lattard’s disclosure in order to bridge different layouts of a semiconductor device.
Claims 12, and 15-19 is rejected under 35 U.S.C. 103 as being unpatentable over Oh in view of Gao et al. (US 2021/0296282, hereinafter Gao).
With respect to claim 12, Oh does not explicitly disclose wherein a state of a magnification of the upper substrate is different from a state of a magnification of the lower substrate.
In an analogous art, Gao discloses wherein a state of a magnification of the upper substrate is different from a state of a magnification of the lower substrate (Para 0048-0049). Therefore, it would have been obvious to one of an ordinary skilled in the art at the time of invention to modify Oh’s first embodiment by having Gao’s disclosure in order to have more reliable electrical connections.
With respect to claim 15, Oh does not explicitly disclose measuring a value
representing a state of the lower substrate or the upper substrate, wherein the first pad and the second pad are formed based on the value such that the structure of the second pad is different from the structure of the first pad.
In an analogous art, Gao discloses measuring a value representing a state of the lower substrate or the upper substrate (Para 0058-0059), wherein the first pad and the second pad are formed based on the value such that the structure of the second pad is different from the structure of the first pad (Para 0038; 0054 and 0056). Therefore, it would have been obvious to one of an ordinary skilled in the art at the time of invention to modify Oh’s first embodiment by having Gao’s disclosure in order to adjust different layouts of a semiconductor device.
With respect to claim 16, Oh does not explicitly disclose wherein the value is related to a warpage of the lower substrate or the upper substrate.
In an analogous art, Gao discloses wherein the value is related to a warpage of the lower substrate or the upper substrate (Para 0040-0041). Therefore, it would have been obvious to one of an ordinary skilled in the art at the time of invention to modify Oh’s first embodiment by having Gao’s disclosure in order to minimize the failures of a semiconductor device by detecting the unevenness.
With respect to claim 17, Oh does not explicitly disclose wherein the value is related to a magnification of the lower substrate or the upper substrate.
In an analogous art, Gao discloses wherein the value is related to a magnification of the lower substrate or the upper substrate (Para 0054). Therefore, it would have been obvious to one of an ordinary skilled in the art at the time of invention to modify Oh’s first embodiment by having Gao’s disclosure in order to adjust different layouts of a semiconductor device.
With respect to claim 18, Oh does not explicitly disclose
correcting structures of the lower pads or the upper pads based on the value, when the lower pads or the upper pads are formed, wherein the first pad and the second pad are formed such that the structure of the second pad before the correction is same as the structure of the first pad before the correction, and the structure of the second pad after the correction is different from the structure of the first pad after the correction.
In an analogous art, Gao discloses correcting structures of the lower pads or the upper pads based on the value, when the lower pads or the upper pads are formed, wherein the first pad and the second pad are formed such that the structure of the second pad before the correction is same as the structure of the first pad before the correction (Para 0038), and the structure of the second pad after the correction is different from the structure of the first pad after the correction (Para 0054-0055).
Therefore, it would have been obvious to one of an ordinary skilled in the art at the time of invention to modify Oh’s first embodiment by having Gao’s disclosure in order to adjust different layouts of a semiconductor device.
With respect to claim 19, Oh does not explicitly disclose wherein the correction is performed such that a joint area of the first pad and a second pad after the correction is larger than a joint area of the first pad and the second pad before the correction.
In an analogous art, Gao discloses wherein the correction is performed such that a joint area of the first pad and a second pad after the correction is larger than a joint area of the first pad and the second pad before the correction (Para 0044 and 0054). Therefore, it would have been obvious to one of an ordinary skilled in the art at the time of invention to modify Oh’s first embodiment by having Gao’s disclosure in order to adjust different layouts of a semiconductor device.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Oh/Gao in view of Lattard.
With respect to claim 20, Oh does not explicitly disclose wherein the correction is performed such that a pitch between the lower pads or the upper pads after the correction is different from a pitch between the lower pads or the upper pads before the correction.
In an analogous art, Lattard discloses wherein the correction is performed such that a pitch between the lower pads or the upper pads after the correction is different from a pitch between the lower pads or the upper pads before the correction (Para 0012; and 0054). Therefore, it would have been obvious to one of an ordinary skilled in the art at the time of invention to modify Oh/Gao’s method by having Lattard’s disclosure in order to bridge different layouts of a semiconductor device.
Conclusion
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/MOHAMMAD M CHOUDHRY/ Primary Examiner, Art Unit 2899
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