Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 9/5/2024 was filed before the mailing date of the Non-final rejection on 9/16/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The formal drawings filed on 9/5/2024 have been approved by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: “ LEAD FRAME HAVING AN ENCAPSULATION PROTRUDING PORTION ON THE SIDE SURFACE ”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4, 7, 14, and 16 are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by Kawashima et al. (WO 2015/173862).
With respect to Claims 1 and 16, Kawashima teaches a lead frame 2a, 2c and a semiconductor chip 5, 6 provided above the lead frame. A first lead terminal electrically connected to the semiconductor chip. A package 10 encapsulating the semiconductor chip 5, 6 a part of the lead frame, and a part of the first lead terminal 2a. The package 10 includes an upper surface , a lower surface, a first side surface, and a second side surface the upper surface is provided above the semiconductor chip 5, 6. The lower surface is provided below the semiconductor chip 5, 6. The first side surface 11 is provided between the upper surface and the lower surface. The first lead terminal 2a protrudes from the first side surface, wherein the first side surface 11 has a first surface, a second surface, and a third surface the first surface is continuous with the upper surface of the package and is provided in an oblique direction with respect to the upper surface of the package. The second surface is continuous with the first surface and is provided in a direction parallel to the upper surface of the package, and the third surface is continuous with the second surface and is provided in a direction orthogonal to the upper surface of the package 10. The second side surface is provided between the upper surface and the lower surface, and the first lead terminal does not protrude from the second side surface (see Figs. 1, 2, 9, 10, 15, and 16).
With respect to Claim 4, Kawashima teaches a distance from the lower surface of the package to the second surface of the first side surface coincides with a distance from the lower surface of the package to an upper surface of the first lead terminal 2a (see Figs. 1, 2, 9, 10, 15, and 16).
With respect to Claim 7, Kawashima teaches the second side surface is provided in an oblique direction with respect to the upper surface of the package 10(see Figs. 1, 2, 9, 10, 15, and 16).
With respect to Claim 14, Kawashima teaches the package 10 seals the semiconductor chip on the lead frame 2a, 2c (see Figs. 1, 2, 9, 10, 15, and 16).
Allowable Subject Matter
Claim 2, 3, 5, 6, 8-12, 15, 17, and 18 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
The following is a statement of reasons for the indication of allowance subject
matter: none of the prior art of record teaches or suggest the combination of the package includes a first portion protruding on the first side surface and provided adjacent to the first lead terminal. An upper surface of the first portion corresponds
to the second surface, and a side surface of the first portion corresponds to the third surface in claim 2.
A position of the second surface of the first side surface coincides with a position of an upper surface of the first lead terminal in a direction orthogonal to the upper surface of the package in claim 3.
A second lead terminal electrically connected to the semiconductor chip. The package includes a third side surface and a fourth side surface the third side surface is provided between the upper surface and the lower surface of the package. The second lead terminal protrudes from the third side surface. The third side surface has a fourth surface, a fifth surface, and a sixth surface the fourth surface is continuous with the
upper surface of the package and is provided in an oblique direction with respect to the upper surface of the package. The fifth surface is continuous with the fourth surface and is provided in a direction parallel to the upper surface of the package. The sixth surface is continuous with the fifth surface and is provided in a direction orthogonal
to the upper surface of the package. The fourth side surface is provided between
the upper surface and the lower surface, and the second lead terminal does not protrude from the fourth side surface in claim 9.
Plating the lead frame after forming the package. Cutting and singulating the lead frame to obtain the semiconductor device after plating the lead frame in claim 17.
The prior art made of record and not relied upon is cited primarily to show the
product of the instant invention.
Conclusion
9. Any inquiry concerning the communication or earlier communications from the
examiner should be directed to Alonzo Chambliss whose telephone number is (571)
272-1927.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's
supervisor, Jacob Y. Choi can be reached on (469) 295-9060. The fax phone number
for the organization where this application or proceeding is assigned is (571) 273-8300.
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AC/September 16, 2026 /Alonzo Chambliss/
Primary Examiner, Art Unit 2897
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