DETAILED ACTION
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/05/2024 was filed after the mailing date of the application. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 9, 13-14 are rejected under 35 U.S.C. 102(2)(a) as being anticipated by Lim et al., U.S. Pub. No. 2025/0280544.
Regarding claim 1, Lim discloses (See Figs. 1, 2A-2B, 3A-3B):
A semiconductor device comprising:
a source structure (SS, Fig. 2A includes substrate 200, conductive layers 202/204),
a stack structure including interlayer (stack structure, Fig. 2A-2B) insulating layers 120 and gate electrodes 185 stacked in a first direction, the first direction being perpendicular to an upper surface of the source structure,
a channel structure (CH layer 150, Figs. 2A-3B) including a back gate electrode penetrating through the stack structure and the source structure in the first direction, a channel layer between the back gate electrode (BGE 130) and the gate electrodes, and a gate dielectric structure 160 between the channel layer 150 and the gate electrodes (the insulating layer 131 separates the channel layer from BGE), and
a back gate structure (BGS) on the stack structure and electrically connected to the back gate electrode,
wherein the back gate structure (BGS) includes a protrusion portion BGS_P penetrating through a side surface of the channel structure and contacting the back gate electrode BGE (BGS_P entering laterally from outside CH 150, through the channel sidewall layers, and contacting electrode 130, the portion of BGL extending into CH is considered as protrusion portion BGS_P).
Regarding claim 2, Lim discloses:
wherein the interlayer insulating layers include an upper interlayer insulating layer on an uppermost gate electrode among the gate electrodes,
the back gate structure BGS further includes a first portion BGS1 extending on the upper interlayer insulating layer in a second direction (BGL extending in X direction), the second direction being perpendicular to the first direction, and
the protrusion portion BGS-P protrudes from a side surface of the first portion (portion/extension of BGL extending into CH toward BGE) to penetrate through the gate dielectric structure 160 and the channel layer (BGS/BGL path through the channel structure, Figs. 2A-2B, 3A-3B, BGS divides CH into CP1 and CP2), the protrusion portion being in contact with a side surface of the back gate electrode (BGL connects to BGE), the gate dielectric structure 160 being adjacent to a side surface of the channel structure 150 that is in contact with the side surface of the first portion (Fig. 3A: BGS2 is the horizontal member coming from the left, and BGS_P is the portion that continues horizontally into the channel structure until it contacts central back-gate electrode 130).
Regarding claim 3, Lim discloses wherein the channel includes (Fig. 3A):
The back gate electrode 130 is a central region of a channel hole defined through the stack structure in the first direction,
a first insulting layer 131 configured to surround the back gate electrode 130,
the channel layer CH/channel hole 150 configured to surround the first insulating layer 131,
the gate dielectric structure 160 configured to surround the channel layer 150, the gate dielectric structure being on a side wall of the channel hole, and
a channel pad pattern 157 on an upper surface of the back gate electrode, the channel pad pattern 157 being inside the channel hole, the channel pad pattern 157 overlapping the back gate electrode 130 in the first direction.
Regarding claim 4, Lim discloses wherein the channel structure further includes a channel insulation pattern extending from the channel layer and surrounding the protrusion portion (Fig. 3A, left side wherein BGS_P inters the channel, insulation must be part of the channel structure, extend from the channel layer and surround BGS_P).
Regarding claim 9, Lim discloses wherein the gate dielectric includes ferroelectric, a second insulating layer including a same material, as the first insulating layer between the ferroelectric layer and the channel layer or between the ferroelectric layer and the gate electrode [0081]-[0084].
Regarding claims 13-14, Lim discloses wherein the back gate structure and the back gate electrode include the same material (Figs.2a-3b).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-7, 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Lim et al., U.S. Pub. No. 2025/0280544.
Regarding claims 5, 6, 7, Lim fails to disclose wherein an upper end of the channel insulating pattern is lower than a lower surface of the channel pad pattern, and a lower end of the channel insulating pattern is higher than an upper surface of the uppermost gate electrode, among the gate electrodes, wherein the protrusion portion has first length in a region penetrating through the channel, a second length penetrating through the gate, the second length being greater than the first length, wherein the first portion extends to the upper interlayer insulating layer and has thickness in the first direction, the thickness being greater than the first length. However, the selection of such parameters such as energy, concentration, temperature, time, molar fraction, depth, thickness, etc., would have been obvious and involve routine optimization which has been held to be within the level of ordinary skill in the art. "Normally, it is to be expected that a change in energy, concentration, temperature, time, molar fraction, depth, thickness, etc., or in conbination of the parameters would be an unpatentable modification. Under some circumstances, however, changes such as these may impart patentability to a process if the particular ranges claimed produce a new and unexpected result which is different in kind and not merely degree from the results of the prior art ... such ranges are termed "critical ranges and the applicant has the burden of proving such criticality.... More particularly, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller 105 USPQ233, 255 (CCPA 1955). See also In re Waite 77 USPQ 586 (CCPA 1948); In re Scherl 70 USPQ 204 (CCPA 1946); In re Irmscher 66 USPQ 314 (CCPA 1945); In re Norman 66 USPQ 308 (CCPA 1945); In re Swenson 56 USPQ 372 (CCPA 1942); In re Sola 25 USPQ 433 (CCPA 1935); In re Dreyfus 24 USPQ 52 (CCPA 1934).
Allowable Subject Matter
Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior made of record and considered pertinent to the applicant’s disclosure does not teach or suggest the claimed limitations having the device of claims 6, 3, 2 and 1, wherein the first portion includes a conductive material layer connected to the protrusion portion, and etch stop layers disposed on an upper portion and a lower portion of the conductive material layer, and a thickness of the conductive material layer in the first direction is equal to the first length of the protrusion portion.
Claims 15-20 are allowed. The following is an examiner’s statement of reason for allowance: None of the references of record teaches or suggests the claimed having channel structures each including a back gate electrode, a channel layer, and a gate dielectric structure, the back gate electrode penetrating through the stack structure and the source structure in the first dielectric, the channel layer being between the back gate electrode and the gate electrodes, and the gate dielectric structure being between the channel layer and the gate electrodes in the first region, separating regions penetrating through the stack structure, the separation regions spaced apart from other in a second direction and extending in a third direction, the second direction being perpendicular to the first direction, the third direction being perpendicular to the first and second directions, a back gate structure including a first portion and a second portion, the first portion extending between the separation regions spaced apart from each other on the stack structure in the second direction, the first portion penetrating through a side surface of the channel structures and electrically connected to the back gate electrode, and the second portion alternating with the first portion in the third direction and extending in the second direction, and a back gate contact connected to the back gate structure to transmit a back gate voltage, wherein a thickness of the first portion is greater than a thickness of the second portion.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THAO P LE whose telephone number is (571)272-1785. The examiner can normally be reached on Monday-Friday 9AM-6PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached on 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306.
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/THAO P LE/Primary Examiner, Art Unit 2818
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