DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
This office acknowledges receipt of the following items from the applicant: Information Disclosure Statement (IDS) filed on 5 September 2024. The references cited on the PTOL 1449 form have been considered.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “wherein each of the plurality of third bonding parts (61) includes a flat section bonded to the plurality of first semiconductor elements (10A)” of claim 3 must be shown or the feature(s) canceled from the claim(s). The applicant discloses that the third bonding parts (61) includes a flat section bonded to the plurality of second semiconductor elements (10B), not the first semiconductor elements (10A). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 3-15 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 3, the applicant’s disclosure does not support the recitation of “wherein each of the plurality of third bonding parts (61) includes a flat section bonded to the plurality of first semiconductor elements (10A)” of claim 3 must be shown or the feature(s) canceled from the claim(s). The applicant discloses that the third bonding parts (61) includes a flat section bonded to the plurality of second semiconductor elements (10B), not the first semiconductor elements (10A). Claims 4-15 include and do not cure the deficiencies of claim 3.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-9 and 12-15 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Wu et al. (U.S. Patent Application Publication 2024/0047433).
The applied reference has a common assignee and one common inventor with the instant application. Based upon the earlier effectively filed date (15 June 2021) of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Referring to Claim 1, Wu teaches in Fig. 1-6 for example, a semiconductor device comprising: a supporting substrate (3) including: a first conductive part (2B) that includes a first obverse surface facing a first side in a thickness direction (z) and is located on a first side in a first direction (x) orthogonal to the thickness direction (z); and
a second conductive part (2A) that includes a second obverse surface facing the first side in the thickness direction (z) and is located on a second side in the first direction (x); a plurality of first semiconductor elements (10B) mounted on the first conductive part (2B) and each having a switching function, the plurality of first semiconductor elements (10B) being aligned in a second direction (y) orthogonal to both the thickness direction (z) and the first direction (x); a plurality of second semiconductor elements (10A) mounted on the second conductive part (2A) and each having a switching function, the plurality of second semiconductor elements (10A) being aligned in the second direction (y); a first terminal (41) protruding toward the first side in the first direction (x) relative to the first conductive part (2B); a first conductive member (6) electrically connecting the plurality of first semiconductor elements (10B) and the second conductive part (2A); a second conductive member (5) electrically connecting the plurality of second semiconductor elements (10A) and the first terminal (41); and
a sealing resin (8) covering the plurality of first semiconductor elements (10B), the plurality of second semiconductor elements (10A), the first conductive member (6), the second conductive member (5), a portion of the supporting substrate (3), and a portion of the first terminal (41), wherein the first conductive member (6) includes a plurality of first bonding parts (62) bonded to the respective first semiconductor elements (10B) and a second bonding part (63) bonded to the second conductive part (2A), the second conductive member (5) includes a plurality of third bonding parts (54) bonded to the respective second semiconductor elements (10A), each of the plurality of first bonding parts (62) includes a first end section located farthest on a second side in the thickness direction (z), each of the plurality of third bonding parts (54) includes a third end section located farthest on the second side in the thickness direction (z), and positions of at least either the first end sections of the plurality of first bonding parts (62) or the third end sections of the plurality of third bonding parts (54) in the thickness direction (z) are designed to conform to warping of the supporting substrate (3) as shown.
Referring to Claim 2, Wu further teaches wherein the positions of the third end sections of the plurality of third bonding parts (54) in the thickness direction (z) are designed to conform to warping of the supporting substrate (3) as shown.
As insofar as claim 3 is supported, Wu further teaches wherein each of the plurality of third bonding parts (54) includes a flat section bonded to the plurality of second semiconductor elements (10A).
Referring to Claim 4, Wu further teaches a second terminal (42) protruding toward the first side in the first direction (x) relative to the first conductive part (2B), the second terminal (42) being located on a second side in the second direction (y) relative to the first terminal (41), wherein the second conductive member (5) includes: a first path part (514) located between the plurality of third bonding parts (54) and the first terminal (41); a second path part (534) located between the plurality of third bonding parts (54) and the second terminal (42); a plurality of third path parts (522) each extending in the first direction (x); and a fourth path part (521) extending in the second direction (y) and connected to ends of the plurality of third path parts (522) on the first side in the first direction (x), the first path part (514), and the second path part (534), and the plurality of third bonding parts (54) are connected to the plurality of third path parts (522).
Referring to Claim 5, Wu further teaches wherein the plurality of third path parts (522) are located at a same position in the thickness direction (z), and distances from the flat sections of the plurality of third bonding parts (54) to the third path parts (522) in the thickness direction (z) are designed to conform to warping of the supporting substrate (3) as shown.
Referring to Claim 6, Wu further teaches in Fig. 2 for example, wherein each of the third bonding parts (54) includes a first inclined section located between one of the third path parts (54) and one of the flat sections.
Referring to Claim 7, Wu further teaches wherein a thickness of the first inclined sections is equal to or less than a thickness of the flat sections.
Referring to Claim 8, Wu further teaches wherein the thickness of the first inclined sections is equal to or less than a thickness of the third path parts (54).
Referring to Claim 9, Wu further teaches wherein a thickness of the flat sections is equal to a thickness of the third path parts (54).
Referring to Claim 12, Wu further teaches wherein each of the third bonding parts (54) includes: two flat sections each bonded to the second semiconductor elements (10A) and aligned in the second direction (y); and two first inclined sections connected to outer ends of the two flat sections in the second direction (y).
Referring to Claim 13, Wu further teaches wherein each of the first inclined sections extends from one of the third path parts (522) in the second direction (y) as viewed in the thickness direction (z).
Referring to Claim 14, Wu further teaches wherein the two flat sections of each of the third bonding parts (54) are spaced apart in the second direction (y).
Referring to Claim 15, Wu further teaches in Fig. 18 (par. 36) wherein each of the plurality of third bonding parts (54) includes a projection (19) that protrudes from one of the flat sections toward the second side in the thickness direction (z).
Claims 1-15 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Yasunishi (U.S. Patent Application Publication 2024/0321693).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date (20 January 2020) of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Referring to Claim 1, Yasunishi teaches in Fig. 1-6 for example, a semiconductor device comprising: a supporting substrate (3) including: a first conductive part (32A) that includes a first obverse surface facing a first side in a thickness direction (z) and is located on a first side in a first direction (x) orthogonal to the thickness direction (z); and
a second conductive part (32B) that includes a second obverse surface facing the first side in the thickness direction (z) and is located on a second side in the first direction (x); a plurality of first semiconductor elements (10A) mounted on the first conductive part (32A) and each having a switching function, the plurality of first semiconductor elements (10A) being aligned in a second direction (y) orthogonal to both the thickness direction (z) and the first direction (x); a plurality of second semiconductor elements (10B) mounted on the second conductive part (32B) and each having a switching function, the plurality of second semiconductor elements (10B) being aligned in the second direction (y); a first terminal (41) protruding toward the first side in the first direction (x) relative to the first conductive part (2B); a first conductive member (5) electrically connecting the plurality of first semiconductor elements (10A) and the second conductive part (32B); a second conductive member (6) electrically connecting the plurality of second semiconductor elements (10B) and the first terminal (41); and
a sealing resin (8) covering the plurality of first semiconductor elements (10A), the plurality of second semiconductor elements (10B), the first conductive member (5), the second conductive member (6), a portion of the supporting substrate (3), and a portion of the first terminal (41), wherein the first conductive member (5) includes a plurality of first bonding parts (52) bonded to the respective first semiconductor elements (10A) and a second bonding part (53) bonded to the second conductive part (32B), the second conductive member (6) includes a plurality of third bonding parts (61) bonded to the respective second semiconductor elements (10B), each of the plurality of first bonding parts (52) includes a first end section located farthest on a second side in the thickness direction (z), each of the plurality of third bonding parts (61) includes a third end section located farthest on the second side in the thickness direction (z), and positions of at least either the first end sections of the plurality of first bonding parts (52) or the third end sections of the plurality of third bonding parts (61) in the thickness direction (z) are designed to conform to warping of the supporting substrate (3) as shown.
Referring to Claim 2, Yasunishi further teaches wherein the positions of the third end sections of the plurality of third bonding parts (61) in the thickness direction (z) are designed to conform to warping of the supporting substrate (3) as shown.
As insofar as claim 3 is supported, Yasunishi further teaches wherein each of the plurality of third bonding parts (61) includes a flat section bonded to the plurality of second semiconductor elements (10B).
Referring to Claim 4, Yasunishi further teaches a second terminal (42) protruding toward the first side in the first direction (x) relative to the first conductive part (32A), the second terminal (42) being located on a second side in the second direction (y) relative to the first terminal (41), wherein the second conductive member (6) includes: a first path part (64) located between the plurality of third bonding parts (61) and the first terminal (41); a second path part (65) located between the plurality of third bonding parts (61) and the second terminal (42); a plurality of third path parts (66) each extending in the first direction (x); and a fourth path part (67) extending in the second direction (y) and connected to ends of the plurality of third path parts (66) on the first side in the first direction (x), the first path part (64), and the second path part (65), and the plurality of third bonding parts (61) are connected to the plurality of third path parts (66).
Referring to Claim 5, Yasunishi further teaches wherein the plurality of third path parts (66) are located at a same position in the thickness direction (z), and distances from the flat sections of the plurality of third bonding parts (61) to the third path parts (66) in the thickness direction (z) are designed to conform to warping of the supporting substrate (3) as shown.
Referring to Claim 6, Yasunishi further teaches in Fig. 2 for example, wherein each of the third bonding parts (61) includes a first inclined section located between one of the third path parts (66) and one of the flat sections.
Referring to Claim 7, Yasunishi further teaches wherein a thickness of the first inclined sections is equal to or less than a thickness of the flat sections.
Referring to Claim 8, Yasunishi further teaches wherein the thickness of the first inclined sections is equal to or less than a thickness of the third path parts (66).
Referring to Claim 9, Yasunishi further teaches wherein a thickness of the flat sections is equal to a thickness of the third path parts (66).
Referring to Claim 10, Yasunishi further teaches wherein the first terminal (41) and the second conductive member (6) are integrally formed (par. 66).
Referring to Claim 11, Yasunishi further teaches wherein the second terminal (42) and the second conductive member (6) are integrally formed (par. 66).
Referring to Claim 12, Yasunishi further teaches wherein each of the third bonding parts (61) includes: two flat sections each bonded to the second semiconductor elements (10B) and aligned in the second direction (y); and two first inclined sections connected to outer ends of the two flat sections in the second direction (y).
Referring to Claim 13, Yasunishi further teaches wherein each of the first inclined sections extends from one of the third path parts (66) in the second direction (y) as viewed in the thickness direction (z).
Referring to Claim 14, Yasunishi further teaches wherein the two flat sections of each of the third bonding parts (61) are spaced apart in the second direction (y).
Referring to Claim 15, Yasunishi further teaches wherein each of the plurality of third bonding parts (61) includes a projection (69) that protrudes from one of the flat sections toward the second side in the thickness direction (z).
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EARL N TAYLOR whose telephone number is (571)272-8894. The examiner can normally be reached M-F, 9:00am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached on (571) 272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EARL N TAYLOR/Primary Examiner, Art Unit 2896
EARL N. TAYLOR
Primary Examiner
Art Unit 2896
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