DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-25 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Regarding independent claims 1, 7, 13, 17, and 22, it is unclear how a vertical wire made of the stacked metal structures can have a longitudinal (vertical) axis perpendicular with a stacking (vertical) direction of the stacked metal structures.
For the purposes of examination with regard to the prior art, “perpendicular” will be treated as --parallel--.
Claims 2-6, because they are dependent on claim 1, inherit the deficiency of claim 1.
Claims 8-12, because they are dependent on claim 7, inherit the deficiency of claim 1.
Claims 14-16, because they are dependent on claim 13, inherit the deficiency of claim 1.
Claims 18-21, because they are dependent on claim 17, inherit the deficiency of claim 1.
Claims 23-25, because they are dependent on claim 22, inherit the deficiency of claim 1.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sio et al. (US 20230387035), corresponding to TW 202123403 A cited by Applicant in the Information Disclosure Statement filed on July 8, 2026.
Regarding claim 1, Sio teaches, in Fig. 2, a semiconductor device (200, [0019]), comprising:
a high voltage electrode (274, [0022]) to carry a voltage greater than other metal structures (276, [0022]) on the semiconductor device; and
a high voltage column (M8, 205, M1, 206, 208, and 203, [0019]) connected to the high voltage electrode (274), the high voltage column including:
stacked metal structures (M8, 205, M1, 206, and 208) layered to provide a vertical wire having a longitudinal axis substantially perpendicular with a stacking (vertical) direction of the stacked metal structures (see Fig. 2).
Regarding claim 2, Sio further teaches, in Fig. 2, that the stacked metal structures (M8, 205, M1, 206, and 208) include a combination of vias (205 and 206, [0019]) and metal lines (M1 and M8, [0019]).
Regarding claim 3, Sio further teaches, in Fig. 2, in Fig. 2, that the combination of vias (205 and 206) and metal lines (M1 and M8) include an alternating arrangement between the vias and the metal lines (see Fig. 2).
Regarding claim 4, Sio further teaches, in Fig. 2, that the stacked metal structures (M8, 205, M1, 206, and 208) include a super via (205, [0019]).
Regarding claim 5, Sio further teaches, in Fig. 2, that the stacked metal structures (M8, 205, M1, 206, and 208) include array vias (208, see Fig. 2, [0019]).
Regarding claim 6, Sio further teaches, in Fig. 2, that the high voltage column (M8, 205, M1, 206, 208, and 203) includes a dielectric column (203, [0019]) that is free of other metal structures and surrounds the stacked metal structures (M8, 205, M1, 206, and 208) (see Fig. 2).
Regarding claim 7, Sio teaches, in Fig. 2, a semiconductor device (200, [0019]), comprising:
a backside power distribution network (270, [0020]) including a high voltage electrode (274, [0022]) to carry a voltage greater than other metal structures (276, [0022]) on the semiconductor device; and
a high voltage column (M8, 205, M1, 206, 208, and 203, [0019]) connected to the high voltage electrode (274) (see Fig. 2, [0026]), the high voltage column traversing a region of lower voltage metal structures (276, [0022]) in the backside power distribution network (270) (see Fig. 2, [0019], the column is present on both the left and right sides) and including:
stacked metal structures (M8, 205, M1, 206, and 208) layered to provide a vertical wire (see Fig. 2) having a longitudinal axis substantially perpendicular with a stacking (vertical) direction of the stacked metal structures.
Regarding claim 8, Sio further teaches, in Fig. 2, that the stacked metal structures (M8, 205, M1, 206, and 208) include a combination of vias (205 and 206, [0019]) and metal lines (M1 and M8, [0019]).
Regarding claim 9, Sio further teaches, in Fig. 2, that the combination of vias (205 and 206) and metal lines (M1 and M8) include an alternating arrangement between the vias and the metal lines (see Fig. 2).
Regarding claim 10, Sio further teaches, in Fig. 2, that the stacked metal structures (M8, 205, M1, 206, and 208) include a super via (205, [0019]).
Regarding claim 11, Sio further teaches, in Fig. 2, that the stacked metal structures (M8, 205, M1, 206, and 208) include array vias (208, see Fig. 2, [0019]).
Regarding claim 12, Sio further teaches, in Fig. 2, that the high voltage column (M8, 205, M1, 206, 208, and 203) includes a dielectric column (203, [0019]) that is free of other metal structures and surrounds the stacked metal structures (M8, 205, M1, 206, and 208) (see Fig. 2).
Regarding claim 13, Sio teaches, in Fig. 2, a semiconductor device (200, [0019]), comprising:
a high voltage electrode (274, [0022]) to carry a voltage greater than other metal structures (276, [0022]) on the semiconductor device; and
a high voltage column (M8, 205, M1, 206, 208, and 203, [0019]) connected to the high voltage electrode (274) (see Fig. 2, [0026]), including:
stacked metal structures (M8, 205, M1, 206, and 208) layered to provide a vertical wire disposed over the high voltage electrode (274) and having a longitudinal axis substantially perpendicular with a stacking (vertical) direction of the stacked metal structures, the stacked metal structures including vias (205 and 206, [0019]) and metal lines (M1 and M8, [0019]) stacked in an alternating arrangement (see Fig. 2).
Regarding claim 14, Sio further teaches, in Fig. 2, that the stacked metal structures (M8, 205, M1, 206, and 208) include a super via (205, [0019]).
Regarding claim 15, Sio further teaches, in Fig. 2, that the stacked metal structures (M8, 205, M1, 206, and 208) include array vias (208, see Fig. 2, [0019]).
Regarding claim 16, Sio further teaches, in Fig. 2, that the high voltage column (M8, 205, M1, 206, 208, and 203) includes a dielectric column (203, [0019]) that is free of other metal structures and surrounds the stacked metal structures (M8, 205, M1, 206, and 208) (see Fig. 2).
Regarding claim 17, Sio teaches, in Fig. 2, a semiconductor device (200, [0019]), comprising:
a high voltage electrode (274, [0022]) to carry a voltage greater than other metal structures (276, [0022]) on the semiconductor device; and
a high voltage column (M8, 205, M1, 206, 208, and 203, [0019]) connected to the high voltage electrode (274) (see Fig. 2, [0026]), the high voltage column including:
stacked metal structures (M8, 205, M1, 206, and 208) layered to provide a vertical wire having a longitudinal axis substantially perpendicular with a stacking (vertical) direction of the stacked metal structures (see Fig. 2); and
a dielectric column (203, [0019]) that is free of other metal structures and surrounds the stacked metal structures (M8, 205, M1, 206, and 208) (see Fig. 2).
Regarding claim 18, Sio further teaches, in Fig. 2, that the stacked metal structures (M8, 205, M1, 206, and 208) include a combination of vias (205 and 206, [0019]) and metal lines (M1 and M8, [0019]).
Regarding claim 19, Sio further teaches, in Fig. 2, that the combination of vias (205 and 206) and metal lines (M1 and M8) include an alternating arrangement between the vias and the metal lines (see Fig. 2).
Regarding claim 20, Sio further teaches, in Fig. 2, that the stacked metal structures (M8, 205, M1, 206, and 208) include a super via (205, [0019]).
Regarding claim 21, Sio further teaches, in Fig. 2, that the stacked metal structures (M8, 205, M1, 206, and 208) include array vias (208, see Fig. 2, [0019]).
Regarding claim 22, Sio teaches, in Fig. 2, a semiconductor device (200, [0019]), comprising:
a backside power distribution network (270, [0020]) including a high voltage electrode (274, [0022]) to carry a voltage greater than other metal structures (276, [0022]) on the semiconductor device; and
a high voltage column (M8, 205, M1, 206, 208, and 203, [0019]) connected to the high voltage electrode (274) (see Fig. 2, [0026]), the high voltage column traversing the backside power distribution network (270) (see Fig. 2, [0019], the column is present on both the left and right sides) and including:
stacked metal structures (M8, 205, M1, 206, and 208) layered to provide a vertical wire (see Fig. 2) disposed over the high voltage electrode (274) and having a longitudinal axis substantially perpendicular with a stacking (vertical) direction of the stacked metal structures, the stacked metal structures include a combination of vias (205 and 206, [0019]) and metal lines (M1 and M8, [0019]); and
a dielectric column (203, [0019]) that is free of other metal structures and surrounds the stacked metal structures (M8, 205, M1, 206, and 208) (see Fig. 2).
Regarding claim 23, Sio further teaches, in Fig. 2, that the combination of vias (205 and 206) and metal lines (M1 and M8) include an alternating arrangement between the vias and the metal lines (see Fig. 2).
Regarding claim 24, Sio further teaches, in Fig. 2, that the stacked metal structures (M8, 205, M1, 206, and 208) include a super via (205, [0019]).
Regarding claim 25, Sio further teaches, in Fig. 2, that the stacked metal structures (M8, 205, M1, 206, and 208) include array vias (208, see Fig. 2, [0019]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIKA HEERA SON whose telephone number is 703-756-4644. The examiner can normally be reached Monday - Friday 12:30-9 PM ET.
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/ERIKA H SON/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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