Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are presented for examination.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 14 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 14 recites the limitation "the vertical transistor" in lines 1-2. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-8 and 10-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pillarisetty et al. (US Pub. No. 2020/0058798 A1), hereafter referred to as Pillarisetty, in view of Matsubayashi (US Pub. No. 2012/0228688 A1).
As to claim 1, Pillarisetty discloses a semiconductor device (fig 3A-B), comprising:
vertical transistors (100), one or more of the vertical transistors comprising:
a channel region (103) comprising an oxide semiconductor material ([0023]) located between a source region (102) and a drain region (104);
a dielectric material (108) on sidewalls of the channel region (103); and
an electrode (106) adjacent to the dielectric material (108),
a pitch of the vertical transistors within a range of from about 10 nm to about 40 nm ([0046], [0152]).
Pillarisetty does not explicitly disclose that the vertical transistors are arranged adjacent to a control logic region.
Nonetheless, Matsubayashi discloses vertical transistors (fig 4, 205) arranged adjacent to a control logic region (203).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to include the vertical transistors of Pillarisetty adjacent to the control logic region taught in Matsubayashi since this will improve control operation of the memory cell.
As to claim 2, Pillarisetty in view of Matsubayashi disclose the semiconductor device of claim 1 (paragraphs above).
Pillarisetty further discloses wherein the pitch of the vertical transistors is between about 20 nm and about 25 nm ([0152]).
As to claim 3, Pillarisetty in view of Matsubayashi disclose the semiconductor device of claim 1 (paragraphs above).
Pillarisetty further discloses wherein the pitch of the one or more of the vertical transistors is between about 15 nm and about 25 nm ([0152]).
As to claim 4, Pillarisetty in view of Matsubayashi disclose the semiconductor device of claim 1 (paragraphs above).
Pillarisetty further discloses wherein the oxide semiconductor material comprises indium gallium zinc oxide ([0023]).
As to claim 5, Pillarisetty in view of Matsubayashi disclose the semiconductor device of claim 1 (paragraphs above).
Pillarisetty further discloses wherein a height of the channel region is between about 40 nm and about 100 nm ([0029]).
As to claim 6, Pillarisetty in view of Matsubayashi disclose the semiconductor device of claim 1 (paragraphs above).
Pillarisetty further discloses wherein an angle of sidewalls of the one or more of the vertical transistors is between about 80° and about 90° (fig 3A-B, sidewalls of 100).
As to claim 7, Pillarisetty in view of Matsubayashi disclose the semiconductor device of claim 1 (paragraphs above).
Pillarisetty further discloses wherein the vertical transistors are substantially free of polymer material ([0023]; no polymer is taught to be included in the transistor components).
As to claim 8, Pillarisetty discloses a semiconductor device (figs 3A-B), comprising:
vertical transistors (100), the vertical transistors comprising:
a channel region (103) comprising an oxide semiconductor material ([0023]) located vertically between a source region (102) and a drain region (104), the oxide semiconductor material comprising an indium gallium zinc oxide (IGZO) material ([0023]);
a dielectric material (108) adjacent to the channel region (103); and
an electrode (106) adjacent to the dielectric material (108),
a pitch of the vertical transistors in a first direction within a range from about 10 nm to about 40 nm ([0046]; [0152]) and a pitch of the vertical transistors in a second direction perpendicular to the first direction within a range from about 20 nm to about 50 nm ([0046]; [0152]).
Pillarisetty does not explicitly disclose that the vertical transistors are arranged adjacent to a control logic region.
Nonetheless, Matsubayashi discloses vertical transistors (fig 4, 205) arranged adjacent to a control logic region (203).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to include the vertical transistors of Pillarisetty adjacent to the control logic region taught in Matsubayashi since this will improve control operation of the memory cell.
As to claim 10, Pillarisetty in view of Matsubayashi disclose the semiconductor device of claim 8 (paragraphs above).
Pillarisetty does not disclose wherein the vertical transistors are between the control logic region and a capacitor region.
Nonetheless, Matsubayashi discloses wherein the vertical transistors (fig 4, 205) are between the control logic region (203) and a capacitor region (207).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to include the vertical transistors of Pillarisetty between the control logic region and capacitor region as taught by Matsubayashi since this will provide improved control and operation of a DRAM cell.
As to claim 11, Pillarisetty in view of Matsubayashi disclose the semiconductor device of claim 8 (paragraphs above).
Pillarisetty further discloses wherein the dielectric material (108) adjacent to the channel region (103) comprises an oxide material on sidewalls of the channel region ([0067]).
As to claim 12, Pillarisetty in view of Matsubayashi disclose the semiconductor device of claim 8 (paragraphs above).
Pillarisetty further discloses a word line laterally adjacent to the channel region ([0027]).
Claim(s) 9 and 15-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pillarisetty in view of Matsubayashi and further in view of Nomura et al. “Thin-film transistor fabricated in single crystalline transparent oxide semiconductor”, Science Vol. 300, May 23, 2003; provided by Applicant on IDS received 9/5/2024), hereafter referred to as Nomura.
As to claim 9, Pillarisetty in view of Matsubayashi disclose the semiconductor device of claim 8 (paragraphs above).
Pillarisetty in view of Matsubayashi do not disclose wherein the oxide semiconductor material comprises an In:Ga:ZnO ratio of 1:1:1:4, an In2O3:Ga2O3:ZnO ratio of 2:2:1, or InGa3(ZnO)5.
Nonetheless, Nomura discloses wherein an oxide semiconductor material comprises an In:Ga:ZnO ratio of 1:1:1:4, an In2O3:Ga2O3:ZnO ratio of 2:2:1, or InGa3(ZnO)5 (abstract).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to use the specific IGZO composition taught by Nomura as the IGZO disclosed by Pillarisetty since this will provide a sufficient on-to-off current ratio and field-effect mobility for the channel of the FET.
As to claim 15, Pillarisetty discloses an electronic device (fig 3A-B), comprising
a transistor region (100), the transistor region comprising one or more vertical transistors (100) comprising:
a vertical channel (103) comprising an oxide semiconductor material ([0023]) located vertically between a source region (102) and a drain region (104) of the one or more vertical transistors (100), the oxide semiconductor material comprising InGaZO ([0023]);
a dielectric material (108) adjacent to the vertical channel (103); and
an electrode (106) adjacent to the dielectric material (108),
a pitch in a first direction of the one or more vertical transistors within a range from about 10 nm to about 40 nm and a pitch in a second direction perpendicular to the first direction of the vertical transistors within a range from about 20 nm to about 50 nm ([0046]; [0152]).
Pillarisetty does not explicitly disclose that the vertical transistors are electrically connected to a control logic region.
Nonetheless, Matsubayashi discloses vertical transistors (fig 4, 205) electrically connected to a control logic region (203).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to include the vertical transistors of Pillarisetty adjacent to the control logic region taught in Matsubayashi since this will improve control operation of the memory cell.
Pillarisetty in view of Matsubayashi do not disclose wherein the oxide semiconductor material comprises an InGa3(ZnO)5.
Nonetheless, Nomura discloses wherein the oxide semiconductor material comprises an InGa3(ZnO)5 (abstract).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to use the specific IGZO composition taught by Nomura as the IGZO disclosed by Pillarisetty since this will provide a sufficient on-to-off current ratio and field-effect mobility for the channel of the FET.
As to claim 16, Pillarisetty in view of Matsubayashi and Nomura disclose the semiconductor device of claim 15 (paragraphs above).
Matsubayashi further discloses wherein the transistor region is vertically adjacent to the control logic region (fig 4).
As to claim 17, Pillarisetty in view of Matsubayashi and Nomura disclose the semiconductor device of claim 15 (paragraphs above).
Pillarisetty further discloses wherein sidewalls of the one or more vertical transistors are substantially perpendicular (fig 3A-B).
As to claim 18, Pillarisetty in view of Matsubayashi and Nomura disclose the semiconductor device of claim 15 (paragraphs above).
Pillarisetty further discloses wherein a height of the vertical channel is between about 40 nm and about 80 nm ([0029]) and a width of the one or more vertical transistors ranges between about 5 nm and about 40 nm ([0029]).
As to claim 19, Pillarisetty in view of Matsubayashi and Nomura disclose the semiconductor device of claim 15 (paragraphs above).
Pillarisetty further discloses wherein a distance between adjacent vertical transistors of the one or more vertical transistors ranges between about 20 nm and about 100 nm ([0046]).
As to claim 20, Pillarisetty in view of Matsubayashi and Nomura disclose the semiconductor device of claim 15 (paragraphs above).
Pillarisetty further discloses a conductive word line electrically connecting each vertical transistor of a row of vertical transistors to each other ([0027]).
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pillarisetty in view of Matsubayashi and further in view of Sandhu (US Pub. No. 2013/0069052 A1).
As to claim 13, Pillarisetty in view of Matsubayashi disclose the semiconductor device of claim 8 (paragraphs above).
Pillarisetty does not explicitly disclose that the IGZO in the channel region exhibits an off-state current leakage of about 1 x 10-24 A and an on-to-off current ratio of about 1,000,000,000 to 1.
Nonetheless Sandhu discloses that IGZO in a channel region exhibits an off-state current leakage of about 1 x 10-24 A and an on-to-off current ratio of about 1,000,000,000 to 1 ([0034]).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention that IGZO in a channel region of Pillarisetty exhibits the current ratio and leakage as taught by Sandhu since these channel structures are used in the same FET structure.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pillarisetty in view of Matsubayashi and further in view of Huang (US Pub. No. 2010/0052029 A1).
As to claim 14, Pillarisetty in view of Matsubayashi disclose the semiconductor device of claim 8 (paragraphs above).
Matsubayashi further discloses wherein the drain region of the vertical transistor is individually in electrical communication with an electrode of a capacitor vertically overlying the vertical transistor ([0046]).
Pillarisetty in view of Matsubayashi do not disclose the capacitor having a larger vertical dimension than a lateral dimension thereof.
Nonetheless, Huang discloses a similar structure with a vertical transistor (fig 1, 12) vertically below a capacitor (18), the capacitor having a larger vertical dimension than a lateral dimension thereof (fig 1, 18).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to replace the capacitor of Pillarisetty in view of Matsubayashi with the trench capacitor taught by Huang since this will improve the utilization of space of the chip and reduce memory cell size in horizontal dimensions.
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pub. No. 2018/0076093 A1 fig 20 discloses the limitations of claim 1 except for the oxide semiconductor limitation.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAUN M CAMPBELL whose telephone number is (571)270-3830. The examiner can normally be reached on MWFS: 7:30-6pm Thurs 1-2pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Purvis, Sue can be reached at (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SHAUN M CAMPBELL/Primary Examiner, Art Unit 2893 9/1/2026
Prosecution Insights