Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to application No. 18/826,146 filed on October 25, 2024.
Priority
3. Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
4. Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS have been considered.
Specification
5. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: “Semiconductor Device Comprising Transistor and Diode Sections Including Drift Region”.
Claim Rejections - 35 USC § 102
6. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
7. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
8. Claims 1-4, 6-9, 10-11, 16-20 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by NAITO (US 2017/0236908 A1).
Regarding independent claim 1, NAITO teaches a semiconductor device comprising (100, Figs. 1-3):
a drift region (18, Fig. 3) of a first conductivity-type (N-) provided in a semiconductor substrate (10, para [0092]);
a base region (14, Fig. 3) of a second conductivity-type (P-) in contact with an upper surface of the semiconductor substrate (10) and provided above the drift region (18);
a first high-concentration lower surface region (28, Fig. 3) of the first conductivity-type (N+) that is provided at a lower surface of the semiconductor substrate (10) and has a doping concentration higher than (N+ vs. N- concentrations) a doping concentration (N-) of the drift region (18);
a second high-concentration lower surface region (22, Fig. 3) of the second conductivity-type (P+) that is provided at the lower surface of the semiconductor substrate (10) and has a doping concentration higher than (P+ vs. P- concentrations) a doping concentration (P-) of the base region (14); and
a temperature sensing part (90, Fig.1) provided above the second high-concentration lower surface region (22), wherein
a first portion, in which the first high-concentration lower surface region (28) and the second high-concentration lower surface region (22) are provided alternately (side-by-side) along a predetermined first direction (x or horizontal direction), is provided such that the first portion sandwiches the temperature sensing part (90) in a second direction (y or vertical direction) that is perpendicular to the first direction (x or horizontal direction) in a top view (see Fig. 1).
Regarding claim 2, NAITO teaches wherein (Figs. 1-3), the first portion is a diode portion (80) that includes a diode element (para [0062]).
Regarding claim 3, NAITO teaches wherein (Figs. 1-3), a second portion (70), in which the second high-concentration lower surface region (22) extends in the first direction (x or horizontal direction), is provided.
Regarding claim 4, NAITO teaches wherein (Figs. 1-3), the second portion (70) is a transistor portion that includes an IGBT element (para [0061]), and the diode portion and the transistor portion are arranged periodically in a plane including the first direction and the second direction.
Regarding claim 6, NAITO teaches wherein (100, Figs. 1-3), the temperature sensing part (90) is provided at a center of an active section (102, para [0060]) of the semiconductor substrate (10).
Regarding claim 7, NAITO teaches wherein (100, Fig. 1), further comprising a temperature sensing wire (see the annotated figure below) that extends in the first direction (y or vertical direction) and is connected to the temperature sensing part (90).
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Regarding claim 8, NAITO teaches wherein (Fig. 1), the first portion also sandwiches the temperature sensing wire (see the figure in claim 7) in the second direction (x or horizontal direction) that is perpendicular to the first direction (y or vertical direction) in the top view (see Fig. 1).
Regarding claim 9, NAITO teaches wherein (Figs. 1-3), further comprising an outer periphery region (105) in which one or more metal pads (106, 107, 108) are arranged, the outer periphery region (105) being provided between the active section (102) and an outer peripheral end of the semiconductor substrate (10), wherein the temperature sensing wire is connected to a temperature measuring pad (108) provided in the outer periphery region (105).
Regarding claim 10, NAITO teaches wherein (Fig. 2), further comprising a plurality of trench parts (40/30, para [0070]) provided on a side of the upper surface of the semiconductor substrate (10), wherein at least a dummy trench part (30, para [0071]) is provided as the plurality of trench parts (40) in the first portion, and at least a gate trench part (40) is provided as the plurality of trench parts (40) in the second portion.
Regarding claim 11, NAITO teaches wherein (100, Figs. 1-3), each of the plurality of trench parts (40) includes a straight portion extends linearly in the first direction (y or vertical direction).
Regarding claim 16, NAITO teaches wherein (Fig. 3), the second high-concentration lower surface region (22) provided in the second portion (left) is a collector region (22) of the second conductivity-type (P+).
Regarding claim 17, NAITO teaches wherein (Fig. 3), a minority carrier injection efficiency is reduced in a first mesa part (see figure below) provided in the first portion than in a second mesa part (see figure below) provided in the second portion.
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Regarding claim 18, NAITO teaches wherein (Fig. 3), the first mesa part (see figure in claim 17) includes a high-concentration region of the first conductivity-type (N+ middle between P+ and P+) that is provided above the drift region (18) and has a doping concentration higher than (N+ vs. N-) the doping concentration (N-) of the drift region (18).
Regarding claim 19, NAITO teaches wherein (Fig. 3), the high-concentration region is provided above the first high-concentration lower surface region (28) and the second high-concentration lower surface region (22).
Regarding claim 20, NAITO teaches wherein (Fig. 3: see the annotated figure below) a depth (d1) of the base region of a first mesa part provided in the first portion is different from a depth (d2) of the base region of a second mesa part provided in the second portion.
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Allowable Subject Matter
9. Claims 5, 12-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 5: the prior art of record alone or in combination neither teaches nor makes obvious a semiconductor device comprising:
…. wherein in the first portion, at least ten first high-concentration lower surface regions, each being the first high-concentration lower surface region, are provided in the first direction and at least nine second high-concentration lower surface regions, each being the second high-concentration lower surface region, are provided in the first direction.
Claim 12: the prior art of record alone or in combination neither teaches nor makes obvious the semiconductor device comprising:
…. wherein the first high-concentration lower surface region provided in the first portion is a first cathode region of the first conductivity-type, and the second high-concentration lower surface region provided in the first portion is a second cathode region of the second conductivity-type.
10. The prior arts made of record and not relied upon is considered pertinent to applicant’s disclosure: the prior art, NAITO (US 2017/0236908 A1) discloses the semiconductor device with drift and base regions including first and second high-concentration lower surface regions and temperature sensing part explained in the office action above, however, the prior arts do not depict the elements as claimed in section 9, therefore, either by itself or in combination with other arts fail to disclose the above limitations in the section 9.
Examiner’s Note
11. Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular paragraphs and/or columns/lines in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
12. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DIDARUL MAZUMDER whose telephone number is (571)272-8823. The examiner can normally be reached M-F 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
13. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DIDARUL A MAZUMDER/Primary Examiner, Art Unit 2812
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