Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 4, 10-12 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lee et al.(US 20250107087 A1, hereafter Lee).
Regarding Claim 1, Lee discloses:
A semiconductor device(Fig. 9) comprising:
a peripheral circuit(Fig. 9 [S2]);
a first gate structure(Fig. 9 [130L]) disposed over the peripheral circuit(Fig. 9 [S2]);
a second gate structure(Fig. 9 [130U]) disposed over the first gate structure;
a dielectric bonding structure(Fig. 9 See figure below) disposed between the first gate structure(Fig. 9 [130L]) and the second gate structure(Fig. 9 [130U]);
a first contact via(Fig. 9 See figure below) extending through the first gate structure(Fig. 9 [130L]) and extending into the dielectric bonding structure(Fig. 9 See figure below);
a second contact via(Fig. 9 See figure below) extending through the second gate structure(Fig. 9 [130U]) and connected to the first contact via(Fig. 9 See figure below); and
a peripheral circuit bonding structure(Fig. 9 [198/298]) electrically connecting the first contact via(Fig. 9 See figure below) and the peripheral circuit(Fig. 9 [S2]) to each other.
Regarding Claim 4, Lee further discloses:
The first gate structure(Fig. 9 [130L]) includes a first staircase structure(Fig. 9 See figure below),
The second gate structure(Fig. 9 [130U]) includes a second staircase structure(Fig. 9 See figure below),
The first contact via(Fig. 9 See figure below) extends through the first staircase structure(Fig. 9 See figure below) and extends into the dielectric bonding layer(Fig. 9 See figure below), and
The second contact via(Fig. 9 See figure below) extends through the second staircase structure(Fig. 9 See figure below) and is connected to the first contact via(Fig. 9 See figure below).
Regarding Claim 10, Lee discloses:
The peripheral circuit(Fig. 9 [S2]) bonding structure(Fig. 9 [198/298]) includes a first peripheral circuit bonding pad(Fig. 9 [298]) and a second peripheral circuit bonding pad(Fig. 9 [198]) disposed on the first peripheral circuit bonding pad(Fig. 9 [298]).
Regarding Claim 11, Lee discloses:
a first stack(Fig. 9 See figure below) disposed at a level corresponding to the first gate structure(Fig. 9 [130L]);
a second stack(Fig. 9 See figure below) disposed at a level corresponding to the second gate structure(Fig. 9 [130U]);
a first contact plug(Fig. 9 [SH], See figure below) extending through the first stack(Fig. 9 See figure below) and extending into the dielectric bonding structure(Fig. 9 See figure below); and
a second contact plug(Fig. 9 [SH], See figure below) extending through the second stack(Fig. 9 See figure below) and connected to the first contact plug(Fig. 9 [SH], See figure below).
Regarding Claim 12, Lee further discloses:
A plug connection portion(Fig. 9 See figure below) where the first contact plug(Fig. 9 See figure below) and the second contact plug(Fig. 9 See figure below) are connected to each other is disposed on the dielectric bonding structure(Fig. 9 See figure below).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-3, 5-9, 13-21, is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Xiao et al.(US 20200176443 A1, hereafter Xiao).
Regarding Claim 2, Lee discloses a first source structure(Fig. 9 [101]) disposed on a first gate structure(Fig. 9 [130L]) and first channel structures(Fig. 9 [CHf]) extending into the first source structure(Fig. 9 [101]) through the first gate structure(Fig.9 [130L]).
Lee does not teach or disclose a second source structure between the first source structure and the second gate structure, and
Second channel structures extending into the second source structure through the second gate structure.
In the same field of endeavor, Xiao discloses:
a second source structure(Fig. 2A [238]) between the first source structure(Fig. 2A [236]) and the second gate structure(Fig. 2A [232B]), and
Second channel structures(Fig. 2A [244A]) extending into the second source structure(Fig. 2A [238]) through the second gate structure(Fig. 2A [232A]).
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to modify the device disclosed by Lee along the lines of Xiao. One might have been motivated to provide an additional source and channel structure in order to increase the memory capacity of the device by providing additional memory structures. Performing this modification would have generated a predictable result in Lee’s device with additional memory stacks above their first.
Regarding Claim 3,
Lee does not teach or disclose the dielectric bonding structure extends between the first source structure and the second source structure.
In the same field of endeavor, Xiao discloses a dielectric bonding structure(“one or more ILD layers”, See paragraph 0066) extending between the first source structure(Fig.2A [236]) and the second source structure(Fig. 2A [238]).
Regarding Claim 5,
Lee discloses the first gate structure(Fig. 9 [130L]) includes first conductive layers, the second gate structure(Fig. 9 [130U]) includes second conductive layers(Fig. 9 See figure below),
The first contact via(Fig. 9 See figure below) is connected to at least one of the first conductive layers(Fig. 9 See figure below).
Lee does not teach or disclose the second contact via is connected to at least one of the second conductive layers.
In the same field of endeavor, Xiao discloses a second contact via(Fig. 2A [148]) connected to at least one second conductive layer(Fig. 2A [134]).
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to modify the device disclosed by Lee along the lines of Xiao. One might have been motivated to provide a connection between the second contact via and the second conductive layers to provide a means by which to read or write a second memory device using the same word line. Performing this modification would have generated a predictable result in the creation of Lee’s device with an additional memory stack that mirrors the word line inputs of the first.
Regarding Claim 6,
Lee does not teach or disclose a first conductive layer connected to the first contact via is an uppermost first conductive layer of the first staircase structure among the first conductive layers, and
The second conductive layer connected to the second contact via is an uppermost second conductive layer of the second staircase structure among the second conductive layers.
In the same field of endeavor, Xiao discloses a pair of staircase structures(Fig. 2A [166/146]) wherein a first contact contacts an uppermost conductive layer of a first staircase(Fig. 2A [146]) and a second contact contacts an uppermost conductive layer of a second staircase(Fig. 2A [166]).
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to modify the device disclosed by Lee along the lines of Xiao. One might have been motivated to provide a connection between the second contact via and an uppermost second conductive layer to provide a means by which to read or write a second memory device using the same word line. Performing this modification would have generated a predictable result in the creation of Lee’s device with an additional memory stack that mirrors the word line inputs of the first.
Regarding Claim 7,
Lee does not teach or disclose a via connection portion where the first contact via and the second contact via are connected to each other is disposed over a dielectric bonding structure.
In the same field of endeavor, Xiao discloses a via connection portion(Fig. 2A [260/212]) where the first contact via(Fig. 2A [248]) and the second contact via(Fig. 2A [220]) is disposed over a dielectric bonding structure(Fig. 2A [210/258]).
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to modify the device disclosed by Lee along the lines of Xiao. One might have been motivated to include a via connection portion in order to join multiple memory stacks to each other. Performing this modification would have generated a predictable result in Lee’s device with additional memory stacks above their first.
Regarding Claim 8,
Lee does not teach or disclose the dielectric bonding structure includes a first dielectric bonding layer and a second dielectric bonding layer disposed on the first dielectric bonding layer.
In the same field of endeavor, Xiao disclose a dielectric bonding structure(Fig. 2A [210/258]) including a first dielectric bonding layer(Fig. 2A [210]) and a second dielectric bonding layer(Fig. 2A [258]) disposed on the first dielectric bonding layer(Fig. 2A [210]).
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to modify the device disclosed by Lee along the lines of Xiao. One might have been motivated to include a dielectric bonding structure as including a first and second dielectric bonding layer to join multiple memory stacks to each other. Performing this modification would have generated a predictable result in Lee’s device with additional memory stacks above their first.
Regarding Claim 9,
Lee does not teach or disclose the dielectric bonding structure includes a first dielectric bonding layer and a second dielectric bonding layer disposed on the first dielectric bonding layer which are directly bonded to each other.
In the same field of endeavor, Xiao disclose a dielectric bonding structure(Fig. 2A [210/258]) including a first dielectric bonding layer(Fig. 2A [210]) and a second dielectric bonding layer(Fig. 2A [258]) disposed on the first dielectric bonding layer(Fig. 2A [210]) which are directly bonded to each other.
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to modify the device disclosed by Lee along the lines of Xiao. One might have been motivated to include a dielectric bonding structure as including a first and second dielectric bonding layer bonded to each other to join multiple memory stacks to each other. Performing this modification would have generated a predictable result in Lee’s device with additional memory stacks above their first.
Regarding Claim 13,
Lee does not teach or disclose a source bonding structure disposed between the first gate structure and the second gate structure;
first channel structures extending into the source bonding structure through the first gate structure; and
second channel structures extending into the source bonding structure through the second gate structure.
In the same field of endeavor,
Xiao discloses a source bonding structure(Fig. 2A [234]) disposed between the first gate structure(Fig. 2A [232A]) and the second gate structure(Fig. 2A [232B])
first channel structures(Fig. 2A [244A]) extending into the source bonding structure(Fig. 2A [234]) through the first gate structure(Fig. 2A [232A]); and
second channel structures(Fig. 2A [244B]) extending into the source bonding structure(Fig. 2A [234]) through the second gate structure(Fig. 2A [232B]).
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to modify the device disclosed by Lee along the lines of Xiao. One might have been motivated to provide a source bonding structure to increase the memory capacity of the device by providing additional memory structures. Performing this modification would have generated a predictable result in Lee’s device with additional memory stacks above their first.
Regarding Claim 14,
Lee does not teach or disclose the dielectric bonding structure is disposed at a level corresponding to the source bonding structure.
In the same field of endeavor, Xiao discloses a dielectric bonding structure(Paragraph 0066, See “one or more ILD layers”) disposed at a level corresponding to the source bonding structure(Fig. 2A [234]).
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to modify the device disclosed by Lee along the lines of Xiao. One might have been motivated to provide a dielectric bonding structure at the level of the source bonding structure to separate two source regions such that different signals can be routed to different parts of the memory device. Performing this modification would have generated a predictable result in Lee’s device with additional memory stacks above their first.
Regarding Claim 15,
Lee does not teach or disclose the dielectric bonding structure includes a first dielectric bonding pattern and a second dielectric bonding pattern disposed on the first dielectric bonding pattern.
In the same field of endeavor, Xiao discloses a dielectric bonding structure(Paragraph 0066, See “one or more ILD layers”).
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to arrive at the claimed limitation by applying the teaching of Xiao to the device disclosed by Lee. As Xiao’s dielectric bonding structure might comprise a plurality of layers, that includes two layers bonded to each other. One might have arrived at this limitation by experimentation with various known ILD structures. Performing this modification would have generated a predictable result in Lee’s device with additional memory stacks above their first, with a dielectric bonding structure comprising two or more layers.
Regarding Claim 16,
Lee does not teach or disclose the dielectric bonding structure includes the first dielectric bonding pattern and the second dielectric bonding pattern are directly bonded to each other.
In the same field of endeavor, Xiao discloses a dielectric bonding structure(Paragraph 0066, See “one or more ILD layers”).
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to arrive at the claimed limitation by applying the teaching of Xiao to the device disclosed by Lee. As Xiao’s dielectric bonding structure might comprise a plurality of layers, that includes two layers bonded to each other. One might have arrived at this limitation by experimentation with various known ILD structures. Performing this modification would have generated a predictable result in Lee’s device with additional memory stacks above their first, with a dielectric bonding structure comprising two or more layers.
Regarding Claim 17,
Lee does not teach or disclose a via connection portion.
In the same field of endeavor, Xiao discloses a via connection portion(Fig. 2B [263]) and a first contact via(Fig. 2A [240]) and a second contact via(Fig. 2A [242]) which are both connected to a source structure.
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to arrive at the claimed limitation by applying the teaching of Xiao to the device disclosed by Lee. As Xiao shows one embodiment wherein the NAND memory strings(Fig. 2B [244A/244B]) are connected to a common junction, one of ordinary skill in the art would be led to a device such as the one in Fig. 2A of Xiao wherein the two source contact vias are connected to each other, unifying the signals between their respective memory stacks. Performing his modification would have generated a predictable result in the creation of Lee’s device with an additional memory stack that mirrors the word line inputs of the first.
Regarding Claim 18,
Lee does not teach or disclose the source bonding structure includes a first source bonding pattern and a second source bonding pattern disposed on the first source bonding pattern.
In the same field of endeavor Xiao discloses the source bonding structure(Fig. 2A [234]) including a first source bonding pattern(Fig. 2A [236]) and a second source bonding pattern(Fig. 2A [238]) disposed on the first source bonding pattern(Fig. 2A [236]).
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to modify the device disclosed by Lee along the lines of Xiao. One might have been motivated to provide a source bonding structure to increase the memory capacity of the device by providing additional memory structures. Performing this modification would have generated a predictable result in Lee’s device with additional memory stacks above their first.
Regarding Claim 19,
Lee does not teach or disclose the first source bonding pattern and the second source bonding pattern are directly bonded to each other.
In the same field of endeavor, Xiao discloses a via connection portion(Fig. 2B [263]) and a first contact via(Fig. 2A [240]) and a second contact via(Fig. 2A [242]) which are both connected to a source structure.
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to arrive at the claimed limitation by applying the teaching of Xiao to the device disclosed by Lee. As Xiao shows one embodiment wherein the NAND memory strings(Fig. 2B [244A/244B]) are connected to a common junction, one of ordinary skill in the art would be led to a device such as the one in Fig. 2A of Xiao wherein the two source contact vias are bonded to each other, unifying the signals between their respective memory stacks. Performing his modification would have generated a predictable result in the creation of Lee’s device with an additional memory stack that mirrors the word line inputs of the first.
Regarding Claim 20, Lee further discloses:
a first stack(Fig. 9 See figure below) disposed at a level corresponding to the first gate structure(Fig. 9 [130L]);
a second stack(Fig. 9 See figure below) disposed at a level corresponding to the second gate structure(Fig. 9 [130U]);
a first contact plug(Fig. 9 [SH], See figure below) extending through the first stack(Fig. 9 See figure below) and extending into the dielectric bonding structure(Fig. 9 See figure below); and
a second contact plug(Fig. 9 [SH], See figure below) extending through the second stack(Fig. 9 See figure below) and connected to the first contact plug(Fig. 9 [SH], See figure below).
Regarding Claim 21, Lee further discloses:
A plug connection portion(Fig. 9 See figure below) where the first contact plug(Fig. 9 See figure below) and the second contact plug(Fig. 9 See figure below) are connected to each other is disposed on the dielectric bonding structure(Fig. 9 See figure below).
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Above: Fig. 9 of Lee with respective components denoted by examiner.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Wu et al.(US 20250349701 A1) discloses a dielectric bonding structure with a source bonding structure therein. Lee et al.(US 20250107086 A1) discloses a memory device with a specific contact via and channel structure. Jeon(US 20240414915 A1) discloses a 3D memory structure. Xiao(US 20200194452 A1) discloses a memory structure with multiple staircases stacked on top of each other.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARSHALL MU-NUO HATFIELD whose telephone number is (703)756-1506. The examiner can normally be reached Mon-Thus 11:00 AM-9:00PM EST.
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/MARSHALL MU-NUO HATFIELD/Examiner, Art Unit 2897
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