DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 9-21 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on September 2 2025.
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged.
Drawings
Drawings 6-8 are objected for failing to comply with 37 CFR 1.84(p)(3), which requires that numbers, letters, and reference characters should not be placed in the drawing so as to interfere with its comprehension. Therefore, they should not cross or mingle with the lines. There are multiple instances where lines cross over letters and reference numbers, such as Figure 6, for example.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The disclosure is objected to because of the following informalities:
[0053]: In line 4, the first instance of “slice task B” is an error and should be corrected to “compute slice B”.
[0076]: The phrase “the current LSU 850 can be made the head pointer and commit” doesn’t seem to be what the Applicant meant. Examiner recommends that the phrase instead reads “the current LSU 850 is pointed to by the head pointer and can commit”.
Appropriate correction is required.
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). See the rejection under 35 U.S.C. 112 below.
Claim Objections/Recommendations
Claims 5, 7, 22, 23 are objected to because of the following informalities:
Claim 5, lines 1-2: The phrase “the checking includes the address data that was collected in the store buffer within the current LSU” is phrased in a way that indicates an action comprising of a noun, which isn’t a valid statement. Examiner recommends the following change: “the checking includes comparing the address data that was collected in the store buffer within the current LSU.”
Claim 7, lines 1-2: The phrase “the checking includes a second previously executed store instruction” is phrased in a way that indicates an action comprising of a noun, which isn’t a valid statement. Examiner recommends the following change: “the checking includes comparing a second previously executed store instruction.”
Claim 22, lines 1-2: The phrase “the plurality of compute slices is coupled” is grammatically incorrect and should instead read “the plurality of compute slices are coupled”.
Claim 23, line 1: The phrase “the plurality of LSUs is coupled” is grammatically incorrect and should instead read “the plurality of LSUs are coupled”.
Claim 1 is given the following recommendation
Claim 1, line 1: Replace “operations comprising” with “operations, the method comprising” to explicitly connect the body with the method, not the memory operations.
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
“control unit… distributing a current slice task” in claims 1 and 25-27, invokes 112(f). However, Examiner could not find the corresponding structure in the specification or drawings. Examiner finds the function supported by the control unit (e.g., [0022]), but could not find any structural support to conclude the structure of the control unit. For the purposes of prior art examination, Examiner is interpreting the limitation as any circuit that performs the function.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-8 and 22-27 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claims 1 and 25-27, as described below in the 112(b) rejection, the disclosure does not provide adequate structure to perform the claimed functions for the ”distributing a current slice task.” The application does not demonstrate that the applicant has made an invention that achieves the claimed functions because the invention is not described with sufficient detail such that one of ordinary skill in the art can reasonably conclude that the inventor had possession of the claimed invention.
Claims 2-8 and 22-25 are rejected for inheriting the rejection of claim 1.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-8 and 22-27 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1 and 25-27 contain the claim limitation “control unit”, which invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. The specification is devoid of adequate structure to perform the claimed function. In particular, the specification states that the claimed function is done by a “control unit.” The use of the term “control unit” is not adequate structure for performing the claimed function mentioned previously because it does not describe a particular structure for performing the function. The specification does not provide sufficient details such that one of ordinary skill in the art would understand which structure would perform the claimed function. Therefore, the claims are indefinite and are rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-8, 22-23, and 26-27 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 1, 1, 1, 1, 1, 14, 12, 19, 19, 20, and 21 of copending Application No. 19/093,385 (hereinafter Reference Application) in view of Hsieh et al. (US 20200285478 A1)
Regarding claim 1, the Reference Application teaches a processor-implemented method for memory operations comprising:
accessing a processing unit comprising a plurality of compute slices, a plurality of load-store units (LSUs), a control unit, and a memory system, wherein each compute slice within the plurality of compute slices includes at least one execution unit and is coupled to a successor compute slice and a predecessor compute slice, wherein each compute slice within the plurality of compute slices includes a unique LSU in the plurality of LSUs, and wherein each LSU in the plurality of LSUs is coupled to a successor LSU and a predecessor LSU (Claim 1: LMDUs as LSUs);
distributing a current slice task, by the control unit, to a current compute slice in the plurality of compute slices, wherein the current compute slice includes a current LSU, wherein the current slice task includes a load instruction (Claim 1: The first compute slice as the current compute slice);
saving, in an entry of a load address buffer (LAB) within the current LSU, a load address associated with the load instruction (Claim 1: Memory operation table containing a first section to save a load address associated to a load instruction. The first section as the load address buffer);
checking for address aliasing between the entry of the LAB and a store address associated with a previously executed store instruction (see claim 1); and
executing the load instruction (Claim 1: “Issuing” indicates that the load instruction is issued into the execution pipeline, therefore the instruction is being executed).
The Reference Application does not teach that the current compute slice is not a head slice.
Hsieh does teach a plurality of slices where a compute slice is not a head slice (Fig. 3: Slice 0 is a head slice since it’s the first slice of the sequence. Therefore Slice 1 is not a head slice).
It would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of the Reference Application with the teachings of Hsieh to have indicated that the current compute slice is not a head slice. One of ordinary skill would understand that a “head slice” may be designed to handle certain tasks in which non-head slices may not be able to handle as they may be restricted in what instructions are to be committed or that the head slice should handle data dependencies differently from the non-head slices as to maintain memory consistency.
Regarding claim 3, the Reference Application, in view of Hsieh, teaches the method of claim 1 wherein the previously executed store instruction was executed by the current LSU (Claim 1).
Regarding claim 4, the Reference Application, in view of Hsieh, teaches the method of claim 3 further comprising collecting, in a store buffer within the current LSU, address data associated with the previously executed store instruction (Claim 1: The memory operation table stores store address in a second section of the table. The second section of the table as the store buffer).
Regarding claim 5, the Reference Application, in view of Hsieh , teaches the method of claim 4 wherein the checking includes the address data that was collected in the store buffer within the current LSU (Claim 1: Checking occurs within the memory operation table).
Regarding claim 6, the Reference Application, in view of Hsieh, teaches the method of claim 5 further comprising returning data, for the load instruction, from the previously executed store instruction, wherein the checking detected address aliasing (see Claim 1).
Regarding claim 7, the Reference Application, in view of Hsieh, teaches the method of claim 6 wherein the checking includes a second previously executed store instruction (Claim 14: Store instructions stored in the memory operation table are indicated to have been executed prior to check to see if address aliasing has occurred).
Regarding claim 8, the Reference Application, in view of Hsieh, teaches the method of claim 6 wherein the current slice task includes a second load instruction (see Claim 12).
Regarding claim 22, the Reference Application, in view of Hsieh, teaches the method of claim 1 wherein the plurality of compute slices is coupled in a ring configuration (see Claim 19).
Regarding claim 23, the Reference Application, in view of Hsieh, teaches the method of claim 1 wherein the plurality of LSUs is coupled in a ring configuration (Claim 19: Given that the compute slices are in a ring configuration and that each compute slice is coupled to an LMDU, the LMDUs would also be part of the ring configuration. Therefore, the LMDUs are coupled in a ring configuration).
Regarding claims 26 and 27, the claims are rejected for the same reasons as claim 1, using claims 20 and 21 of the Reference Application, respectively.
Claims 2 and 24 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 1 of copending Application No. 19/093,385 (hereinafter Reference Application) in view of Hsieh et al. (US 20200285478 A1) and University of California (hereinafter UC) (The Load/Store Unit (LSU)).
Regarding claim 2, the Reference Application, in view of Hsieh, teaches the method of claim 1.
The Reference Application, in view of Hsieh, does not teach that the checking did not detect address aliasing.
UC teaches that the checking does not detect address aliasing (UC, Fig. 24 and Section “Load Instructions”, Paragraphs 1 and 3: Load address is compared to all store addresses in STQ and if no match is found, then loads are processed normally).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of the Reference Application, in view of Hsieh, with the teachings of UC to have the checking not detect address aliasing. One of ordinary skill would understand that every load instruction will not cause the LSU to detect address aliasing. Therefore, it’s important to indicate that address aliasing wasn’t detected as to allow the execution pipeline to continue executing without issue.
Regarding claim 24, the Reference Application, in view of Hsieh, teaches the method of claim 1.
The Reference Application, in view of Hsieh, does not teach that the checking occurs in a single cycle
UC teaches that a checking for address aliasing occurs in a single cycle (UC, Fig. 24: In the memory stage, searching to see if there is a match between a load address and a store address all occurs within the memory stage (i.e., within a single cycle)).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of the Reference Application, in view of Hsieh, with the teachings of UC to have checked for address aliasing in a single cycle. One of ordinary skill would have realized that checking to see if a match exists between a load address and store address would only require combinational logic, therefore it’s doable to do the checking within a single cycle, as seen in Fig. 24 of UC.
Claim 25 is provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of copending Application No. 19/093,385 (hereinafter Reference Application) in view of Hsieh et al. (US 20200285478 A1) and Arndt et al. (US 20120072707 A1).
Regarding claim 25, the Reference Application, in view of Hsieh, teaches the method of claim 1, wherein the head slice is a compute slice (Hsieh, Fig. 3: Slice 0 is a compute slice and the first compute slice in the sequence. Therefore Slice 0 is a head slice)
However, the Reference Application, in view of Hsieh, does not teach that the head slice is pointed to by a head pointer within the control unit.
Arndt teaches that the head hardware thread is a compute hardware thread which is pointed to by a head pointer within a control unit (Fig. 3B and [0047-0048]: Hardware status store (HWSS) keeps track of assist hardware threads statuses starting with the first assist hardware thread, which can be considered as the head hardware thread and is capable of computation so it’s also a compute hardware thread. The first entry of the HWSS points to the first hardware thread initiated and tracks its current status; therefore the first entry acts as a head pointer pointing to the first hardware thread. HWSS as the control unit).
It would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of the Reference Application, in view of Hsieh, with the teachings of Arndt to have the control unit point to the head slice indicated by a head pointer. One of ordinary skill may appreciate tracking the current head slice as they can utilize the pointer to track important information, such as whether the slice is current executing a thread or if the slice is idle.
This is a provisional nonstatutory double patenting rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8, 22-24, and 27 is rejected under 35 U.S.C. 103 as being unpatentable over Hsieh et al. (US 20200285478 A1) in view of the University of California (hereinafter UC) (The Load/Store Unit (LSU)) and Kim et al. (US 20230333852 A1).
Regarding claim 1, Hsieh teaches a processor-implemented method for memory operations comprising:
accessing a processing unit comprising a plurality of compute slices (Fig. 3 and [0035, 0037]: Processor 200, with execution slices S0 and S1 shown in the figure. There can be more than 2 slices within the processor), a plurality of load-store units (LSUs) (Fig. 3 and [0035]: Each slice has an LSU 304, therefore a plurality of slices mean a plurality of LSUs) a control unit (Fig. 2 and [0023]: logic unit 208 dispatches instructions to execution slices, therefore a control unit), and a memory system (Figs. 2-3 and [0036]: WB bus 230 is connected to each slice, where the WB bus is connected to D-cache 206 and eventually connects to memory 103, hence a memory system), wherein each compute slice within the plurality of compute slices includes at least one execution unit (Fig. 3 and [0035]: LSU 304, vector scalar unit 306, register file 216, and history buffer unit 214 are execution units), wherein each compute slice within the plurality of compute slices includes a unique LSU in the plurality of LSUs (Fig. 3: Within each slice contains an LSU, therefore each LSU is unique to their respective slice), and
distributing a current slice task, by the control unit, to a current compute slice in the plurality of compute slices (Fig. 3 and [0035, 0038]: Each slice may process a thread, therefore logic unit 208 may dispatch a plurality of instructions related to each thread, including slice 1. Slice 1 as the current slice and the thread dispatched to slice 1 as the slice task), wherein the current compute slice includes a current LSU (Fig. 3: LSU 304a in slice 1 as the current slice), wherein the current slice task includes a load instruction (Fig. 3: An LSU handles load/store instructions, therefore the thread dispatched to slice 1 may include a load instruction), and wherein the current compute slice is not a head slice (Fig. 3: Slice 1 is not the first slice of the sequence of slices, therefore Slice 1 is not a head slice); and
executing the load instruction (Fig. 3: An instruction that’s processed in the LSU would mean that the instruction is in the process of being executed).
However, Hsieh does not teach that each compute is coupled to a successor compute slice and a predecessor compute slice, each LSU in the plurality of LSUs is coupled to a successor LSU and a predecessor LSU, saving, in an entry of a load address buffer (LAB) within the current LSU, a load address associated with the load instruction, and checking for address aliasing between the entry of the LAB and a store address associated with a previously executed store instruction.
UC teaches saving, in an entry of a load address buffer (LAB) within an LSU, a load address associated with a load instruction (Fig. 24: load instructions and addresses are stored in the LDQ. The LDQ as the load address buffer), checking for address aliasing between the entry of the LAB and a store address associated with a previously executed store instruction (Fig. 24 and section “Load Instructions” Paragraph 3: During the execution of a load instruction, the LDQ entry corresponding to the load instruction is compared with all STQ entries at the searcher module and checks to see if address aliasing has occurred. Each entry in the STQ includes a store address associated to a store instruction previously executed).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Hsieh with the teachings of UC to detect for address aliasing within the LSU. One of ordinary skill would recognize that load-after-store violations are possible in an out-of-order execution pipeline, which indicates that a load instruction would use data that may be out of date due to a prior executed store instruction. Therefore, there needs to be a system in place to indicate a load-after-store violation occurred and forward the data to the load instruction for proper data consistency.
However, Hsieh and UC still does not teach that each compute slice within the plurality of compute slices is coupled to a successor compute slice and a predecessor compute slice and each LSU in the plurality of LSUs is coupled to a successor LSU and a predecessor LSU.
While predecessor/successor couplings are taught (Fig. 3: Slice 1 and LSU 304b is coupled to Slice 0, where Slice 0 and LSU 304a is considered to be a predecessor slice and LSU for Slice 1 and LSU 304b, and Slice 1 and 304b is considered to be a successor slice and LSU for Slice 0 and LSU 304a, based on the ordering of the slices and LSUs), Hsieh has not taught that each compute slice or LSU is coupled to a predecessor and successor.
Note that if every slice was coupled to a predecessor slice and a successor slice, then every LSU would also be coupled to a successor LSU and a predecessor LSU, based on the slice layout in Hsieh.
Kim teaches a ring configuration of clusters, where each cluster has a predecessor cluster and a successor cluster (Fig. 5, [0054]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Hsieh, in view of UC, with the teachings of Kim to have each slice be connected to a successor slice and a predecessor slice in a ring configuration. A ring configuration would be beneficial in execution as it would allow a continuous cycle of executing/loading instructions between slices as to increase the utilization of resources (see Kim, Fig. 5 and [0054]), which one of ordinary skill may appreciate.
Regarding claim 2, Hsieh, in view of UC and Kim, teaches the method of claim 1, wherein the checking did not detect address aliasing (UC, Fig. 24 and Section “Load Instructions”, Paragraphs 1 and 3: Load address is compared to all store addresses in STQ and if no match is found, then loads are processed normally).
Regarding claim 3, Hsieh, in view of UC and Kim, teaches the method of claim 1 wherein the previously executed store instruction was executed by the current LSU (UC, Fig. 24 and Section “Store Instructions”: After the “execution stage” of the pipeline, where the store instruction data are stored in STQ in the “decode stage”, the store instruction would have been executed).
Regarding claim 4, Hsieh, in view of UC and Kim, teaches the method of claim 3 further comprising collecting, in a store buffer within the current LSU, address data associated with the previously executed store instruction (UC, Fig. 24 and Section “Store Instructions”: When a store instruction has been decoded, the store address data associated to the store instruction is stored into STQ and is to be processed in the “execution stage”. STQ as the store buffer).
Regarding claim 5, Hsieh, in view of UC and Kim, teaches the method of claim 4 wherein the checking includes the address data that was collected in the store buffer within the current LSU (UC, Fig. 24 and Section “Store Instructions”: Store addresses are collected and stored in the STQ, where these entries are used for comparison in the searcher module of the LSU).
Regarding claim 6, Hsieh, in view of UC and Kim, teaches the method of claim 5 further comprising returning data, for the load instruction, from the previously executed store instruction, wherein the checking detected address aliasing (UC, Fig. 24 and Section “Load Instructions” Paragraph 3: When a load address matches to a store address, data is forwarded from the SDQ and becomes the output for the writeback stage).
Regarding claim 7, Hsieh, in view of UC and Kim, teaches the method of claim 6 wherein the checking includes a second previously executed store instruction (UC, Fig. 24 and Section “Store Instructions”: The STQ can hold multiple entries and the searcher module checks all entries in the STQ. Therefore a second previously executed store instruction may store the second store instruction’s address and data in the STQ).
Regarding claim 8, Hsieh, in view of UC and Kim, teaches the method of claim 6 wherein the current slice task includes a second load instruction (UC, Fig. 24: The LDQ may hold multiple load address entries; therefore the LSU may process multiple load instructions when a thread requires multiple loads to be processed).
Regarding claim 22, Hsieh, in view of UC and Kim, teaches the method of claim 1 wherein the plurality of compute slices is coupled in a ring configuration (The current configuration is in a ring configuration; therefore the slices are coupled in a ring configuration).
Regarding claim 23, Hsieh, in view of UC and Kim, teaches the method of claim 1 wherein the plurality of LSUs is coupled in a ring configuration (The current configuration is in a ring configuration; therefore the LSUs are coupled in a ring configuration).
Regarding claim 24, Hsieh, in view of UC and Kim, teaches the method of claim 1 wherein the checking occurs in a single cycle (UC, Fig. 24: In the memory stage, searching to see if there is a match between a load address and a store address all occurs within the memory stage (i.e., within a single cycle)).
Regarding claim 27, the claim recites a computer system similar to the method of claim 1, therefore the claim is rejected on the same premises.
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Hsieh et al. (US 20200285478 A1) in view of the University of California (The Load/Store Unit (LSU)), Kim et al. (US 20230333852 A1), and Arndt et al. (US 20120072707 A1).
Regarding claim 25, Hsieh, in view of UC and Kim, teaches the method of claim 1 wherein the head slice is a compute slice (Hsieh, Fig. 3: Slice 0 is a compute slice).
Hsieh, in view of UC and Kim, does not teach that the head slice is a compute slice which is pointed to by a head pointer within the control unit.
Note that the slices in Hsieh act similar to hardware threads as they are capable of executing threads in parallel (see Hsieh, [0038]).
Arndt teaches that the head hardware thread is a compute hardware thread which is pointed to by a head pointer within a control unit (Fig. 3B and [0047-0048]: Hardware status store (HWSS) keeps track of assist hardware threads statuses starting with the first assist hardware thread, which can be considered as the head hardware thread and is capable of computation so it’s also a compute hardware thread. The first entry of the HWSS points to the first hardware thread initiated and tracks its current status; therefore the first entry acts as a head pointer pointing to the first hardware thread. HWSS as the control unit).
It would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Hsieh, in view of UC and Kim, with the teachings of Arndt to have the control unit point to the head slice indicated by a head pointer. One of ordinary skill may appreciate tracking the current head slice as they can utilize the pointer to track important information, such as whether the slice is current executing a thread or if the slice is idle.
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Hsieh et al. (US 20200285478 A1) in view of the University of California (The Load/Store Unit (LSU)), Kim et al. (US 20230333852 A1), and Anderson et al. (US 20190196790 A1).
Regarding claim 26, the claim is mostly rejected for the same reasons as claim 1. Hsieh, in view of UC and Kim, does not teach a computer program product embodied in a non-transitory computer readable medium for task processing, the computer program product comprising code which causes one or more processors to generate semiconductor logic
Anderson teaches a computer program product embodied in a non-transitory computer readable medium for task processing, the computer program product comprising code which causes one or more processors to generate semiconductor logic (see [0123-0124]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Hsieh, in view of UC and Kim, with the teachings of Anderson to store a computer program in a non-transitory CRM to generate semiconductor logic. Implementing the design to the CRM would allow one of ordinary skill to model, simulate, and test the design as it’s fundamental to debug and finalize designs prior to processing it on a semiconductor to avoid issues.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 20230205525 A1: Sadayan et al. teaches a processor that detects address aliasing by masking multiple store instruction address bytes.
US 20210072997 A1: Kothari et al. teaches a processor with an LSU that flushes and replays load instructions if address aliasing occurred.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMILIO ALCANTARA-RAMOS whose telephone number is (571)272-4211. The examiner can normally be reached Mon-Fri 8:30-5:00 PST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached at (571)270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/E.A./Examiner, Art Unit 2183
/JYOTI MEHTA/Supervisory Patent Examiner, Art Unit 2183