DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Terminal Disclaimer
The terminal disclaimer filed on April 21, 2026, disclaiming the terminal portion of any patent granted on this application which would extend beyond the expiration date of any patent granted on Application Number 19/093,385 has been reviewed and is accepted. The terminal disclaimer has been recorded. The Non-Statutory Double Patenting rejections of claims 1-8, 22-23, and 26-27 has been withdrawn
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Examiner recommends that Applicant adds concepts of detecting address aliasing in a current compute slice using an LSU.
Claim Objections/Recommendations
Claim 27 is objected to because of the following informalities:
Line 2: An “and” is missing after the semicolon and should be added.
Appropriate correction is required.
Examiner makes the following recommendations to the claims:
Claim 26, lines 3-4: Insert “circuit” after “logic” to avoid “semiconductor logic” being interpreted under 112(f).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 22 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 22 recites the limitation "the compute slice ring" in line 2. There is insufficient antecedent basis for this limitation in the claim. There was no prior instance of “a compute slice ring” within the claim or the claim it depends on. For the sake of examination, Examiner will interpret this limitation to be “the ring configuration”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8, 23-24, and 27 is rejected under 35 U.S.C. 103 as being unpatentable over Hsieh et al. (US 20200285478 A1) in view of the University of California (hereinafter UC) (The Load/Store Unit (LSU), see Non-Final Office Action mailed 10/27/2025), Kim et al. (US 20230333852 A1), and Rakib et al. (US 20100281236 A1).
Regarding claim 1, Hsieh teaches a processor-implemented method for memory operations, the method comprising:
accessing a processor comprising a plurality of compute slices (Fig. 3 and [0035, 0037]: Processor 200, with execution slices S0 and S1 shown in the figure. There can be more than 2 slices within the processor), a plurality of load-store units (LSUs) (Fig. 3 and [0035]: Each slice has an LSU 304, therefore a plurality of slices mean a plurality of LSUs), and a memory system (Figs. 2-3 and [0036]: WB bus 230 is connected to each slice, where the WB bus is connected to D-cache 206 and eventually connects to memory 103, hence a memory system), wherein each compute slice within the plurality of compute slices includes at least one execution unit (Fig. 3 and [0035]: LSU 304, vector scalar unit 306, register file 216, and history buffer unit 214 are execution units), wherein each compute slice within the plurality of compute slices includes a unique LSU in the plurality of LSUs (Fig. 3: Within each slice contains an LSU, therefore each LSU is unique to their respective slice), and
distributing a current slice task, to a current compute slice in the plurality of compute slices (Fig. 3 and [0035, 0038]: Each slice may process a thread, therefore logic unit 208 may dispatch a plurality of instructions related to each thread, including slice 1. Slice 1 as the current slice and the thread dispatched to slice 1 as the slice task), wherein the current compute slice includes a current LSU (Fig. 3: LSU 304a in slice 1 as the current slice), wherein the current slice task includes a load instruction (Fig. 3: An LSU handles load/store instructions, therefore the thread dispatched to slice 1 may include a load instruction), and wherein the current compute slice is not a head slice (Fig. 3: Slice 1 is not the first slice of the sequence of slices, therefore Slice 1 is not a head slice); and
executing the load instruction (Fig. 3: An instruction that’s processed in the LSU would mean that the instruction is in the process of being executed).
However, Hsieh does not teach that each compute is coupled to a successor compute slice and a predecessor compute slice, each LSU in the plurality of LSUs is coupled to a successor LSU and a predecessor LSU, saving, in an entry of a load address buffer (LAB) within the current LSU, a load address associated with the load instruction, and checking for address aliasing between the entry of the LAB and a store address associated with a previously executed store instruction, and that each compute slice coupling uses a barrier register set that provides unidirectional communication between the compute slice and the successor slice.
UC teaches saving, in an entry of a load address buffer (LAB) within an LSU, a load address associated with a load instruction (Fig. 24: load instructions and addresses are stored in the LDQ. The LDQ as the load address buffer), checking for address aliasing between the entry of the LAB and a store address associated with a previously executed store instruction (Fig. 24 and section “Load Instructions” Paragraph 3: During the execution of a load instruction, the LDQ entry corresponding to the load instruction is compared with all STQ entries at the searcher module and checks to see if address aliasing has occurred. Each entry in the STQ includes a store address associated to a store instruction previously executed).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Hsieh with the teachings of UC to detect for address aliasing within the LSU. One of ordinary skill would recognize that load-after-store violations are possible in an out-of-order execution pipeline, which indicates that a load instruction would use data that may be out of date due to a prior executed store instruction. Therefore, there needs to be a system in place to indicate a load-after-store violation occurred and forward the data to the load instruction for proper data consistency.
However, Hsieh and UC still does not teach that each compute slice within the plurality of compute slices is coupled to a successor compute slice and a predecessor compute slice, each LSU in the plurality of LSUs is coupled to a successor LSU and a predecessor LSU, and that each compute slice coupling uses a barrier register set that provides unidirectional communication between the compute slice and the successor slice.
While predecessor/successor couplings are taught (Fig. 3: Slice 1 and LSU 304b is coupled to Slice 0, where Slice 0 and LSU 304a is considered to be a predecessor slice and LSU for Slice 1 and LSU 304b, and Slice 1 and 304b is considered to be a successor slice and LSU for Slice 0 and LSU 304a, based on the ordering of the slices and LSUs), Hsieh has not taught that each compute slice or LSU is coupled to a predecessor and successor.
Note that if every slice was coupled to a predecessor slice and a successor slice, then every LSU would also be coupled to a successor LSU and a predecessor LSU, based on the slice layout in Hsieh.
Kim teaches a ring configuration of clusters, where each cluster has a predecessor cluster and a successor cluster (Fig. 5, [0054]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Hsieh, in view of UC, with the teachings of Kim to have each slice be connected to a successor slice and a predecessor slice in a ring configuration. A ring configuration would be beneficial in execution as it would allow a continuous cycle of executing/loading instructions between slices as to increase the utilization of resources (see Kim, Fig. 5 and [0054]), which one of ordinary skill may appreciate.
However, Hsieh, in view of UC and Kim, still does not teach that each compute slice coupling uses a barrier register set that provides unidirectional communication between the compute slice and the successor slice.
Rakib teaches that each processing element uses a barrier register set that provides unidirectional communication between a processing element and a neighboring processing element ([0023, 0049]: Each processing element includes one or more exchange registers that may enable unidirectional communication between neighboring processing elements. The exchange registers as the barrier register set since they prevent bi-directional communication of data, hence a barrier).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Hsieh, in view of UC and Kim, with the teachings of Rakib to have each of the slices comprise of exchange registers that provides unidirectional communication between the current slice and the successor slice. By using exchange registers, data that needs to be communicated to a successor slice can be transferred through the exchange register rather than having the data stored in memory by the current slice and then reload the same data in the successor slice (see [0049]), which may be appreciated by one of ordinary skill.
Regarding claim 2, Hsieh, in view of UC, Kim, and Rakib, teaches the method of claim 1, wherein the checking did not detect address aliasing (UC, Fig. 24 and Section “Load Instructions”, Paragraphs 1 and 3: Load address is compared to all store addresses in STQ and if no match is found, then loads are processed normally).
Regarding claim 3, Hsieh, in view of UC, Kim, and Rakib, teaches the method of claim 1 wherein the previously executed store instruction was executed by the current LSU (UC, Fig. 24 and Section “Store Instructions”: After the “execution stage” of the pipeline, where the store instruction data are stored in STQ in the “decode stage”, the store instruction would have been executed).
Regarding claim 4, Hsieh, in view of UC, Kim, and Rakib, teaches the method of claim 3 further comprising collecting, in a store buffer within the current LSU, address data associated with the previously executed store instruction (UC, Fig. 24 and Section “Store Instructions”: When a store instruction has been decoded, the store address data associated to the store instruction is stored into STQ and is to be processed in the “execution stage”. STQ as the store buffer).
Regarding claim 5, Hsieh, in view of UC, Kim, and Rakib, teaches the method of claim 4 wherein the checking includes comparing the address data that was collected in the store buffer within the current LSU (UC, Fig. 24 and Section “Store Instructions”: Store addresses are collected and stored in the STQ, where these entries are used for comparison in the searcher module of the LSU).
Regarding claim 6, Hsieh, in view of UC, Kim, and Rakib, teaches the method of claim 5 further comprising returning data, for the load instruction, from the previously executed store instruction, wherein the checking detected address aliasing (UC, Fig. 24 and Section “Load Instructions” Paragraph 3: When a load address matches to a store address, data is forwarded from the SDQ and becomes the output for the writeback stage).
Regarding claim 7, Hsieh, in view of UC, Kim, and Rakib, teaches the method of claim 6 wherein the checking includes comparing a second previously executed store instruction (UC, Fig. 24 and Section “Store Instructions”: The STQ can hold multiple entries and the searcher module checks all entries in the STQ. Therefore a second previously executed store instruction may have its respective address and data stored in the STQ to be compared with the load instruction).
Regarding claim 8, Hsieh, in view of UC, Kim, and Rakib, teaches the method of claim 6 wherein the current slice task includes a second load instruction (UC, Fig. 24: The LDQ may hold multiple load address entries; therefore the LSU may process multiple load instructions when a thread requires multiple loads to be processed).
Regarding claim 23, Hsieh, in view of UC, Kim, and Rakib, teaches the method of claim 1 wherein the plurality of LSUs are coupled in a ring configuration (The current configuration is in a ring configuration; therefore the LSUs are coupled in a ring configuration).
Regarding claim 24, Hsieh, in view of UC, Kim, and Rakib, teaches the method of claim 1 wherein the checking occurs in a single cycle (UC, Fig. 24: In the memory stage, searching to see if there is a match between a load address and a store address all occurs within the memory stage (i.e., within a single cycle)).
Regarding claim 27, the claim recites a computer system similar to the method of claim 1, therefore the claim is rejected on the same premises.
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Hsieh et al. (US 20200285478 A1) in view of the University of California (The Load/Store Unit (LSU), see Non-Final Office Action mailed 10/27/2025), Kim et al. (US 20230333852 A1), Rakib et al. (US 20100281236 A1), and Amirichimeh et al. (US 20040141531 A1).
Regarding claim 22, Hsieh, in view of UC, Kim, and Rakib, teaches the method of claim 1 wherein the plurality of compute slices are coupled in a ring configuration, (The current configuration is in a ring configuration; therefore the slices are coupled in a ring configuration).
Hsieh, in view of UC, Kim, and Rakib, does not teach that the compute slice ring is based on equalized interconnect lengths.
Amirichimeh teaches a ring configuration comprised of equalized interconnect lengths (Fig. 3A, [0059]: The cross link MUX bus 300 is arranged in a circular configuration where each interconnect length between MUX pairs is the same size).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Hsieh, in view of UC, Kim, and Rakib, with the techniques of Amirichimeh to have the interconnects of the ring configuration of compute slices have equal interconnect lengths. By having equal interconnect lengths, signals between the compute slices, signal synchronization may be maintained between the slices, which may be appreciated by one of ordinary skill. Furthermore, changes in size/proportion, i.e., changing the size of the interconnects to be the same length, is considered to be a routine expedient, not a patentable distinction (MPEP 2144.04(IV)(A)).
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Hsieh et al. (US 20200285478 A1) in view of the University of California (The Load/Store Unit (LSU), see Non-Final Office Action mailed 10/27/2025), Kim et al. (US 20230333852 A1), Rakib et al. (US 20100281236 A1), and Arndt et al. (US 20120072707 A1).
Regarding claim 25, Hsieh, in view of UC, Kim, and Rakib, teaches the method of claim 1 wherein the head slice is a compute slice .
Hsieh, in view of UC, Kim, and Rakib, does not teach that the head slice is a compute slice which is pointed to by a head pointer.
Note that the slices in Hsieh act similar to hardware threads as they are capable of executing threads in parallel (see Hsieh, [0038]).
Arndt teaches that the head hardware thread is a compute hardware thread which is pointed to by a head pointer within a hardware status store (Fig. 3B and [0047-0048]: Hardware status store (HWSS) keeps track of assist hardware threads statuses starting with the first assist hardware thread, which can be considered as the head hardware thread and is capable of computation so it’s also a compute hardware thread. The first entry of the HWSS points to the first hardware thread initiated and tracks its current status; therefore the first entry acts as a head pointer pointing to the first hardware thread).
It would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Hsieh, in view of UC, Kim, and Rakib, with the teachings of Arndt to have the head slice be indicated by a head pointer. One of ordinary skill may appreciate tracking the current head slice as they can utilize the pointer to track important information, such as whether the slice is current executing a thread or if the slice is idle.
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Hsieh et al. (US 20200285478 A1) in view of the University of California (The Load/Store Unit (LSU), see Non-Final Office Action mailed 10/27/2025), Kim et al. (US 20230333852 A1), Rakib et al. (US 20100281236 A1), and Anderson et al. (US 20190196790 A1).
Regarding claim 26, the claim is mostly rejected for the same reasons as claim 1. Hsieh, in view of UC, Kim, and Rakib, does not teach a computer program product embodied in a non-transitory computer readable medium for task processing, the computer program product comprising code which causes one or more processors to generate semiconductor logic.
Anderson teaches a computer program product embodied in a non-transitory computer readable medium for task processing, the computer program product comprising code which causes one or more processors to generate semiconductor logic (see [0123-0124]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Hsieh, in view of UC, Kim, and Rakib, with the teachings of Anderson to store a computer program in a non-transitory CRM to generate semiconductor logic. Implementing the design to the CRM would allow one of ordinary skill to model, simulate, and test the design as it’s fundamental to debug and finalize designs prior to processing it on a semiconductor to avoid issues.
Response to Arguments/Amendments
Applicant’s amendments, filed April 21, 2026, with respect to the objections of the specification has been mostly addressed. Examiner believes the title is not specific enough and should be amended further. Examiner has provided guidance regarding the title in the “Specification” section above. Therefore, the objection to the title will be maintained and all other specification objections has been withdrawn.
Applicant’s amendments, filed April 21, 2026, with respect to the objections of the claims has been addressed. The objections of the claims has been withdrawn. However, new objections to the claims have been raised. See “Claim Objections/Recommendations” section above.
Applicant’s amendments, filed April 21, 2026, with respect to the rejections of claims 1-8 and 22-27 under 35 U.S.C. 112(a)/112(b) has been addressed. The rejection of the claims has been withdrawn. However, a new 112(b) rejection has been raised. See “Claim Rejections - 35 USC § 112” section above.
Applicant’s arguments, see page 13, last paragraph to page 17, paragraph 4, filed April 21, 2026, with respect to the rejection(s) of claim(s) 1-8 and 22-27 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of newly found prior art. See 103 rejections above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/E.A./Examiner, Art Unit 2183
/David J. Huisman/Primary Examiner, Art Unit 2183
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