DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a) because they fail to show “an insulating structure having a first surface and a second surface facing each other” as recited in claims 21 and 37, and as described in the specification. Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. MPEP § 608.02(d). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Fig. 4A of the present invention show a solid single layer/structure 210 having a first surface (top surface) opposing the second surface (bottom surface). The insulating structure 210 does not have any gap or space or void inside itself to create/form two inner surfaces that are facing to each other, as recited in claims 21 and 37.
Specification
The disclosure is objected to because of the following informalities:
The specification of the present invention is not clear because it states in paragraph [0061] that “the insulating structure 210 may include the first surface S1 and the opposing (or facing) second surface S2”. However, the drawing (e.g., Fig. 4A) shows that the insulating structure 210 is a solid continuous structure/layer without any internal grooves, spaces or voids that may form/create two inner surfaces that are facing together. The term “opposing (or facing)” in the specification of the present invention is not clear and conflates two mutually exclusive geometric relationships.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
Claim 21-40 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 21 is not clear because it recites, in lines 10-11, the limitation “an insulating structure having a first surface and a second surface facing each other” (emphasis added). The specification of the invention states in paragraph [0061] that “the insulating structure 210 may include the first surface S1 and the opposing (or facing) second surface S2”. However, the drawing (e.g., Fig. 4A) shows that the insulating structure 210 is a solid continuous structure/layer without any internal grooves, spaces or voids that may form/create two inner surfaces that are facing together, and the reference pointers for S1 and S2 are directed to the interior body of this solid structure (210). It is a geometric and physical impossibility for two internal surface of a solid, continuous structure to “face each other” without an intervening space or physical boundary. The term “opposing (or facing)” in the specification of the invention conflates two mutually exclusive geometric relationships. Because the physical boundaries of the first and second surfaces cannot be clearly defined or reconciled with the solid structure shown in the drawings, the scope of the claim is unclear and vague.
For the purpose of examination, the Examiner assumes the above limitation of “an insulating structure having a first surface and a second surface facing each other” (as recited in claim 21, lines 10-11) is:
“an insulating structure having a first surface and an opposing second surface” (emphasis added).
Claim 37 is also not clear because it recites, in lines 12-13, the limitation “an insulating structure having a first surface and a second surface facing each other” (emphasis added). The same reason (as discussed above) for rejecting claim 37 under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph. For the purpose of examination, the Examiner assumes the above limitation of “an insulating structure having a first surface and a second surface facing each other” (as recited in claim 37, lines 12-13) is:
“an insulating structure having a first surface and an opposing second surface” (emphasis added).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 21-37 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-10 of U.S. Patent No. 12,107,061. Although the claims at issue are not identical, they are not patentably distinct from each other because the limitations recited in claims 21-37 of the present invention are recited within claims 1-10 of U.S. Patent No. 12,107,061.
Application No. 18/826,451 (present invention)
U.S. Patent No. 12,107,061 (reference)
Claim 21: An integrated circuit device comprising a peripheral circuit structure and a cell array structure, wherein the peripheral circuit structure comprises: a circuit substrate; a peripheral circuit on the circuit substrate; a first insulating layer covering the circuit substrate and the peripheral circuit; and a first bonding pad in the first insulating layer, and the cell array structure comprises: an insulating structure having a first surface and a second surface facing each other; a conductive plate on the first surface of the insulating structure; a memory cell array on the conductive plate; a second insulating layer covering the first surface of the insulating structure, the conductive plate, and the memory cell array; a second bonding pad arranged in the second insulating layer and contacting the first bonding pad; a plurality of lines on the second surface of the insulating structure; and a plurality of conductive vias penetrating the insulating structure and connecting the plurality of lines to the conductive plate (although claim 1 of U.S. Patent No. 12,107,061 recites “a line” and “a conductive via” in the singular, it would have been obvious to a person of ordinary skill in the art at the time of the invention to duplicate these elements to arrive at “a plurality of lines” and “a plurality of conductive vias” as recited in the present claim, as such a modification represents a mere routine duplication of components to achieve predictable scaling/capacity with no patentable or unexpected distinctiveness) (see claim 1 of U.S. Patent No. 12,107,061).
Claim 1: “An integrated circuit device comprising: a peripheral circuit structure and a cell array structure, wherein the peripheral circuit structure includes a circuit substrate, a peripheral circuit on the circuit substrate, a first insulating layer covering the circuit substrate and the peripheral circuit, and a first bonding pad in the first insulating layer, the cell array structure includes an insulating structure having a first surface and an opposing second surface, a conductive plate on the first surface of the insulating structure, a memory cell array on the conductive plate, a second insulating layer covering the first surface of the insulating structure, the conductive plate, and the memory cell array, a second bonding pad arranged in the second insulating layer in contact with the first bonding pad, a line on the second surface of the insulating structure, and a conductive via penetrating the insulating structure and connecting the conductive plate to the line…”
Claim 22: The integrated circuit device of claim 21, further comprising a plurality of contact plugs arranged on one side of the memory cell array and electrically connecting the plurality of lines to the peripheral circuit (see claims 1 and 4 of U.S. Patent No. 12,107,061).
Claims 1 and 4: “the integrated circuit device further comprises contact plugs electrically connecting the line to the peripheral circuit” (claim 1); and “wherein the contact plugs respectively contact the conductive lines, and the integrated circuit device further comprises an extension line arranged in the second insulating layer to electrically connect the contact plugs” (claim 4).
Claim 23: The integrated circuit device of claim 22, further comprising a conductive line disposed at a same level as that of the conductive plate and electrically connecting the plurality of lines to the plurality of contact plugs (see claim 2 of U.S. Patent No. 12,107,061).
Claim 2: The integrated circuit device of claim 1, further comprising: “conductive lines arranged on both sides of the conductive plate, electrically connected to the line, and disposed at a same level as that of the conductive plate”.
Claim 24: The integrated circuit device of claim 23, wherein a length of each of the plurality of lines is greater than a length of the conductive plate (see claim 5 of U.S. Patent No. 12,107,061).
Claim 5: The integrated circuit device of claim 4, “wherein the extension line is disposed between the memory cell array and the peripheral circuit structure, and a length of the extension line is greater than a length of the conductive plate”.
Claim 25: The integrated circuit device of claim 22, further comprising an extension line disposed between the memory cell array and the peripheral circuit structure in the second insulating layer and electrically connected to the plurality of contact plugs (see claims 4 and 6 of U.S. Patent No. 12,107,061).
Claims 4 and 6: The integrated circuit device of claim 3, “wherein the contact plugs respectively contact the conductive lines, and the integrated circuit device further comprises an extension line arranged in the second insulating layer to electrically connect the contact plugs” (claim 4); and “wherein the extension line is disposed between the memory cell array and the peripheral circuit structure, and a length of the extension line is less than a length of the conductive plate” (claim 6)
Claim 26: The integrated circuit device of claim 25, wherein a length of the extension line is greater than a length of the conductive plate (see claim 5 of U.S. Patent No. 12,107,061).
Claim 5: The integrated circuit device of claim 4, “wherein the extension line is disposed between the memory cell array and the peripheral circuit structure, and a length of the extension line is greater than a length of the conductive plate”.
Claim 27: The integrated circuit device of claim 25, wherein a length of the extension line is less than a length of the conductive plate (see claim 6 of U.S. Patent No. 12,107,061).
Claim 6: The integrated circuit device of claim 4, wherein the extension line is disposed between the memory cell array and the peripheral circuit structure, and a length of the extension line is less than a length of the conductive plate.
Claim 28: The integrated circuit device of claim 21, further comprising a plurality of contact plugs arranged on both sides of the memory cell array and electrically connecting the plurality of lines to the peripheral circuit (see claims 1 and 4 of U.S. Patent No. 12,107,061).
Claims 1 and 4: “the integrated circuit device further comprises contact plugs electrically connecting the line to the peripheral circuit” (claim 1); and “wherein the contact plugs respectively contact the conductive lines, and the integrated circuit device further comprises an extension line arranged in the second insulating layer to electrically connect the contact plugs” (claim 4).
Claim 29: The integrated circuit device of claim 28, further comprising a plurality of conductive lines disposed at a same level as that of the conductive plate and electrically connecting the plurality of lines to the plurality of contact plugs (see claims 2 and 4 of U.S. Patent No. 12,107,061).
Claims 2 and 4: “conductive lines arranged on both sides of the conductive plate, electrically connected to the line, and disposed at a same level as that of the conductive plate” (claim 2); and “wherein the contact plugs respectively contact the conductive lines, and the integrated circuit device further comprises an extension line arranged in the second insulating layer to electrically connect the contact plugs” (claim 4).
Claim 30: The integrated circuit device of claim 29, wherein the plurality of lines extend across the conductive plate and electrically connect the plurality of conductive lines arranged on both sides of the conductive plate (see claim 3 of U.S. Patent No. 12,107,061).
Claim 3: The integrated circuit device of claim 2, “wherein the line extends across the conductive plate to electrically connect the conductive lines arranged on both sides of the conductive plate”.
Claim 31: The integrated circuit device of claim 30, wherein a length of each of the plurality of lines is greater than a length of the conductive plate (see claim 5 of U.S. Patent No. 12,107,061).
Claim 5: The integrated circuit device of claim 4, “wherein the extension line is disposed between the memory cell array and the peripheral circuit structure, and a length of the extension line is greater than a length of the conductive plate”.
Claim 32: The integrated circuit device of claim 21, further comprising a third insulating layer covering the plurality of lines (see claim 4 of U.S. Patent No. 12,107,061).
Claim 4: The integrated circuit device of claim 3, “…the integrated circuit device further comprises an extension line arranged in the second insulating layer to electrically connect the contact plugs”.
Claim 33: The integrated circuit device of claim 32, further comprising an input/output pad arranged on the second surface of the insulating structure and electrically connected to the peripheral circuit, wherein the third insulating layer covers the plurality of lines and the input/output pad (see claims 4 and 10 of U.S. Patent No. 12,107,061).
Claims 4 and 10: “…the integrated circuit device further comprises an extension line arranged in the second insulating layer to electrically connect the contact plugs” (claim 4); and “an input/output pad arranged on the second surface of the insulating structure to electrically connect the peripheral circuit” (claim 10).
Claim 34: The integrated circuit device of claim 33, wherein the third insulating layer comprises an open hole through which a portion of a top surface of the input/output pad is exposed (see claim 10 of U.S. Patent No. 12,107,061 is inherent to include an open hole so that the an input/output can be exposed for external connection).
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Claim 10: The integrated circuit device of claim 1, further comprising: “an input/output pad arranged on the second surface of the insulating structure to electrically connect the peripheral circuit”.
Claim 35: The integrated circuit device of claim 21, wherein the plurality of lines are arranged at regular intervals (see claims 2 and 3 of U.S. Patent No. 12,107,061, the arranged lines inherently have regular intervals).
Claims 2 and 3: “further comprising: conductive lines arranged on both sides of the conductive plate, electrically connected to the line, and disposed at a same level as that of the conductive plate” (claim 2); and “wherein the line extends across the conductive plate to electrically connect the conductive
lines arranged on both sides of the conductive plate” (claim 3).
Claim 36: The integrated circuit device of claim 35, wherein the plurality of lines are electrically connected to each other (see claim 2 of U.S. Patent No. 12,107,061).
Claim 2: The integrated circuit device of claim 1, further comprising: “conductive lines arranged on both sides of the conductive plate, electrically connected to the line, and disposed at a same level as that of the conductive plate”.
Claim 37: A semiconductor package comprising a plurality of integrated circuit devices stacked in a vertical direction, wherein each of the plurality of integrated circuit devices comprises a peripheral circuit structure and a cell array structure, wherein the peripheral circuit structure comprises: a circuit substrate; a peripheral circuit on the circuit substrate; a first insulating layer covering the circuit substrate and the peripheral circuit; and a first bonding pad in the first insulating layer, and the cell array structure comprises: an insulating structure having a first surface and a second surface facing each other; a conductive plate on the first surface of the insulating structure; a memory cell array on the conductive plate; a second insulating layer covering the first surface of the insulating structure, the conductive plate, and the memory cell array; a second bonding pad arranged in the second insulating layer and contacting the first bonding pad; a plurality of lines on the second surface of the insulating structure; a plurality of conductive vias penetrating the insulating structure and connecting the plurality of lines to the conductive plate; and a plurality of contact plugs arranged on at least one side of the memory cell array and electrically connecting the plurality of lines to the peripheral circuit (although claims 1 and 4 of U.S. Patent No. 12,107,061 recites “a line” and “a conductive via” in the singular, it would have been obvious to a person of ordinary skill in the art at the time of the invention to duplicate these elements to arrive at “a plurality of lines” and “a plurality of conductive vias” as recited in the present claim, as such a modification represents a mere routine duplication of components to achieve predictable scaling/capacity with no patentable or unexpected distinctiveness) (see claims 1 and 4 of U.S. Patent No. 12,107,061).
Claims 1 and 4: “An integrated circuit device comprising: a peripheral circuit structure and a cell array structure, wherein the peripheral circuit structure includes a circuit substrate, a peripheral circuit on the circuit substrate, a first insulating layer covering the circuit substrate and the peripheral circuit, and a first bonding pad in the first insulating layer, the cell array structure includes an insulating structure having a first surface and an opposing second surface, a conductive plate on the first surface of the insulating structure, a memory cell array on the conductive plate, a second insulating layer covering the first surface of the insulating structure, the conductive plate, and the memory cell array, a second bonding pad arranged in the second insulating layer in contact with the first bonding pad, a line on the second surface of the insulating structure, and a conductive via penetrating the insulating structure and connecting the conductive plate to the line, and the integrated circuit device further comprises contact plugs electrically connecting the line to the peripheral circuit” (claim 1); and “wherein the contact plugs respectively contact the conductive lines, and the integrated circuit device further comprises an extension line arranged in the second insulating layer to electrically connect the contact plugs” (claim 4).
Claim 38: The semiconductor package of claim 37, wherein each of the plurality of integrated circuit devices comprises a plurality of conductive lines disposed at a same level as that of the conductive plate and electrically connecting the plurality of lines to the plurality of contact plugs (see claims 2 and 4 of U.S. Patent No. 12,107,061).
Claims 2 and 4: “conductive lines arranged on both sides of the conductive plate, electrically connected to the line, and disposed at a same level as that of the conductive plate” (claim 2); and “wherein the contact plugs respectively contact the conductive lines, and the integrated circuit device further comprises an extension line arranged in the second insulating layer to electrically connect the contact plugs” (claim 4).
Claim 39: The semiconductor package of claim 37, wherein the plurality of lines are arranged at regular intervals and are electrically connected to each other (see claims 2 and 3 of U.S. Patent No. 12,107,061, the arranged lines inherently have regular intervals).
Claims 2 and 3: “further comprising: conductive lines arranged on both sides of the conductive plate, electrically connected to the line, and disposed at a same level as that of the conductive plate” (claim 2); and “wherein the line extends across the conductive plate to electrically connect the conductive
lines arranged on both sides of the conductive plate” (claim 3).
Claim 40: The semiconductor package of claim 37, wherein a length of the plurality of contact plugs in the vertical direction is greater than a length of the memory cell array in the vertical direction (see claim 4 and 9 of U.S. Patent No. 12,107,061, it is inherent to include a length of the plurality of contact plugs in the vertical direction is greater than a length of the memory cell array in the vertical direction).
Claim 4 and 9: The integrated circuit device of claim 3, “wherein the contact plugs respectively contact the conductive lines, and the integrated circuit device further comprises an extension line arranged in the second insulating layer to electrically connect the contact plugs” (claim 4); and “wherein the contact plugs have a trapezoidal shape defined by a width increasing as a distance from the conductive plate increases, and the conductive via has an inverted trapezoidal shape defined by a width increasing as the distance from the conductive plate increases” (claim 9).
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THANH Y TRAN whose telephone number is (571)272-2110. The examiner can normally be reached M-F, 10am-10pm (flex) (PST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571)272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Thanh Y. Tran/Primary Examiner, Art Unit 2817
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