DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to amendments/remarks for application 18826673 filed on 03/19/2026. Claims 1-25 are presented for examination, of which claims 17-25 are withdrawn from consideration.
Prior Art Rejections
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 7, 8 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Oshima et al. (US Patent Pub. No. 2005/0264550 A1) in view of Yamamoto et al. (US Patent Pub. No. 2005/0052443 A1).
Regarding claim 1, Oshima teaches A driving circuit for display panel (Oshima, Fig. 11, drivers 37, 38, power source circuit 38 and current controller 900), comprising:
a current generating circuit (Oshima, Fig. 11, power source circuit 38), generating a first current and a second current for driving a display element, and the first current smaller than the second current (Oshima, Figs. 14A-14C, taking 14A as example, frame 1 for 1st layer is provided with a current value of 1, and frame 3 of 1st layer is provided with a current value of 4); and
a current control circuit (Oshima, Fig. 11, current controller 900), controlling the current generating circuit to generate the first current and the second current (Oshima, Figs. 14A-14C, taking 14A as example, frame 1 for 1st layer is provided with a current value of 1, and frame 3 of 1st layer is provided with a current value of 4);
wherein the current control circuit controls the current generating circuit to generate the first current for driving the display element to emit light in an initial stage, and controls the current generating circuit to generate the first current and the second current for driving the display element to emit light after the initial stage (Oshima, Figs. 14A-14C, taking 14A as example, frame 1 for 1st layer is provided with a current value of 1, and frame 3 of 1st layer is provided with a current value of 4, i.e., frame 3 is after frame 1; Oshima, [0160]-[0162], supplying current to emit light).
Oshima does not seem to explicitly teach the scanning timing is according to a clock signal. However, in the art of driving display, Yamamoto teaches a clock signal is generally used to keep all the operation, including scanning of display to be in sync (Yamamoto, Figs. 5, 9, 10 and 12, clock signal). Before the time of first effective filing of the claimed invention, one of ordinary skill in the art could have combined the elements as claimed by known methods, and that in combination, each element merely performs the same function as it does separately.
The results of the combination would have been predictable and resulted in also include a clock signal as suggested by Yamamoto in the display driver of Oshima.
Therefore, the claimed subject matter would have been obvious to a person having ordinary skill in the art before the time of first effective filing of the claimed invention.
Regarding claim 2, Oshima in view of Yamamoto teaches the limitation of claim 1, and further teaches the current control circuit controls the current generating circuit in a cycle according to the clock signal; the cycle includes the initial stage; the current control circuit controls the current generating circuit to generate the first current in the initial stage of the cycle (Oshima, Figs. 14A-14C, taking 14A as example, frame 3 is after frame 1); and the current control circuit controls the current generating circuit to generate the first current and the second current after the initial stage (Oshima, Figs. 14A-14C, taking 14A as example current level for 1st layer is provided with levels 1 and 4 repeatedly after frame 1).
Regarding claim 7, Oshima in view of Yamamoto teaches the limitation of claim 1. Oshima in view of Yamamoto does not seem to explicitly teach the current generating circuit further comprises:
a first current circuit, generating the first current; and
a second current circuit, generating the second current.
The difference between the teachings of Oshima in view of Yamamoto and claim 7 is the separation of a single current generating circuit into two current circuit. However, making separable does not distinguish over the prior arts (MPEP 2144.04 V.). Hence, claim 7 is still unpatentable over Oshima in view of Yamamoto.
Regarding claim 8, Oshima teaches a driving circuit for display panel (Oshima, Fig. 11, drivers 37, 38, power source circuit 38 and current controller 900), comprising:
a current generating circuit, generating at least one current for driving a display element (Oshima, Fig. 11, power source circuit 38); and
a current control circuit (Oshima, Fig. 11, current controller 900), controlling the current generating circuit to generate the current in a plurality of cycles, each cycle including an initial stage, and the current control circuit controlling the current generating circuit to generate the current for driving a display element to emit light in the initial stage of a cycle for every N cycles of the plurality of cycles with N greater than 2 (Oshima, Figs. 14A-14C, taking 14A as example, frame 1 for 1st layer is provided with a current value of 1, and frame 3 of 1st layer is provided with a current value of 4, i.e., frame 3 is after frame 1, and is repeated every 3 frames; Oshima, [0160]-[0162], supplying current to emit light).
Oshima does not seem to explicitly teach the scanning timing is according to a clock signal. However, in the art of driving display, Yamamoto teaches a clock signal is generally used to keep all the operation, including scanning of display to be in sync (Yamamoto, Figs. 5, 9, 10 and 12, clock signal). Before the time of first effective filing of the claimed invention, one of ordinary skill in the art could have combined the elements as claimed by known methods, and that in combination, each element merely performs the same function as it does separately.
The results of the combination would have been predictable and resulted in also include a clock signal as suggested by Yamamoto in the display driver of Oshima.
Therefore, the claimed subject matter would have been obvious to a person having ordinary skill in the art before the time of first effective filing of the claimed invention.
Regarding claim 13, Oshima in view of Yamamoto teaches the limitation of claim 8, and further teaches the at least one current includes a first current and a second current, the first current is smaller than the second current (shima, Figs. 14A-14C, taking 14A as example, frame 1 for 1st layer is provided with a current value of 1, and frame 3 of 1st layer is provided with a current value of 4); the current control circuit controls the current generating circuit to generate the first current in the initial 2 stage of one of every N cycles; and after the initial stage of each cycle, the current control circuit controls the current generating circuit to generate the first current and the second current (Oshima, Figs. 14A-14C, taking 14A as example current level for 1st layer is provided with levels 1 and 4 repeatedly after frame 1).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Oshima et al. (US Patent Pub. No. 2005/0264550 A1) in view of Yamamoto et al. (US Patent Pub. No. 2005/0052443 A1) and Takagi (US Patent Pub. No. 2002/0000982 A1).
Regarding claim 12, Oshima in view of Yamamoto teaches the limitation of claim 8. Oshima in view of Yamamoto does not seem to explicitly teach a period counter counting the plurality of cycles, and driving the current control circuit to control the current generating circuit to generate the current in the initial stage of one of every N cycles of the plurality of cycles.
However, in a related art of controlling displays, Takagi teaches a counter is used to control enable and disable of signals (Takagi, [0089]-[0092]).
Before the time of the first effective filing of the claimed invention, it would have been obvious to a person ordinary skill in the art to further include a counter, as suggested by Takagi, to control the current output of Oshima in view of Yamamoto. The suggestion/motivation would have been in order to allow for a high frequency clock to be used for higher accuracy while still be able to output a signal that is longer than a single clock cycle (Takagi, Fig. 6, high frequency clock CLK when ENI is larger than a single clock cycle).
Response to Arguments
Applicant’s arguments with respect to the claims as amended have been considered but are moot because the arguments do not apply to the current reference combination including the new reference of Oshima being used in the current rejections under new grounds of rejection necessitated by amendment. See above rejections for full detail.
Allowable Subject Matter
Claims 3-6, 9-11 and 14-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art, whether considered alone or in combination, fail to disclose the technical features of the claimed invention in context as a whole. Specifically, the determination of the first driving time and the second driving time according to the pixel data and providing the current in the respective orders in the manner claimed as a whole, is not sufficiently taught or suggested in the prior art.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DONG HUI LIANG whose telephone number is (571)272-0487. The examiner can normally be reached M-F 7am-3pm EST.
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/DONG HUI LIANG/Primary Examiner, Art Unit 2629
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