DETAILED ACTION
This Office Action is in response to an application that was filed on 09/06/2024. Claims 1-20 are presented for examination consideration.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
In independent claim 1, the limitation phrase “pathways” in the limitation “a nonconductive matrix surrounding the plurality of conductors and configured to isolate each conductor of the plurality of conductors from one another along an axis that is perpendicular to the plurality of pathways”, is confusing. The premise of the confusion is compounded by the limitation phrase “pathways” NOT having the proper antecedent basis. Therefore, the claim DOES NOT make it clear if the cited limitation structure “pathways” is the “pathways” in the earlier limitation “conductive pathways” OR entirely different structure. The limitation “a nonconductive matrix surrounding the plurality of conductors and configured to isolate each conductor of the plurality of conductors from one another along an axis that is perpendicular to the plurality of pathways” will be examine as “a nonconductive matrix surrounding the plurality of conductors and configured to isolate each conductor of the plurality of conductors from one another along an axis that is perpendicular to the plurality of conductive pathways”.
Claims 2-10 are rejected since the base independent claim 1 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph.
In independent claim 11, the limitation phrase “PCB” in the limitation “and a universal substrate placed at a third position in the PCB package and interconnecting the IC unit and PCB with one another”, is confusing. The premise of the confusion is compounded by the limitation phrase “PCB” NOT having the proper antecedent basis. Therefore, the claim DOES NOT make it clear if the cited limitation structure “PCB” is the “PCB” in the earlier limitation “PCB unit” OR entirely different structure. The limitation “and a universal substrate placed at a third position in the PCB package and interconnecting the IC unit and PCB with one another” will be examine as “and a universal substrate placed at a third position in the PCB package and interconnecting the IC unit and PCB unit with one another”.
Claims 12-17 are rejected since the base independent claim 11 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph.
In independent claim 11, the limitation phrase “pathways” in the limitation “a nonconductive matrix surrounding the plurality of conductors and configured to isolate each conductor of the plurality of conductors from one another along an axis that is perpendicular to the plurality of pathways”, is confusing. The premise of the confusion is compounded by the limitation phrase “pathways” NOT having the proper antecedent basis. Therefore, the claim DOES NOT make it clear if the cited limitation structure “pathways” is the “pathways” in the earlier limitation “conductive pathways” OR entirely different structure. The limitation “a nonconductive matrix surrounding the plurality of conductors and configured to isolate each conductor of the plurality of conductors from one another along an axis that is perpendicular to the plurality of pathways” will be examine as “a nonconductive matrix surrounding the plurality of conductors and configured to isolate each conductor of the plurality of conductors from one another along an axis that is perpendicular to the plurality of conductive pathways”.
Claims 12-17 are rejected since the base independent claim 11 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph.
In claim 12, the limitation phrase “PCB” in the limitation “and wherein the IC unit and PCB of the PCB package are free from being conductive along the at least one non-linear section or are conductive along the at least one non-linear section”, is confusing. The claim DOES NOT make it clear if the cited limitation structure “PCB” is the “PCB” in the earlier limitation “PCB unit” of independent claim 11 OR entirely different structure. The limitation “and wherein the IC unit and PCB of the PCB package are free from being conductive along the at least one non-linear section or are conductive along the at least one non-linear section” will be examine as “and wherein the IC unit and PCB unit of the PCB package are free from being conductive along the at least one non-linear section or are conductive along the at least one non-linear section”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4, 7, 8, 9, and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Otsubo (US20140034365A1 and Otsubo hereinafter).
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Reproduced Drawing A of Fig. 8 from Otsubo (US20140034365A1)
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Reproduced Drawing B of Fig. 11 from Otsubo (US20140034365A1)
Regarding claim 1, Otsubo discloses a universal substrate for a printed circuit board (PCB) package (item A of Reproduced Drawing A & items 20i, 3a, 3b, 3, 6a, 6b of Fig. 8 and ¶[0039-0041] shows and indicates universal substrate A {substrate comprised of the following structures: first resin layer 3a and second resin layer 3b of resin layer 3, where first resin layer 3a and second resin layer 3b are joined by skin layer joint plane 30; and by via conductor 6a and via conductor 6b joined by skin layer joint plane 30} for printed circuit board (PCB) package 20i {flexible multilayer substrate 20i}), the universal substrate comprising: a first end and a second end opposite to the first end (items B, C of Reproduced Drawing A & Fig. 8 and ¶[0039-0041] shows and indicates universal substrate A is comprised first end B and second end C opposite to first end B); a plurality of conductors located between the first end and the second end (item D of Reproduced Drawings A-B & items 6a, 6b, 30 of Fig. 8 & item 30 of Fig. 11 and ¶[0039-0041] shows and indicates the plurality of conductors D {conductive structure formed by via conductor 6a and via conductor 6b joined by skin layer joint plane 30} located between first end B and second end C), the plurality of conductors having a first connection end, a second connection end opposite to the first connection end (items E, F of Reproduced Drawing A & Fig. 8 and ¶[0039-0041] shows and indicates the plurality conductors D having first connection end E {top connection of via conductor 6b of conductor D} and second connection end F {bottom connection of via conductor 6a of conductor D} opposite to first connection end E), and a plurality of conductive pathways defined between the first connection end and the second connection end (Reproduced Drawings A-B & Figs. 8_11 and ¶[0039-0041] shows and indicates a plurality of conductive pathways established by conductors D defined between first connection end E and second connection end F); a nonconductive matrix surrounding the plurality of conductors and configured to isolate each conductor of the plurality of conductors from one another along an axis that is perpendicular to the plurality of conductive pathways (item G of Reproduced Drawings A-B & item 30 of Figs. 8_11 and ¶[0039-0041] shows and indicates nonconductive matrix G {nonconductive matrix formed by first resin layer 3a and second resin layer 3b of resin layer 3 joined by skin layer joint plane 30} surrounding the plurality conductors D and configured to isolate each conductor D of the plurality conductors D from one another along axis 30 {axis of skin layer joint plane 30} that is perpendicular to the plurality of conductive pathways established by conductors D); and at least one non-linear section defined between the first connection end and the second connection end (item H of Reproduced Drawings A-B & item A of Fig. 8 & Fig. 11 and ¶[0040] shows and indicates non-linear section H of A portion {A portion in FIG. 8 where FIG. 11 represents the state where the flexible multilayer substrate 20i is flexed; where A portion includes the bent portion of flexible multilayer substrate 20i} defined between first connection end E and second connection end F); wherein at least two devices of the PCB package have conductivity at any two positions along the first connection end and the second connection end (items I, J of Reproduced Drawing A & items 7, 18, 19 of Fig. 8 and ¶[0034_0036-0037 & 0050] shows and indicates where upper device I {device formed from the upper conductor pattern 7 on the upper surface of universal substrate A to external electrode 19} of PCB package 20i; and where lower device J {device formed from the lower conductor pattern 7 on the lower surface of universal substrate A to external electrode 18} of PCB package 20i; and where upper device I and lower device J have conductivity at any two positions along first connection end E and second connection end F).
Regarding claim 4, Otsubo discloses a universal substrate, further comprising: a first connection section defined between the first end of the universal substrate and the at least one non-linear section; and a second connection section defined between the second end of the universal substrate that is opposite to the first end and the at least one non-linear section; wherein the second connection section is positioned above the first connection section (Reproduced Drawings A-B & Figs. 8_11 and ¶[0039-0041] shows and indicates universal substrate A is further comprised of the first connection section part of second connection end F defined between first end B of universal substrate A and non-linear section H of A portion; and where the second connection section part of first connection end E that is defined between second end C of universal substrate A that is opposite to first end B and non-linear section H of A portion; and where the second connection section part of first connection end E is positioned above the first connection section part of second connection end F).
Regarding claim 7, Otsubo discloses a universal substrate, wherein the first connection end is substantially parallel to the second connection end (Reproduced Drawing A & Fig. 8 and ¶[0039-0041] shows and indicates where first connection end E is substantially parallel to second connection end F).
Regarding claim 8, Otsubo discloses a universal substrate, wherein the first connection end is positioned at a range of angles relative to the second connection end from about 0 degrees to about 90 degrees (Reproduced Drawings A-B & Figs. 8_11 and ¶[0022_0039-0041] shows and indicates where first connection end E is positioned at a range of angles relative to the second connection end F from about 0 degrees to about 90 degrees during the transition of non-linear section H of A portion from Fig. 8 to Fig. 11).
Regarding claim 9, Otsubo discloses a universal substrate, wherein the first connection end is positioned at a range of angles relative to the second connection end from about 0 degrees to about 180 degrees (Reproduced Drawings A-B & Figs. 8_11 and ¶[0022_0039-0041] shows and indicates where first connection end E is positioned at a range of angles relative to the second connection end F from about 0 degrees to about 180 degrees during the final transition of non-linear section H of A portion from Fig. 8 to Fig. 11).
Regarding claim 10, Otsubo discloses a universal substrate, wherein the universal substrate is formed from a resilient, flexible material (Reproduced Drawings A-B & Figs. 8_11 and ¶[0039-0041] shows and indicates where universal substrate A is understood to be formed from a resilient, flexible material during the transition of non-linear section H of A portion from Fig. 8 to Fig. 11).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 11, 12, 13, 14, 15, 16, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Otsubo, in view of Sakai et al. (US20170347447A1 and Sakai hereinafter).
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Reproduced Drawing A of Fig. 8 from Otsubo (US20140034365A1)
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Reproduced Drawing B of Fig. 11 from Otsubo (US20140034365A1)
Regarding claim 11, Otsubo discloses a printed circuit board (PCB) package, comprising: an unit placed at a first position in the PCB package (items K, I of Reproduced Drawing A & items 20i, 7, 19 of Fig. 8 and ¶[0034_0036-0037_0039 & 0050] shows and indicates printed circuit board (PCB) package 20i {flexible multilayer substrate 20i} that is comprised of a unit that is comprised of upper device I {unit comprised of a device formed from the upper conductor pattern 7 on the upper surface of universal substrate A to external electrode 19} placed at first position K in PCB package 20i); a PCB unit placed at a second position in the PCB package (items L, J of Reproduced Drawing A & item 19 of Fig. 8 and ¶[0034_0036-0037_0039 & 0050] is understood to show and indicate a PCB unit that is comprised of lower device J {PCB comprised of a device formed from the lower conductor pattern 7 on the lower surface of universal substrate A to external electrode 18} placed at second position L in PCB package 20i); and a universal substrate placed at a third position in the PCB package and interconnecting the unit and PCB unit with one another (items A, M of Reproduced Drawing A & items 20i, 3a, 3b, 3, 6a, 6b, 30 of Fig. 8 & item 30 of Fig. 11 and ¶[0039-0041] shows and indicates universal substrate A {substrate comprised of the following structures: first resin layer 3a and second resin layer 3b of resin layer 3, where first resin layer 3a and second resin layer 3b are joined by skin layer joint plane 30; and by via conductor 6a and via conductor 6b joined by skin layer joint plane 30} placed at third position M in PCB package 20i and interconnecting the unit that is comprised of upper device I and PCB unit that is comprised of lower device J with one another); wherein the universal substrate comprises: a first end and a second end opposite to the first end (items B, C of Reproduced Drawing A & Fig. 8 and ¶[0039-0041] shows and indicates universal substrate A is comprised first end B and second end C opposite to first end B); a plurality of conductors located between the first end and the second end (item D of Reproduced Drawings A-B & items 6a, 6b, 30 of Fig. 8 & item 30 of Fig. 11 and ¶[0039-0041] shows and indicates the plurality of conductors D {conductive structure formed by via conductor 6a and via conductor 6b joined by skin layer joint plane 30} located between first end B and second end C), the plurality of conductors having a first connection end that connects with the unit, a second connection end opposite to the first connection end and that connects with the PCB unit (items E, F of Reproduced Drawing A & Fig. 8 and ¶[0039-0041] shows and indicates the plurality conductors D having first connection end E {top connection of via conductor 6b of conductor D} that connects with the unit that is comprised of upper device I and second connection end F {bottom connection of via conductor 6a of conductor D} opposite to first connection end E and that connects with the PCB unit that is comprised of lower device J), and a plurality of conductive pathways defined between the first connection end and the second connection end (Reproduced Drawings A-B & Figs. 8_11 and ¶[0039-0041] shows and indicates a plurality of conductive pathways established by conductors D defined between first connection end E and second connection end F); a nonconductive matrix surrounding the plurality of conductors and configured to isolate each conductor of the plurality of conductors from one another along an axis that is perpendicular to the plurality of conductive pathways (item G of Reproduced Drawings A-B & item 30 of Figs. 8_11 and ¶[0039-0041] shows and indicates nonconductive matrix G {nonconductive matrix formed by first resin layer 3a and second resin layer 3b of resin layer 3 joined by skin layer joint plane 30} surrounding the plurality conductors D and configured to isolate each conductor D of the plurality conductors D from one another along axis 30 {axis of skin layer joint plane 30} that is perpendicular to the plurality of conductive pathways established by conductors D); and at least one non-linear section defined between the first connection end and the second connection end (item H of Reproduced Drawings A-B & item A of Fig. 8 & Fig. 11 and ¶[0040] shows and indicates non-linear section H of A portion {A portion in FIG. 8 where FIG. 11 represents the state where the flexible multilayer substrate 20i is flexed; where A portion includes the bent portion of flexible multilayer substrate 20i} defined between first connection end E and second connection end F).
Otsubo discloses the claimed invention except to explicitly disclose an integrated circuit (IC) unit placed at a first position in the PCB package; a PCB unit placed at a second position in the PCB package; and a universal substrate placed at a third position in the PCB package and interconnecting the IC unit and PCB unit with one another.
Sakai discloses an integrated circuit (IC) unit placed at a first position in the PCB package; a PCB unit placed at a second position in the PCB package; and a universal substrate placed at a third position in the PCB package and interconnecting the IC unit and PCB unit with one another (items 19, 2, 16, 18, 7 of Fig. 28 and ¶[0058 & 0064-0065] shows and indicates where an integrated circuit (IC) unit is placed at first position 19-mounted-component {conductor pattern 7 formed on resin layer 2 located in the uppermost layer of the substrate serves as an external electrode 19 for mounting an IC component} in PCB package of Fig. 24; PCB unit 2-three-bottom-16_18 {PCB constituted of the three bottom resin layer 2 to external electrode 18} placed at second position 2-three-bottom {three bottom resin layers 2} in PCB package of Fig. 24; and where universal substrate 2-two-top-16_19 {substrate constituted of the two top resin layer 2 to external electrode 19} placed at third position 2-two-top {two top resin layers 2} in PCB package of Fig. 24 and interconnecting the IC unit and PCB unit 2-three-bottom-16_18 with one another; therefore, Otsubo will have the PCB package with the following limitations by incorporating the structure of Sakai: an integrated circuit (IC) unit placed at the first position in the PCB package; a PCB unit placed at the second position in the PCB package; and the universal substrate placed at the third position in the PCB package and interconnecting the IC unit and PCB unit with one another).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate an integrated circuit (IC) unit placed at a first position in the PCB package; a PCB unit placed at a second position in the PCB package; and a universal substrate placed at a third position in the PCB package and interconnecting the IC unit and PCB unit with one another into the structure of Otsubo. One would have been motivated in the PCB package of Otsubo and have the integrated circuit (IC) unit be placed at the first position in the PCB package, and have the PCB unit be placed at the second position in the PCB package, and have the universal substrate be placed at the third position in the PCB package and interconnecting the IC unit and PCB unit with one another, in order to design a PCB package with external electrodes forming the initial first position so as to mount an IC component and have a universal substrate in the middle position to function as an interconnect to a PCB unit in the second position, as implied in ¶[0064] and Fig. 24 by Sakai, in the PCB package of Otsubo.
Regarding claim 12, modified Otsubo discloses a PCB package, wherein the at least one non-linear section is a continuous curved section, and wherein the IC unit and PCB unit of the PCB package are conductive along the at least one non-linear section (Otsubo: Reproduced Drawings A-B & Figs. 8_11 and ¶[0040] shows and indicates where non-linear section H of A portion is a continuous curved section; and where unit that is comprised of upper device I and PCB unit that is comprised of lower device J of PCB package 20i are conductive along non-linear section H of A portion; Sakai: Fig. 28 and ¶[0058 & 0064-0065] shows and indicates where an integrated circuit (IC) unit is placed at first position 19-mounted-component).
Regarding claim 13, modified Otsubo discloses a PCB package, wherein the universal substrate further comprises: a first connection section defined between the first end of the universal substrate and the at least one non-linear section; and a second connection section defined between the second end of the universal substrate that is opposite to the first end and the at least one non-linear section; wherein the second connection section is positioned above the first connection section (Otsubo: Reproduced Drawings A-B & Figs. 8_11 and ¶[0039-0041] shows and indicates universal substrate A is further comprised of the first connection section part of second connection end F defined between first end B of universal substrate A and non-linear section H of A portion; and where the second connection section part of first connection end E that is defined between second end C of universal substrate A that is opposite to first end B and non-linear section H of A portion; and where the second connection section part of first connection end E is positioned above the first connection section part of second connection end F).
Regarding claim 14, modified Otsubo discloses a PCB package, wherein the first connection end is substantially parallel to the second connection end (Otsubo: Reproduced Drawing A & Fig. 8 and ¶[0039-0041] shows and indicates where first connection end E is substantially parallel to second connection end F).
Regarding claim 15, modified Otsubo discloses a PCB package, wherein the first connection end is positioned at a range of angles relative to the second connection end from about 0 degrees to about 90 degrees (Otsubo: Reproduced Drawings A-B & Figs. 8_11 and ¶[0022_0039-0041] shows and indicates where first connection end E is positioned at a range of angles relative to the second connection end F from about 0 degrees to about 90 degrees during the transition of non-linear section H of A portion from Fig. 8 to Fig. 11).
Regarding claim 16, modified Otsubo discloses a PCB package, wherein the first connection end is positioned at a range of angles relative to the second connection end from about 0 degrees to about 180 degrees (Otsubo: Reproduced Drawings A-B & Figs. 8_11 and ¶[0022_0039-0041] shows and indicates where first connection end E is positioned at a range of angles relative to the second connection end F from about 0 degrees to about 180 degrees during the final transition of non-linear section H of A portion from Fig. 8 to Fig. 11).
Regarding claim 17, modified Otsubo discloses a PCB package, wherein the universal substrate is formed from a resilient, flexible material (Otsubo: Reproduced Drawings A-B & Figs. 8_11 and ¶[0039-0041] shows and indicates where universal substrate A is understood to be formed from a resilient, flexible material during the transition of non-linear section H of A portion from Fig. 8 to Fig. 11).
Claims 18, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Otsubo in view of Sakai.
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Reproduced Drawing A of Fig. 8 from Otsubo (US20140034365A1)
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Reproduced Drawing B of Fig. 11 from Otsubo (US20140034365A1)
Regarding claim 18, Otsubo discloses a method, comprising: forming at least one non-linear section into a universal substrate (items A, H of Reproduced Drawing A & item H of Reproduced Drawing B & items 20i, 3a, 3b, 3, 6a, 6b, 30 of Fig. 8 & item 30 of Fig. 11 and ¶[0039-0041] shows and indicates the method that is comprised of forming non-linear section H of A portion {A portion in FIG. 8 where FIG. 11 represents the state where the flexible multilayer substrate 20i is flexed; where A portion includes the bent portion of flexible multilayer substrate 20i} into universal substrate A {substrate comprised of the following structures: first resin layer 3a and second resin layer 3b of resin layer 3, where first resin layer 3a and second resin layer 3b are joined by skin layer joint plane 30; and by via conductor 6a and via conductor 6b joined by skin layer joint plane 30}); connecting a unit with a first connection end of a universal substrate defined between a first end of the universal substrate and the at least one non-linear section (items I, E, B of Reproduced Drawing A & items 20i, 7, 19 of Fig. 8 and ¶[0034_0036-0037_0039 & 0050] shows and indicates the method of connecting a unit that is comprised of upper device I {unit comprised of a device formed from the upper conductor pattern 7 on the upper surface of universal substrate A to external electrode 19} with first connection end E {top connection of via conductor 6b of conductor formed by via conductor 6a and via conductor 6b joined by skin layer joint plane 30} of universal substrate A defined between first end B of universal substrate A and non-linear section H of A portion); connecting a printed circuit board (PCB) with a second connection end of the universal substrate defined between a second end of the universal substrate and the at least one non-linear section (items J, F, C of Reproduced Drawing A & item 18 of Fig. 8 and ¶[0034_0036-0037_0039 & 0050] is understood to show and indicate connecting a PCB that is comprised of lower device J {PCB comprised of a device formed from the lower conductor pattern 7 on the lower surface of universal substrate A to external electrode 18} with second connection end F {bottom connection of via conductor 6a of conductor formed by via conductor 6a and via conductor 6b joined by skin layer joint plane 30} of universal substrate A defined between second end C of universal substrate A and non-linear section H of A portion); and interconnecting the unit and the PCB by the universal substrate (Reproduced Drawing A-B & Figs. 8_11 and ¶[0039-0041] shows and indicates the method further provides interconnecting the unit that is comprised of upper device I and PCB that is comprised of lower device J by universal substrate A).
Otsubo discloses the claimed method except to explicitly disclose wherein connecting an integrated circuit (IC) unit with a first connection end.
Sakai discloses wherein connecting an integrated circuit (IC) unit with a first connection end (items 19, 7, 2 of Fig. 28 and ¶[0064] shows and indicates where connecting an integrated circuit (IC) unit with a first connection end 19 {conductor pattern 7 formed on resin layer 2 located in the uppermost layer of the substrate serves as an external electrode 19 for mounting an IC component}; therefore, Otsubo will have the method with the following method limitations by incorporating the structure of Sakai into the method: connecting an integrated circuit (IC) unit with the first connection end of a universal substrate that is defined between the first end of the universal substrate; and interconnecting the IC unit and the PCB by the universal substrate).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein connecting an integrated circuit (IC) unit with a first connection end into the method of Otsubo. One would have been motivated in the method of Otsubo and have connecting the integrated circuit (IC) unit with the first connection end, in order for the method to design a PCB package with external electrodes so as to mount an IC component, as indicated in ¶[0064] and Fig. 24 by Sakai, in the method of Otsubo.
Regarding claim 19, modified Otsubo discloses a method, further comprising: aligning a first build-up component and a second build-up component with one another; aligning the universal substrate between the first build-up component and the second build-up component; and joining the first build-up component, the second build-up component, and the universal substrate together; wherein the step forming the at least one non-linear section into the universal substrate further includes that the at least one non-linear section is formed between the first build-up component and the second build-up component (Otsubo: Reproduced Drawing A & items 20i, 7, 18, 19 of Fig. 8 and ¶[0034_0036-0037_0039-0041 & 0050] shows and indicates the method is further comprised of aligning a first build-up component forming a unit that is comprised of upper device I {build-up component forming a unit comprised of a device formed from the upper conductor pattern 7 on the upper surface of universal substrate A to external electrode 19} with first connection end E {top connection of via conductor 6b of conductor formed by via conductor 6a and via conductor 6b joined by skin layer joint plane 30} and a second build-up component, what is understood to show and indicate, forming a PCB that is comprised of lower device J {build-up component forming a PCB comprised of a device formed from the lower conductor pattern 7 on the lower surface of universal substrate A to external electrode 18} with one another; then the method is further comprised of universal substrate A between the first build-up component forming a unit that is comprised of upper device I and the second build-up component forming a PCB that is comprised of lower device J; and joining the first build-up component forming a unit that is comprised of upper device I and the second build-up component forming a PCB that is comprised of lower device J, and universal substrate A together; where the step forming non-linear section H of A portion into universal substrate A further includes that non-linear section H of A portion is formed between the first build-up component forming a unit that is comprised of upper device I and the second build-up component forming a PCB that is comprised of lower device J).
Regarding claim 20, modified Otsubo discloses a method, wherein the first connection end is positioned at a range of angles relative to the second connection end from about 0 degrees to about 180 degrees (Otsubo: Reproduced Drawings A-B & Figs. 8_11 and ¶[0022_0039-0041] shows and indicates where the method has first connection end E be in positioned at a range of angles relative to the second connection end F from about 0 degrees to about 180 degrees during the final transition of non-linear section H of A portion from Fig. 8 to Fig. 11).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUILLERMO J EGOAVIL whose telephone number is (571)270-1325. The examiner can normally be reached Mon-Fri 8:00-5:00.
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/GUILLERMO J EGOAVIL/Examiner, Art Unit 2847
/TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847
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