DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-9 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
The recitation of “a plurality of selected voltage selection circuits, each memory plane corresponding to the plurality of selected voltage selection circuits” in claim 1, lines 5-6 is not disclosed in the specification or shown in any of the drawings. The specification discloses “the peripheral circuit includes a plurality of selected voltage selection circuits corresponding to the plurality of memory planes”. That means “each memory plane corresponding to respective selected voltage selection circuits of the plurality of selected voltage selection circuits”, not “corresponding to the plurality of selected voltage selection circuits” as recited in claim 1.
Claims 10 and 16 recite the same limitation; therefore, claims 10 and 16 are also rejected for the same reason as set forth in the rejection of claim 1.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-8, 11 and 14-20 of U.S. Patent No. 12,112,802 Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-8, 10-12 and 14-20 are anticipated by claims 1-8, 11 and 14-20 of the patent and claims 9 and 13 would have been obvious over claims 1 and 6 of the patent.
Regarding claim 1, claim 1 of the patent recites a memory device, comprising:
a memory cell array comprising a plurality of memory planes (claim 1, lines 3-4); and
a peripheral circuit coupled to the memory cell array, wherein the peripheral circuit comprises:
a plurality of selected voltage selection circuits, each memory plane corresponding to the plurality of selected voltage selection circuits (claim 1, lines 5-7);
a plurality of global word line voltage selection circuits coupled to the plurality of selected voltage selection circuits, each memory plane corresponding to respective global word line voltage selection circuits of the plurality of global word line voltage selection circuits (claim 1, lines 7-9); and
a plurality of local word line voltage selection circuits coupled to the plurality of global word line voltage selection circuits, each memory plane corresponding to respective local word line voltage selection circuits of the plurality of local word line voltage selection circuits (claim 1, lines 9-11); and
at least one of the plurality of selected voltage selection circuits is configured to apply a program voltage and a read voltage (claim 1, lines 20-25).
Regarding claim 2, claim 1 of the patent recites the memory device according to claim 1, wherein
during a program operation, the plurality of selected voltage selection circuits are configured to output the program voltage; and
during a read operation, a part of the plurality of selected voltage selection circuits are configured to output the read voltage.
Regarding claim 3, claim 2 of the patent recites the memory device according to claim 2, wherein
during the program operation, a number of selected voltages corresponding to the plurality of memory planes is a, and a number of the selected voltage selection circuits corresponding to the plurality of memory planes is at least a;
during the read operation, a number of selected voltages corresponding to each memory plane is b, and a number of the selected voltage selection circuits corresponding to each memory plane is at least b; and
a number of the memory planes is c, and a relationship among a, b, and c is: a≥b*c; wherein both a and b are positive integers greater than 0, and c is a positive integer greater than 1.
Regarding claim 4, claim 3. The memory device according to claim 2, wherein
the peripheral circuit further comprises a plurality of global word lines corresponding to the global word line voltage selection circuits one-to-one;
during the program operation, the number of the selected voltage selection circuits corresponding to the plurality of memory planes is a, and adjacent a global word lines on each memory plane correspond to different selected voltage selection circuits; and
during the read operation, the global word lines on different memory planes correspond to different selected voltage selection circuits, the number of the selected voltage selection circuits corresponding to each memory plane is b, and adjacent b global word lines on each memory plane correspond to different selected voltage selection circuits.
Regarding claim 5, claim 4 of the patent recites the memory device according to claim 2, wherein the peripheral circuit further comprises:
a plurality of unselected voltage selection circuits each corresponding to local word line voltage selection circuits of one memory plane, each memory plane sharing the plurality of unselected voltage selection circuits.
Regarding claim 6, claim 5 of the patent recites the memory device according to claim 5, wherein
during the program operation, a number of unselected voltages corresponding to the plurality of memory planes is d, and a number of the unselected voltage selection circuits corresponding to the plurality of memory planes is at least d;
during the read operation, a number of unselected voltages corresponding to each memory plane is e, and a number of the unselected voltage selection circuits corresponding to each memory plane is at least e; and
a number of the memory planes is c, and a relationship among c, d, and e is: d≧e*c; wherein both d and e are positive integers greater than 0, and c is a positive integer greater than 1.
Regarding claim 7, claim 6 of the patent recites the memory device according to claim 4, wherein
each of the memory planes comprises a plurality of word lines;
the peripheral circuit further comprises a plurality of local word lines corresponding to the local word line voltage selection circuits one-to-one, wherein each of the global word lines corresponds to the plurality of local word lines, and each local word line corresponds to one word line;
the global word line voltage selection circuits output a voltage to the local word line voltage selection circuits through the global word lines; and
the local word line voltage selection circuits output the voltage to corresponding word lines through the local word lines.
Regarding claim 8, claim 7 of the patent recites the memory device according to claim 4, wherein the selected voltage selection circuits, the global word line voltage selection circuits, the local word line voltage selection circuits, and the unselected voltage selection circuits all comprise a multiplexer.
Regarding claim 9, claim 1 of the patent recites the memory device according to claim 1, wherein the number of the plurality of selected voltage selection circuits is ten, the number of global word line voltage selection circuits corresponding to one memory plane is twenty.
It would have been a matter of design choice to use wherein the number of the plurality of selected voltage selection circuits is ten, the number of global word line voltage selection circuits corresponding to one memory plane is twenty since Applicant has not disclosed that the use the specific numbers for the selected voltage selection circuit and for the global voltage selection circuits solves any state problem and it appears that the memory device would perform well with the numbers of claim 1 of the patent. .
Regarding claim 10, claim 8 of the patent recites a memory system, comprising one or more memory devices and a memory controller coupled to and configured to control the one or more memory devices, wherein each of the memory devices comprises a memory cell array and a peripheral circuit coupled to the memory cell array;
the memory cell array comprises a plurality of memory planes;
the peripheral circuit comprises:
a plurality of selected voltage selection circuits, each memory plane corresponding to the plurality of selected voltage selection circuits;
a plurality of global word line voltage selection circuits coupled to the plurality of selected voltage selection circuits, each memory plane corresponding to respective global word line voltage selection circuits of the plurality of global word line voltage selection circuits; and
a plurality of local word line voltage selection circuits coupled to the plurality of global word line voltage selection circuits, each memory plane corresponding to respective local word line voltage selection circuits of the plurality of local word line voltage selection circuits；
wherein at least one of the plurality of selected voltage selection circuits is configured to apply a program voltage and a read voltage.
Regarding claim 11, claim 8 of the patent recites the memory device according to claim 10, wherein
during a program operation, the plurality of selected voltage selection circuits are configured to output the program voltage; and
during a read operation, a part of the plurality of selected voltage selection circuits is configured to output the read voltage.
Regarding claim 12, claim 11 of the patent recites the memory device according to claim 10, wherein the peripheral circuit further comprises:
a plurality of unselected voltage selection circuits each corresponding to local word line voltage selection circuits of one memory plane, each memory plane sharing the plurality of unselected voltage selection circuits.
Regarding claim 13, claim 8 of the patent recites the memory device according to claim 10, wherein the number of the plurality of selected voltage selection circuits is ten, the number of global word line voltage selection circuits corresponding to one memory plane is twenty.
It would have been a matter of design choice to use wherein the number of the plurality of selected voltage selection circuits is ten, the number of global word line voltage selection circuits corresponding to one memory plane is twenty since Applicant has not disclosed that the use the specific numbers for the selected voltage selection circuit and for the global voltage selection circuits solves any state problem and it appears that the memory device would perform well with the numbers of claim 8 of the patent. .
Regarding claim 14, claim 14 of the patent recites the memory system according to claim 12, wherein the selected voltage selection circuits, the global word line voltage selection circuits, the local word line voltage selection circuits, and the unselected voltage selection circuits all comprise a multiplexer.
Regarding claim 15, claim 15 of the patent recites the memory system according to claim 10, wherein the memory system comprises a memory card or a solid-state hard disk.
Regarding claim 16, claim 16 of the patent recites a method for operating a memory device, wherein the memory device comprises a memory cell array and a peripheral circuit coupled to the memory cell array;
the memory cell array comprises a plurality of memory planes;
the peripheral circuit comprises a plurality of selected voltage selection circuits, each memory plane corresponding to the plurality of selected voltage selection circuits; wherein the method comprises:
during a program operation, the plurality of selected voltage selection circuits output a program voltage; and
during a read operation, at least part of the plurality of selected voltage selection circuits output a read voltage.
Regarding claim 17, claim 17 of the patent recites the method according to claim 16, wherein
during the program operation performed on the plurality of memory planes simultaneously, a number of selected voltages corresponding to the plurality of memory planes is a, and a number of the selected voltage selection circuits corresponding to the plurality of memory planes is at least a;
during the read operation performed on the plurality of memory planes, a number of selected voltages corresponding to each memory plane is b, and a number of the selected voltage selection circuits corresponding to each memory plane is at least b; and
a number of the memory planes is c, and a relationship among a, b, and c is: a≥b*c, wherein both a and b are positive integers greater than 0, and c is a positive integer greater than 1.
Regarding claim 18, claim 18 of the patent recites the method according to claim 17, wherein
the peripheral circuit further comprises a plurality of global word lines corresponding to a plurality global word line voltage selection circuits one-to-one;
during the program operation performed on the plurality of memory planes simultaneously, the number of the selected voltage selection circuits corresponding to the plurality of memory planes is a, and adjacent a global word lines on each memory plane correspond to different selected voltage selection circuits; and
during the read operation performed on the plurality of memory planes, the global word lines on different memory planes correspond to different selected voltage selection circuits, the number of the selected voltage selection circuits corresponding to each memory plane is b, and adjacent b global word lines on each memory plane correspond to different selected voltage selection circuits.
Regarding claim 19, claim 19 of the patent recites the method according to claim 16, wherein
the peripheral circuit further comprises a plurality of unselected voltage selection circuits corresponding to the plurality of memory planes;
the method further comprises:
applying a plurality of different voltages output by the plurality of unselected voltage selection circuits to each memory plane during the program operation; and
applying a part of the plurality of different voltages output by the plurality of unselected voltage selection circuits respectively to different memory planes during the read operation.
Regarding claim 20, claim 20 of the patent recites the method according to claim 19, wherein
during the program operation, a number of unselected voltages corresponding to the plurality of memory planes is d, and a number of the unselected voltage selection circuits corresponding to the plurality of memory planes is at least d;
during the read operation, a number of unselected voltages corresponding to each memory plane is e, and a number of the unselected voltage selection circuits corresponding to each memory plane is at least e; and
a number of the memory planes is c, and a relationship among c, d and, e is: d≧e*c, wherein both d and e are positive integers greater than 0, and c is a positive integer greater than 1.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 10, 12 and16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang (CN 110289035 A).
Regarding claims 1, 10 and 16, Wang discloses a memory device, a memory system and a method, comprising:
a memory cell array comprising a plurality of memory planes (claim 1, lines 3-4); and
a peripheral circuit coupled to the memory cell array (Abstract), wherein the peripheral circuit comprises:
a plurality of selected voltage selection circuits (said peripheral circuit, comprising: N selected voltage selection module, a plurality of global word lines, a plurality of global word line voltage selecting module and a plurality of local word line voltage selecting module); each memory plane corresponding to the plurality of selected voltage selection circuits;
a plurality of global word line voltage selection circuits coupled to the plurality of selected voltage selection circuits, each memory plane corresponding to respective global word line voltage selection circuits of the plurality of global word line voltage selection circuits; and
a plurality of local word line voltage selection circuits coupled to the plurality of global word line voltage selection circuits, each memory plane corresponding to respective local word line voltage selection circuits of the plurality of local word line voltage selection circuits (each memorizing unit plane on the ith local word line and the j-th corresponding to said selected voltage selection module, each said global word line corresponds to at least one of the local word lines on each memorizing unit plane, and corresponding to the global word line voltage selecting module, each local word line corresponding to one of the global word line, the local word line voltage selecting module and the local wordline, j=i-ak, a is a positive integer, 1≤i ≤ M, 1≤j ≤ N, N is greater than or equal to k;); and
at least one of the plurality of selected voltage selection circuits is configured to apply a program voltage and a read voltage (the voltage selection module can output the selection of selected voltage to the global word line voltage selecting module; global word line voltage selecting module and voltage from the selected and non-selected voltage, selecting a voltage through the corresponding global word line output local word line voltage selecting module on the plane corresponding to each storage unit, output from the global word line voltage selecting module by the local word line voltage selecting module of the selected voltage and the unselected voltage a voltage output to the corresponding LWL, so that the desired voltage of selected and unselected voltage is applied to each LWL to realize the selected storage unit tube to erase, program or read operation.).
.
Regarding claim 12, Wang discloses the memory device according to claim 10, wherein the peripheral circuit further comprises:
a plurality of unselected voltage selection circuits each corresponding to local word line voltage selection circuits of one memory plane, each memory plane sharing the plurality of unselected voltage selection circuits (Optionally, the non-selected voltage is more than one, then the peripheral circuit, further comprising: a plurality of non-selected voltage selecting module; each of said at least one local word line unselected voltage selection module corresponding to a storage unit on the plane, each local word line corresponding to one of the non-selected voltage selection module).
Regarding claim 14, Wang discloses the memory system according to claim 12, wherein the selected voltage selection circuits, the global word line voltage selection circuits, the local word line voltage selection circuits, and the unselected voltage selection circuits all comprise a multiplexer (in the current peripheral circuit structure, typically by the multi-path selector (multiplexer MUX) applies different voltages (including all selected voltage and the unselected voltage) selected to GWL and In a specific implementation, the global word line voltage selecting module 220, and a local word line voltage selecting module 230 can be a multiplexer (MUX))
.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Wang.
The only difference between claims 9 and 13 and Wang is that the number of the plurality of selected voltage selection circuits is ten, the number of global word line voltage selection circuits corresponding to one memory plane is twenty.
It would have been a matter of design choice to use wherein the number of the plurality of selected voltage selection circuits is ten, the number of global word line voltage selection circuits corresponding to one memory plane is twenty since Applicant has not disclosed that the use the specific numbers for the selected voltage selection circuit and for the global voltage selection circuits solves any state problem and it appears that the memory device would perform well with the numbers of Wang.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUAN HOANG whose telephone number is (571)272-1779. The examiner can normally be reached 7:30AM-4:00PM M-F.
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/HUAN HOANG/Primary Examiner, Art Unit 2827
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