DETAILED ACTION
Response to Amendment
1. Applicant's amendment filed on 06/15/26 has been received and entered in the case. The amendments to the claims do not distinguish patentably over the previously applied prior art, i.e., AAPA figure 1 in view of either Kerr or Kerr et al, and therefore the obviousness rejection under 35 USC 103 based on such prior art is maintained and repeated, as set forth below.
Information Disclosure Statements
2. The information disclosure statements (IDS) submitted on 01/22/26 and 04/08/26 have been considered by the examiner.
Drawings
3. The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the plurality of bypass switches configured to bypass both the rail resistors and the rung resistors, as recited in claims 8 and 17, must be shown or the feature canceled from the claims, note that none of figures 2 through 10 of the instant drawings shows any bypass resistors bypassing the rung resistors. Applicant's argument that in instant figure 2, switches 220 bypass both of the rail and rung resistors is not persuasive because when these switches are closed, the input signal IN still passes through all of the rail resistors rung resistors before it is received at the gate terminals of the stacked semiconductor switching elements. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
4. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 8 and 17 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claims 8 and 17 are indefinite because they are misdescriptive of applicant's invention, i.e., in applicant's invention plurality of bypass switches are not configured to bypass both the rail resistors and the rung resistors, i.e., none of figures 2 through 10 of the instant drawings shows any bypass resistors bypassing the rung resistors. As noted above, switches 220 do not bypass both of the rail or rung resistors because when these switches are closed, the input signal IN still passes through all of the rail and rung resistors before it is received at the gate terminals of the stacked semiconductor switching elements.
Claim Rejections - 35 USC § 103
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 2, 4, 7-14 and 16-21 are rejected under 35 U.S.C. 103 as being unpatentable over applicant's admitted prior art (AAPA) figure 1 in view of Kerr (USP 10,454,529) or Kerr et al (USP 10,608,623).
As to claims 2, 7 and 12, AAPA figure 1 shows
a semiconductor system comprising:
a plurality of semiconductor switching elements (FET1 through FETn+1) arranged in a stacked configuration;
a control network (the unillustrated circuitry which provides signal IN to circuit 130) coupled to gates of the semiconductor switching elements for providing gate control signals;
a resistor network comprising a plurality of ladder resistors (the four rail resistors shown in AAPA figure 1 or, alternatively, the combination of these four rail resistors together with the four rung resistors 160), and a plurality of common resistors (the two resistors within circuit 130 or, alternatively, the two resistors within circuit 130 together with the resistor coupled directly to the output of circuit 130) connected to the control network; and
a plurality of bypass switches, each bypass switch corresponding to a subset of the resistor network (although not shown in AAPA figure 1, the inclusion of a plurality of bypass switches for bypassing the ladder resistors in AAPA figure 1 would have been obvious to one of ordinary skill in the art in view of what is shown in figures 2A and 2B of Kerr, note bypass switches SRG1 through SRG3 which are coupled across ladder resistors RG2 through RG4, or would have been obvious in view of what is shown in figure 14 of Kerr et al, note bypass switches SA1 through SA3 which are coupled across ladder resistors RG--as noted in parent case 17/492,180, it would have been obvious to one of ordinary skill in the art to provide bypass switches across the ladder resistors in AAPA figure 1 in order to provide the speed up switching advantages taught by Kerr and Kerr et al, see column 6, line 48 through column 7, line 41 of the former and column 10, lines 32-46 of the latter);
wherein:
the semiconductor switch system is configured to operate in at least an ON state, an OFF state, and a transition state (inherently or obviously the AAPA figure 1 semiconductor switch system is configured to operate in at least an ON state, an OFF state, and a transition state) and
the plurality of bypass switches are selectively activating based on the operational state of the semiconductor switching system to bypass at least part of the resistor network during the transition state (inherently or obviously during operation of the AAPA figure 1 semiconductor switch system, the above-noted obvious bypass switches are selectively activated based on the operational state of the plurality of semiconductor switching elements to bypass at least part of the resistor network during the transition state);
and wherein the plurality of bypass switches comprise:
a first set of bypass switches connected across corresponding common resistors (note the bypass switches within circuit 130 which are connected across corresponding common resistors within circuit 130), and
a second set of bypass switches connected across corresponding ladder resistors (as noted above, it would have been obvious to one of ordinary skill in the art to connect a second set of bypass switches across the ladder resistors shown in AAPA figure 1).
As to claim 4, in AAPA figure 1 as modified by either Kerr or Kerr et al so as to include the above-noted obvious bypass switches, the first and second sets of bypass switches will be configured to be either inherently or obviously activated simultaneously during at least a portion of the transition state.
As to claim 8, in AAPA figure 1 as modified by either Kerr or Kerr et al so as to include the above-noted obvious bypass switches, the bypass switches will inherently be configured to bypass both the rail resistors and the rung resistors during at least a portion of the transition state (alternatively, such bypassing of the rung resistors would have been obvious to one of ordinary skill in the art because it was old and well-known in the art before the effective filing date of applicant's invention to connect a plurality of bypass switches across a corresponding plurality of gate resistors, two examples of this well-known concept being disclosed by Kim et al and Shanjani et al, cited on the attached PTO-892 form, note figure 3 of the former and figure 4 of the latter, motivation for providing bypass switches across the rung resistors in AAPA figure 1 being to achieve the advantages taught by Kim et al and Shanjani et al, i.e., improved isolation characteristics and/or improved switching time.
As to claim 9, in AAPA figure 1 as modified by either Kerr or Kerr et al so as to include the above-noted obvious bypass switches, the bypass switches will be configured to either inherently or obviously bypass only the rail resistors during at least a portion of the transition state.
As to claim 10, in AAPA figure 1 as modified by either Kerr or Kerr et al so as to include the above-noted obvious bypass switches, the bypass switches will inherently or obviously comprise multiple bypass feeds, each bypass feed configured to inherently or obviously bypass a separate subset of the resistor network.
As to claim 11, in AAPA figure 1 as modified by either Kerr or Kerr et al so as to include the above-noted obvious bypass switches, the bypass switches will be configured to inherently or obviously not bypass the resistor network during at least a portion of the ON state and the OFF state.
As to claim 13, note that the semiconductor switch system shown in AAPA figure 1 can obviously be implemented in a radio frequency (RF) switch, i.e., obvious in view of the RFIN and RFOUT signals.
As to claims 14 and 16-21, the limitations of these method claims would have been obvious from AAPA figure 1 in view of either Kerr or Kerr et al, using the same analysis as set forth above with regard to claims 1, 4 and 7-13.
Double Patenting
6. Claims 2, 4, 7-14 and 16-21 are rejected on the ground of non-statutory double patenting as being unpatentable over the claims of U.S. Patent No. 11,632,107. Although the claims at issue are not identical, they are not patentably distinct from each other because the limitations of claims 2-21 of the instant application are either anticipated by or would have been obvious from the limitations of the claims of USP 11,632,107. Note, for example, that the limitations recited on the first three lines of independent claim 2 of the instant application are fully anticipated by what is recited on lines 1-2 of independent claim 1 of the '107 patent; the control network limitation recited on lines 4-5 of independent claim 2 of the instant application would have been obvious in view of lines 15-16 of independent claim 1 of the '107 patent (obviously a control network will provide the gate control voltage); the resistor network limitation recited on lines 6-7 of independent claim 2 of the instant application are anticipated by what is recited on lines 12-15 of independent claim 1 of the '107 patent; the plurality of bypass switches recited on lines 8-9 of independent claim 2 of the instant application are anticipated by what is recited on lines 17-21 of independent claim 1 of the '107 patent; the limitation recited on lines 11-12 of independent claim 2 of the instant application is anticipated by what is recited on lines 4-8 of independent claim 1 of the '107 patent; the limitation recited on the last three lines of independent claim 2 of the instant application is anticipated by, or would have been obvious from, what is recited in claim 2 of the '107 patent, i.e., either inherently or obviously the bypass switches in claim 2 of the '107 patent will be selectively activated based on the operational state of the semiconductor switching elements in order to bypass at least part of the resistor network during the transition state; and the new limitations added on the last five lines of claim 2 are anticipated by what is recited in claim 2 of the ‘107 patent.
Applicant should also note that the limitations of claims 4, 7-14 and 16-21 of the instant application are similarly either anticipated by or obvious in view of what is recited in the claims of the '107 patent.
The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A non-statutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on non-statutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a non-statutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Allowable Subject Matter
7. Claims 5 and 6 would be allowable upon the filing of the above-noted terminal disclaimer if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: none of the prior art of record, including AAPA figure 1, Kerr and Kerr et al, supra, discloses or suggests the semiconductor switch system of claim 3 with the further limitation that each bypass switch in the first and second sets comprises a transistor pair including an NMOS transistor in series with a PMOS transistor, as recited in claim 5, and claim 6 is allowable in view of its dependency on allowable claim 5.
Response to Arguments
8. Applicant's arguments filed on 06/15/26 have been fully considered but they are not persuasive.
Applicant's first argument is that "Kerr 1 stands in sharp contrast as Kerr 1 never bypasses its common gate resistors. In particular, FIGs. 1A-D in Kerr 1 do not show any bypass switches. The common gate resistor RG1 of FIGs. 2A and 2B in Kerr 1 is not bypassed. Each of FIGs. 3A, 3B, 3E, 5, 6, 8-10 is just showing a portion of the resistor ladder and thus shows no common gate resistor. Since Kerr 1 has no teaching or suggestion for the common gate resistor bypass of claim 1, claim 1 and its remaining dependent claims 4 and 7-13 are allowable over Kerr 1."
Applicant's first argument is not persuasive because Kerr 1 is not being relied upon by the examiner for the limitation that the common gate resistors are bypassed, i.e., this limitation is shown in AAPA figure 1. Applicant should note that one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Applicant's second argument is that "Kerr 2 also stands in sharp contrast as Kerr 2 never bypasses its common gate resistors. For example, Kerr 2 shows no bypass switches in FIGs. 1-3. In FIG. 4, Kerr 2 discloses a single common gate resistor (RGC1) that couples to a gate control node 24. This sole common gate resistor is not bypassed. Instead, Kerr 2 only bypasses the ladder resistors RG using transistors 40. This same failure to teach or suggest any bypassing of the common gate resistor RGC1 also occurs in Kerr 2's remaining FIGs. 5-12A and 15A. Kerr 2 does not show a common gate resistor in FIGs. 12B, 13A, 13B, 14A, 14B and 15B. Since Kerr 2 has no teaching or suggestion for the common gate resistor bypass of claim 1, claim 1 and its remaining dependent claims 4 and 7-13 are allowable over Kerr 2. Accordingly, claim 1 and its dependent claims 4 and 7-13 are allowable over the combination of Kerr 1 and Kerr 2."
Applicant's second argument is not persuasive for the same reason noted above, i.e., Kerr 2 is not being relied upon by the examiner for the limitation that the common gate resistors are bypassed, i.e., this limitation is shown in AAPA figure 1. As noted above, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Action is Final
9. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Conclusion
10. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENNETH B WELLS whose telephone number is (571)272-1757. The examiner can normally be reached Monday-Friday, 8:30am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, REGIS J BETSCH, can be reached at (571)270-7101. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KENNETH B WELLS/Primary Examiner, Art Unit 2836 June 24, 2026
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