DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
2. The information disclosure statement (IDS) submitted on 09/17/24 has been considered by the examiner.
Specification
3. The disclosure is objected to because of the following informalities: in paragraph [0001] of the instant specification, reference to parent case 18/183,806 should be updated so as to reflect the fact that this application has now issued as U.S. Patent No. 12,119,814.
Appropriate correction is required.
Claim Objections
4. Claims 8-11 are objected to because of the following informalities:
On line 2 of claim 8, the word "is" should be changed to --are-- for purposes of proper grammatical form (applicant should note line 13 of instant claim 2 which correctly recites that the plurality of bypass switches "are" selectively activated, not “is” selectively activated).
On line 2 of claim 9, the word "is" should again be changed to --are--.
On line 2 of claim 10, the word "comprises" should be changed to --comprise--.
On line 2 of claim 11, the word "is" should again be changed to --are--.
Appropriate correction is required.
Drawings
5. The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the plurality of bypass switches configured to bypass both the rail resistors and the rung resistors, as recited in claims 8 and 17, must be shown or the feature canceled from the claims, note that none of figures 2 through 10 of the instant drawings shows any bypass resistors bypassing the rung resistors. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
6. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 8 and 17 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claims 8 and 17 are indefinite because they are misdescriptive of applicant's invention, i.e., in applicant's invention plurality of bypass switches are not configured to bypass both the rail resistors and the rung resistors, i.e., none of figures 2 through 10 of the instant drawings shows any bypass resistors bypassing the rung resistors
Claim Rejections - 35 USC § 103
7. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 2-4 and 7-21 are rejected under 35 U.S.C. 103 as being unpatentable over applicant's admitted prior art (AAPA) figure 1 in view of Kerr (USP 10,454,529) or Kerr et al (USP 10,608,623).
As to claims 2, 7 and 12, AAPA figure 1 shows
a semiconductor system comprising:
a plurality of semiconductor switching elements (FET1 through FETn+1) arranged in a stacked configuration;
a control network (the unillustrated circuitry which provides signal IN to circuit 130) coupled to gates of the semiconductor switching elements for providing gate control signals;
a resistor network comprising a plurality of ladder resistors (the four rail resistors shown in AAPA figure 1 or, alternatively, the combination of these four rail resistors together with the four rung resistors 160), and a plurality of common resistors (the two resistors within circuit 130 or, alternatively, the two resistors within circuit 130 together with the resistor coupled directly to the output of circuit 130) connected to the control network; and
a plurality of bypass switches (although not shown in AAPA figure 1, the inclusion of a plurality of bypass switches would have been obvious to one of ordinary skill in the art in view of what is shown in figures 2A and 2B of Kerr, note bypass switches SRG1 through SRG3 which are coupled across ladder resistors RG2 through RG4, or would have been obvious in view of what is shown in figure 14 of Kerr et al, note bypass switches SA1 through SA3 which are coupled across ladder resistors RG--as noted in parent case 17/492,180, it would have been obvious to one of ordinary skill in the art to provide bypass switches across the ladder resistors in AAPA figure 1 in order to provide the speed up switching advantages taught by Kerr and Kerr et al, see column 6, line 48 through column 7, line 41 of the former and column 10, lines 32-46 of the latter);
wherein:
the semiconductor switch system is configured to operate in at least an ON state, an OFF state, and a transition state (inherently or obviously the AAPA figure 1 semiconductor switch system is configured to operate in at least an ON state, an OFF state, and a transition state) and
the plurality of bypass switches are selectively activating based on the operational state of the plurality of semiconductor switching elements to bypass at least part of the resistor network during the transition state (inherently or obviously during operation of the AAPA figure 1 semiconductor switch system, the above-noted obvious bypass switches are selectively activated based on the operational state of the plurality of semiconductor switching elements to bypass at least part of the resistor network during the transition state).
As to claim 3, the claimed first set of bypass switches can be read on any single one of the above-noted obvious bypass switches, i.e., a set can be broadly interpreted as a single element (or, alternatively, any pair of the above-noted obvious bypass switches), and the claimed second set of bypass switches can be read on any additional single one of the above-noted obvious bypass switches (or, alternatively, any additional pair of the above-noted obvious bypass switches).
As to claim 4, in AAPA figure 1 as modified by either Kerr or Kerr et al so as to include the above-noted obvious bypass switches, the first and second sets of bypass switches will be configured to be either inherently or obviously activated simultaneously during at least a portion of the transition state.
As to claim 8, in AAPA figure 1 as modified by either Kerr or Kerr et al so as to include the above-noted obvious bypass switches, the bypass switches will inherently be configured to bypass both the rail resistors and the rung resistors during at least a portion of the transition state (alternatively, such bypassing of the rung resistors would have been obvious to one of ordinary skill in the art because it was old and well-known in the art before the effective filing date of applicant's invention to connect a plurality of bypass switches across a corresponding plurality of gate resistors, two examples of this well-known concept being disclosed by Kim et al and Shanjani et al, cited on the attached PTO-892 form, note figure 3 of the former and figure 4 of the latter, motivation for providing bypass switches across the rung resistors in AAPA figure 1 being to achieve the advantages taught by Kim et al and Shanjani et al, i.e., improved isolation characteristics and/or improved switching time.
As to claim 9, in AAPA figure 1 as modified by either Kerr or Kerr et al so as to include the above-noted obvious bypass switches, the bypass switches will be configured to either inherently or obviously bypass only the rail resistors during at least a portion of the transition state.
As to claim 10, in AAPA figure 1 as modified by either Kerr or Kerr et al so as to include the above-noted obvious bypass switches, the bypass switches will inherently or obviously comprise multiple bypass feeds, each bypass feed configured to inherently or obviously bypass a separate subset of the resistor network.
As to claim 11, in AAPA figure 1 as modified by either Kerr or Kerr et al so as to include the above-noted obvious bypass switches, the bypass switches will be configured to inherently or obviously not bypass the resistor network during at least a portion of the ON state and the OFF state.
As to claim 13, note that the semiconductor switch system shown in AAPA figure 1 can obviously be implemented in a radio frequency (RF) switch, i.e., obvious in view of the RFIN and RFOUT signals.
As to claims 14-21, the limitations of these method claims would have been obvious from AAPA figure 1 in view of either Kerr or Kerr et al, using the same analysis as set forth above with regard to claims 1-4 and 7-13.
Double Patenting
8. Claims 2-21 are rejected on the ground of non-statutory double patenting as being unpatentable over the claims of U.S. Patent No. 11,632,107. Although the claims at issue are not identical, they are not patentably distinct from each other because the limitations of claims 2-21 of the instant application are either anticipated by or would have been obvious from the limitations of the claims of USP 11,632,107. Note, for example, that the limitations recited on the first three lines of independent claim 2 of the instant application are fully anticipated by what is recited on lines 1-2 of independent claim 1 of the '107 patent; the control network limitation recited on lines 4-5 of independent claim 2 of the instant application would have been obvious in view of lines 15-16 of independent claim 1 of the '107 patent (obviously a control network will provide the gate control voltage); the resistor network limitation recited on lines 6-7 of independent claim 2 of the instant application are anticipated by what is recited on lines 12-15 of independent claim 1 of the '107 patent; the plurality of bypass switches recited on lines 8-9 of independent claim 2 of the instant application are anticipated by what is recited on lines 17-21 of independent claim 1 of the '107 patent; the limitation recited on lines 11-12 of independent claim 2 of the instant application is anticipated by what is recited on lines 4-8 of independent claim 1 of the '107 patent; and the limitation recited on the last three lines of independent claim 2 of the instant application is anticipated by, or would have been obvious from, what is recited in claim 2 of the '107 patent, i.e., either inherently or obviously the bypass switches in claim 2 of the '107 patent will be selectively activated based on the operational state of the semiconductor switching elements in order to bypass at least part of the resistor network during the transition state. Applicant should also note that the limitations of claims 3-21 of the instant application are similarly either anticipated by or obvious from the claims of the '107 patent.
The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A non-statutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on non-statutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a non-statutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Allowable Subject Matter
9. Claims 5 and 6 are objected to as being dependent upon a rejected base claim, but would be allowable upon the filing of the above-noted terminal disclaimer if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: none of the prior art of record, including AAPA figure 1, Kerr and Kerr et al, supra, discloses or suggests the semiconductor switch system of claim 3 with the further limitation that each bypass switch in the first and second sets comprises a transistor pair including an NMOS transistor in series with a PMOS transistor, as recited in claim 5. Claim 6 is allowable in view of its dependency on allowable claim 5.
Prior Art Not Relied Upon
10. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Figure 3 of Scott et al (USP 10,897,246), cited by applicant, discloses another example of a semiconductor switch system comprising a plurality of semiconductor switching elements (24A through 24N) arranged in a stacked configuration together with a control network and a resistor network comprising a plurality of ladder resistors. Not disclosed by figure 3 of Scott et al are the claimed plurality of bypass switches, each corresponding to a subset of the resistor network, however such bypass switches would have been obvious to one of ordinary skill in the art for the same reason noted above in the rejection based on AAPA figure 1 in view of either Kerr or Kerr et al, i.e., obvious to add such bypass switches in figure 3 of Scott et al in order to provide the speed up switching advantages taught by Kerr and Kerr et al, see column 6, line 48 through column 7, line 41 of the former and column 10, lines 32-46 of the latter);
Conclusion
11. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENNETH B WELLS whose telephone number is (571)272-1757. The examiner can normally be reached Monday-Friday, 8:30am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, LINCOLN DONOVAN can be reached at (571)272-1988. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KENNETH B WELLS/Primary Examiner, Art Unit 2842 January 9, 2026