Prosecution Insights
Last updated: October 04, 2026
Application No. 18/827,292

MANUFACTURING SEMICONDUCTOR DEVICE USING SELECTIVE DIELECTRIC ON DIELECTRIC (DOD) DEPOSITION PROCESS

Non-Final OA §102§103
Filed
Sep 06, 2024
Examiner
LEE, DA WEI
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Merck Patent GmbH
OA Round
1 (Non-Final)
80%
Grant Probability
Favorable
1-2
OA Rounds
1y 5m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 80% — above average
80%
Career Allowance Rate
37 granted / 46 resolved
+12.4% vs TC avg
Strong +15% interview lift
Without
With
+15.4%
Interview Lift
resolved cases with interview
Typical timeline
3y 6m
Avg Prosecution
22 currently pending
Career history
82
Total Applications
across all art units

Statute-Specific Performance

§103
59.9%
+19.9% vs TC avg
§102
31.6%
-8.4% vs TC avg
§112
7.8%
-32.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 46 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1 – 5, 7 – 11, 14 – 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Illiberi ( Pub. No. US 20210301392 A1 ), hereinafter Illiberi. PNG media_image1.png 650 1233 media_image1.png Greyscale Regarding Independent claim 1, Illiberi teaches a method of manufacturing a semiconductor device, the method comprising: providing a structure comprising a first insulating pattern ( Illiberi, FIG. 2A, dielectric surface 220; [0043], [0226] – [0227] ) and a metal pattern ( Illiberi, FIG. 2A, metal surface 210; [0043] and [0226] – [0227] ) disposed on a substrate; performing a cleaning process on the structure ( Illiberi, [0064], the substrate may be pretreated or cleaned prior to or at the beginning of the deposition process … the substrate may be subjected to a plasma cleaning process prior to or at the beginning of the deposition process ); exposing the structure to a reducing agent ( Illiberi, [0029], A polymer passivation layer may be selectively formed on the metal surface relative to the dielectric surface. In some embodiments the passivation agent on the dielectric surface inhibits or prevents formation of the polymer passivation layer on the dielectric surface; [0030], A plasma treatment may be used to activate the dielectric surface. For example, the silylated dielectric surface may be exposed to a H2 plasma; [0041], The passivation layer on the dielectric surface may facilitate selectivity for the subsequent passivation of the metal surface by a polymer. In addition, the passivation layer on the dielectric can serve to functionalize the surface such that the catalyst is able to chemisorb on the dielectric surface … passivation layer on the dielectric surface can be activated, such as by exposure to a plasma reactant, for example H2 plasma ); forming, selectively, a passivation layer on the metal pattern ( Illiberi, FIG. 2C, 240; [0036], metal surface is passivated 120 by exposure to one or more second passivation agents, leading to selective formation of a polymer layer on the metal surface; [0087], metal surface 210 that has been passivated with a polymer layer 240; [0226], selective polymer passivation 240 of the metal surface 210 relative to the dielectric surface 220 ); forming, selectively, a second insulating pattern on the first insulating pattern ( Illiberi, FIG. 2E, 260; [0088], silicon oxide film 260 typically comprises multiple molecular layers; [0266], elective deposition of silicon oxide 260 on the dielectric surface 220 relative to the polymer passivated metal surface; [0231], silicon oxide 260 is formed by exposing the substrate to a silanol reactant, such as tris(tert-pentoxy)silanol. The silanol reactant may decompose on the aluminum atoms on the catalyzed dielectric surface, leading to the deposition of silicon oxide 260 on the dielectric surface 220 ); and performing thermal processing on the structure ( Illiberi, [0234], Additional treatments, such as heat or chemical treatment, can be conducted prior to, after or between the foregoing processes. For example, treatments may modify the surfaces or remove portions of the metal, silicon oxide, passivation and metal oxide surfaces exposed at various stages of the process ). Regarding claim 2, Illiberi teaches the method as claimed in claim 1, Illiberi further teaches: wherein the performing of the cleaning process comprises: exposing the structure to a cleaning liquid including an organic acid having a carboxyl group ( Illiberi, [0079], carboxylic acid; [0212], In some embodiments the cleaning step may comprise etching ); and washing the structure with distilled water ( Illiberi, [0064] In some embodiments, the substrate may be pretreated or cleaned prior to or at the beginning of the deposition process or prior to or after one or more of the steps in the selective deposition processes ). Regarding claim 3, Illiberi teaches the method as claimed in claim 2, Illiberi further teaches: wherein the organic acid having a carboxyl group ( Illiberi, [0079], carboxylic acid ) includes at least one of acetic acid, citric acid, formic acid, methanoic acid, ethanoic acid, propanoic acid, butanoic acid ( Illiberi, [0079], butanedioic acid ), pentanoic acid ( Illiberi, [0079], pentanedioic acid ), hexanoic acid, heptanoic acid, octanoic acid, nonanoic acid, decanoic acid, ethanedioic acid, propanedioic acid ( Illiberi, [0079], propanedioic acid ), butanedioic acid, pentanedioic acid ( Illiberi, [0079], propanedioic acid ), hexanedioc acid, heptanedioic acid, octanedioic acid, nonanedioic acid, decanedioic acid, 2-hydroxypropane-1,2,3-tricarboxylic acid, 1-hydroxypropane-1,2,3-tricarboxylic acid, prop-1-ene-1,2,3-tricarboxylic acid, propane-1,2,3-tricarboxylic acid, 2-hydroxynonadecane-1,2,3-tricarboxylic acid, or benzene-1,3,5-tricarboxylic acid. Regarding claim 4, Illiberi teaches the method as claimed in claim 1, Illiberi further teaches: wherein the reducing agent includes hydrogen-based plasma ( Illiberi, [0030], A plasma treatment may be used to activate the dielectric surface. For example, the silylated dielectric surface may be exposed to a H2 plasma; [0041], passivation layer on the dielectric surface can be activated, such as by exposure to a plasma reactant, for example H2 plasma ). Regarding claim 5, Illiberi teaches the method as claimed in claim 4, Illiberi further teaches: wherein the exposing of the structure to the reducing agent comprises supplying H2 ( Illiberi, [0030], A plasma treatment may be used to activate the dielectric surface. For example, the silylated dielectric surface may be exposed to a H2 plasma; [0041], The passivation layer on the dielectric surface may facilitate selectivity for the subsequent passivation of the metal surface by a polymer. In addition, the passivation layer on the dielectric can serve to functionalize the surface such that the catalyst is able to chemisorb on the dielectric surface … passivation layer on the dielectric surface can be activated, such as by exposure to a plasma reactant, for example H2 plasma ) and an inert gas ( Illiberi, [0056], the reaction chamber may be evacuated and/or purged with an inert gas ) to the structure in a temperature range of about 250 °C to about 350 °C ( Illiberi, [0212], In some embodiments the cleaning step may comprise H2 plasma treatment. In some embodiments the cleaning step is carried out at a temperature of about room temperature to about 400° C ) and in a direct plasma or remote plasma state. Regarding claim 7, Illiberi teaches the method as claimed in claim 1, Illiberi further teaches: wherein the forming the passivation layer ( Illiberi, FIG. 2C, selective polymer passivation 240 ) on the metal pattern ( Illiberi, FIG. 2C, metal surface 210 ) includes exposing the structure to a passivation gas, and the passivation gas includes at least one of methanethiol, ethanethiol, propanethiol, butanethiol, pentanethiol, hexanethiol, heptanethiol, octanethiol, nonanethiol, decanethiol, undecanethiol, dodecanethiol ( Illiberi, [0036], a self-assembled monolayer (SAM) is selectively formed on the metal layer, for example from a vapor-phase dodecanethiol precursor; [0081], SAM passivation layer may be selectively formed on the metal surface by contacting the substrate with a sulfur-containing monomer, such as 1-dodecanethiol (CH3(CH2)11SH), which can be referred to as a thiol SAM precursor or monomer ), tridecanethiol, tetradecanethiol, pentadecanethiol, hexadecanethiol, heptadecanethiol, octadecanethiol, nonadecanethiol, tetrahydro-2H-pyran-4-thiol, 2-propene-1-thiol, tetrahydro-2H-pyran-4-thiol, thiophenol, 4-methyl-1-thiophenol, 3-methyl-1-thiophenol, 2-methyl-1-thiophenol, para-xylene-alpha-thiol, 1H,1H,2H,2H-perfluorodecanethiol, 2,2,2-trifluoroethanethiol, 4-methyl-6-trifluoromethyl-pyrimidine-2-thiol, 4-trifluoromethylbenzyl mercaptan, 4-(trifluoromethoxy)benzyl mercaptan, 4-fluorobenzyl mercaptan, 3,5-bis(trifluoromethyl)benzenethiol, 2-(trifluoromethyl)benzenethiol, 4-trifluoromethyl-2,3,5,6-tetrafluorothiophenol, 3,5-difluorobenzyl mercaptan, 4-trifluoromethyl-2,3,5,6-tetrafluorothiophenol, para-trifluoromethylbenzenethiol, di-tert-butyl disulfide, or di-heptane disulfide. Regarding claim 8, Illiberi teaches the method as claimed in claim 1, Illiberi further teaches: wherein the passivation layer ( Illiberi, FIG. 2C, selective polymer passivation 240 ) includes a self-assembled monolayer ( SAM ) ( Illiberi, [0009], polymer passivation layer comprises a self-assembled monolayer (SAM). In some embodiments, a SAM is formed by exposing the substrate to a thiol polymer. In some embodiments, the polymer passivation layer comprises a polyimide layer; [0036], a self-assembled monolayer (SAM) is selectively formed on the metal layer, for example from a vapor-phase dodecanethiol precursor ). Regarding claim 9, Illiberi teaches the method as claimed in claim 1, Illiberi further teaches: wherein the forming of the second insulating pattern ( Illiberi, FIG. 2E, 260; [0088], silicon oxide film 260 ) on the first insulating pattern ( Illiberi, FIG. 2E, dielectric surface 220 ) includes: supplying a catalyst to the structure, wherein a first portion of the catalyst ( Illiberi, FIG. 2D, 250; [0087] As shown in FIG. 2D, in some embodiments an aluminum catalyst 250 is selectively deposited on the dielectric surface 220 relative to a metal surface 210; [0230], The aluminum catalyst 250 may be formed selectively on the dielectric surface 220 by exposing the substrate to an aluminum reactant such as trimethyl aluminum (TMA), dimethylaluminumchloride, aluminum trichloride (AlCl3), dimethylaluminum isopropoxide (DMAI), tris(tertbutyl)aluminum (TTBA), tris(isopropoxide)aluminum (TIPA) or triethyl aluminum (TEA) ) is adsorbed by the first insulating pattern ( Illiberi, FIG. 2D, dielectric surface 220 ); performing a first purge ( Illiberi,[0098], [0211], Trimethyl aluminum (TMA) is pulsed into the reaction chamber for 150 ms, followed by a 3 s purge ) operation removing a second portion of the catalyst other than the first portion of the catalyst ( Illiberi,[0098], In between pulses, excess catalyst may be removed from the reaction space. For example, the reaction chamber may be evacuated and/or purged with an inert gas. The purge may be, for example for about 1 to 30 seconds or more. Purging means that vapor phase catalyst and/or vapor phase byproducts, if any, are removed from the reaction chamber such as by evacuating the chamber with a vacuum pump and/or by replacing the gas inside the reaction chamber with an inert gas ); supplying a precursor to the structure, wherein a first portion of the precursor ( Illiberi, abstract, silicon precursor comprising a silanol; [0006], contacting the dielectric surface with a silicon reactant comprising a silanol; [0009], silicon reactant comprises tris(tert-butoxy)silanol (TBS), tris(isopropoxy)silanol (TIS), or tris(tert-pentoxy)silanol (TPS); [0088], The catalyst forms up to a molecular layer of catalytic sites on the dielectric surface of the substrate. The catalyst compound preferably catalyzes the formation of silicon oxide from a vapor phase silanol reactant. Briefly, the substrate is exposed to silanol, such as TPS, and a silicon oxide film, such as silicon dioxide film, for example SiO2 film is formed over the dielectric surface, as illustrated in FIG. 2E. The silicon oxide film 260 typically comprises multiple molecular layers ) forms the second insulating pattern ( Illiberi, FIG. 2E, 260; [0088], silicon oxide film 260 ); and performing a second purge ( Illiberi, [0211], TPS is then pulsed into the reaction chamber for 100 s, followed by a 90 s purge ) operation removing a second portion of the precursor other than the first portion of the precursor ( Illiberi, [0037], Excess catalyst and silanol may be removed from the substrate surface after each contacting step 140; [0204], providing a second vapor phase reactant pulse comprising a silanol to the reaction chamber; [0205], removing excess second reactant and reaction byproducts, if any, from the reaction chamber; [0211], TPS is then pulsed into the reaction chamber for 100 s, followed by a 90 s purge ). Regarding claim 10, Illiberi teaches the method as claimed in claim 9, Illiberi further teaches: wherein the catalyst includes at least one of aluminum alkyls ( Illiberi, [0009], metal catalyst comprises trimethyl aluminum (TMA) ), aluminum dialkylamides, aluminum alkoxides, mixed alkyl-alkoxy aluminum, dialkylaluminum chlorides, or dimethylaluminum i-propoxide (DMAI) ( Illiberi, [0009], dimethylaluminum isopropoxide (DMAI); [0090]–[0092] ). Regarding claim 11, Illiberi teaches the method as claimed in claim 9, Illiberi further teaches: wherein the precursor includes at least one of bis(tert-butoxy)(isopropoxy)silanol, bis(isopropoxy)(tert-butoxy)silanol, bis(tert-pentoxy)(isopropoxy)silanol, bis(isopropoxy)(tert-pentoxy)silanol, bis(tert-pentoxy)(tert-butoxy)silanol, bis(tert-butoxy)(tert-pentoxy)silanol, tris(tert-butoxy)silanol, or tris(tert-pentoxy)silanol ( Illiberi, [0009], the silicon reactant comprises tris(tert-butoxy)silanol (TBS), tris(isopropoxy)silanol (TIS), or tris(tert-pentoxy)silanol (TPS) ). Regarding claim 14, Illiberi teaches the method as claimed in claim 1, Illiberi further teaches: wherein the exposing of the structure to the reducing agent ( Illiberi, [0030], A plasma treatment may be used to activate the dielectric surface. For example, the silylated dielectric surface may be exposed to a H2 plasma ) and the forming of the passivation layer on the metal pattern ( Illiberi, FIG. 2C, 240; [0041], The passivation layer on the dielectric surface may facilitate selectivity for the subsequent passivation of the metal surface by a polymer ) are performed continuously in a same deposition equipment ( Illiberi, [0063] the silylation process and/or plasma treatment may be carried out in situ, that is in the same reaction chamber as other parts of the deposition process ). Regarding Independent claim 15, Illiberi teaches a method of manufacturing a semiconductor device, the method comprising: providing a structure comprising a first insulating pattern ( Illiberi, FIG. 2A, dielectric surface 220; [0043], [0226] – [0227] ) and a metal pattern ( Illiberi, FIG. 2A, metal surface 210; [0043] and [0226] – [0227] ) disposed on a substrate; performing a cleaning process on the structure ( Illiberi, [0064], the substrate may be pretreated or cleaned prior to or at the beginning of the deposition process … the substrate may be subjected to a plasma cleaning process prior to or at the beginning of the deposition process ); exposing the structure to a reducing agent ( Illiberi, [0029], A polymer passivation layer may be selectively formed on the metal surface relative to the dielectric surface. In some embodiments the passivation agent on the dielectric surface inhibits or prevents formation of the polymer passivation layer on the dielectric surface; [0030], A plasma treatment may be used to activate the dielectric surface. For example, the silylated dielectric surface may be exposed to a H2 plasma; [0041], The passivation layer on the dielectric surface may facilitate selectivity for the subsequent passivation of the metal surface by a polymer. In addition, the passivation layer on the dielectric can serve to functionalize the surface such that the catalyst is able to chemisorb on the dielectric surface … passivation layer on the dielectric surface can be activated, such as by exposure to a plasma reactant, for example H2 plasma ); forming, selectively, a passivation layer on the metal pattern ( Illiberi, FIG. 2C, 240; [0036], metal surface is passivated 120 by exposure to one or more second passivation agents, leading to selective formation of a polymer layer on the metal surface; [0087], metal surface 210 that has been passivated with a polymer layer 240; [0226], selective polymer passivation 240 of the metal surface 210 relative to the dielectric surface 220 ); forming, selectively, a second insulating pattern on the first insulating pattern ( Illiberi, FIG. 2E, 260; [0088], silicon oxide film 260 typically comprises multiple molecular layers; [0266], elective deposition of silicon oxide 260 on the dielectric surface 220 relative to the polymer passivated metal surface; [0231], silicon oxide 260 is formed by exposing the substrate to a silanol reactant, such as tris(tert-pentoxy)silanol. The silanol reactant may decompose on the aluminum atoms on the catalyzed dielectric surface, leading to the deposition of silicon oxide 260 on the dielectric surface 220 ); and performing thermal processing on the structure ( Illiberi, [0234], Additional treatments, such as heat or chemical treatment, can be conducted prior to, after or between the foregoing processes. For example, treatments may modify the surfaces or remove portions of the metal, silicon oxide, passivation and metal oxide surfaces exposed at various stages of the process ), wherein the forming of the second insulating pattern ( Illiberi, FIG. 2E, silicon oxide film 260 ) comprises a plurality of cycles ( Illiberi, FIG. 1, 130, 160; [0037], A silicon oxide deposition sub-cycle 130 is carried out in which the substrate is contacted with the catalyst 140 and a silicon precursor 140, such as a silanol. As mentioned above, in some embodiments the substrate is contacted with an oxygen reactant such as H2O in addition to the silicon reactant. Excess catalyst and silanol may be removed from the substrate surface after each contacting step 140 and 150. The sub-cycle may be repeated 160 multiple times in a single deposition cycle 100 ), each of the plurality of cycles comprising: supplying a catalyst to the structure, wherein a first portion of the catalyst ( Illiberi, FIG. 2D, 250; [0087] As shown in FIG. 2D, in some embodiments an aluminum catalyst 250 is selectively deposited on the dielectric surface 220 relative to a metal surface 210; [0230], The aluminum catalyst 250 may be formed selectively on the dielectric surface 220 by exposing the substrate to an aluminum reactant such as trimethyl aluminum (TMA), dimethylaluminumchloride, aluminum trichloride (AlCl3), dimethylaluminum isopropoxide (DMAI), tris(tertbutyl)aluminum (TTBA), tris(isopropoxide)aluminum (TIPA) or triethyl aluminum (TEA) ) is adsorbed by the first insulating pattern; performing a first purge ( Illiberi,[0098], [0211], Trimethyl aluminum (TMA) is pulsed into the reaction chamber for 150 ms, followed by a 3 s purge ) operation removing a second portion of catalyst, other than the first portion of the catalyst ( Illiberi,[0098], In between pulses, excess catalyst may be removed from the reaction space. For example, the reaction chamber may be evacuated and/or purged with an inert gas. The purge may be, for example for about 1 to 30 seconds or more. Purging means that vapor phase catalyst and/or vapor phase byproducts, if any, are removed from the reaction chamber such as by evacuating the chamber with a vacuum pump and/or by replacing the gas inside the reaction chamber with an inert gas ); supplying a precursor to the structure, a first portion of the precursor ( Illiberi, abstract, silicon precursor comprising a silanol; [0006], contacting the dielectric surface with a silicon reactant comprising a silanol; [0009], silicon reactant comprises tris(tert-butoxy)silanol (TBS), tris(isopropoxy)silanol (TIS), or tris(tert-pentoxy)silanol (TPS); [0088], The catalyst forms up to a molecular layer of catalytic sites on the dielectric surface of the substrate. The catalyst compound preferably catalyzes the formation of silicon oxide from a vapor phase silanol reactant. Briefly, the substrate is exposed to silanol, such as TPS, and a silicon oxide film, such as silicon dioxide film, for example SiO2 film is formed over the dielectric surface, as illustrated in FIG. 2E. The silicon oxide film 260 typically comprises multiple molecular layers ) forming the second insulating pattern ( Illiberi, FIG. 2E, 260; [0088], silicon oxide film 260 ); and performing a second purge ( Illiberi, [0211], TPS is then pulsed into the reaction chamber for 100 s, followed by a 90 s purge ) operation removing a second portion of the precursor other than the first portion of the precursor ( Illiberi, [0037], Excess catalyst and silanol may be removed from the substrate surface after each contacting step 140; [0204], providing a second vapor phase reactant pulse comprising a silanol to the reaction chamber; [0205], removing excess second reactant and reaction byproducts, if any, from the reaction chamber; [0211], TPS is then pulsed into the reaction chamber for 100 s, followed by a 90 s purge ). Regarding claim 16, Illiberi teaches the method as claimed in claim 15, Illiberi further teaches: wherein the performing of the cleaning process on the structure comprises supplying a cleaning liquid including an organic acid having a carboxyl group ( Illiberi, [0079], carboxylic acid; [0212], In some embodiments the cleaning step may comprise etching ). Regarding claim 17, Illiberi teaches the method as claimed in claim 15, Illiberi further teaches: wherein the reducing agent includes a hydrogen-based plasma ( Illiberi, [0041] and [0062]–[0064] ) ( Illiberi, [0030], A plasma treatment may be used to activate the dielectric surface. For example, the silylated dielectric surface may be exposed to a H2 plasma; [0041], passivation layer on the dielectric surface can be activated, such as by exposure to a plasma reactant, for example H2 plasma ). Regarding claim 18, Illiberi teaches the method as claimed in claim 15, Illiberi further teaches: wherein the forming the passivation layer ( Illiberi, FIG. 2C, selective polymer passivation 240 ) on the metal pattern ( Illiberi, FIG. 2C, metal surface 210 ) includes exposing the structure to a passivation gas, and the passivation gas includes at least one of methanethiol, ethanethiol, propanethiol, butanethiol, pentanethiol, hexanethiol, heptanethiol, octanethiol, nonanethiol, decanethiol, undecanethiol, dodecanethiol ( Illiberi, [0036], a self-assembled monolayer (SAM) is selectively formed on the metal layer, for example from a vapor-phase dodecanethiol precursor; [0081], SAM passivation layer may be selectively formed on the metal surface by contacting the substrate with a sulfur-containing monomer, such as 1-dodecanethiol (CH3(CH2)11SH), which can be referred to as a thiol SAM precursor or monomer ), tridecanethiol, tetradecanethiol, pentadecanethiol, hexadecanethiol, heptadecanethiol, octadecanethiol, nonadecanethiol, tetrahydro-2H-pyran-4-thiol, 2-propene-1-thiol, tetrahydro-2H-pyran-4-thiol, thiophenol, 4-methyl-1-thiophenol, 3-methyl-1-thiophenol, 2-methyl-1-thiophenol, para-xylene-alpha-thiol, 1H,1H,2H,2H-perfluorodecanethiol, 2,2,2-trifluoroethanethiol, 4-methyl-6-trifluoromethyl-pyrimidine-2-thiol, 4-trifluoromethylbenzyl mercaptan, 4-(trifluoromethoxy)benzyl mercaptan, 4-fluorobenzyl mercaptan, 3,5-bis(trifluoromethyl)benzenethiol, 2-(trifluoromethyl)benzenethiol, 4-trifluoromethyl-2,3,5,6-tetrafluorothiophenol, 3,5-difluorobenzyl mercaptan, 4-trifluoromethyl-2,3,5,6-tetrafluorothiophenol, para-trifluoromethylbenzenethiol, di-tert-butyl disulfide, or di-heptane disulfide. Regarding claim 19, Illiberi teaches the method as claimed in claim 15, Illiberi further teaches: wherein the catalyst includes at least one of aluminum alkyls, aluminum dialkylamides, aluminum alkoxides, mixed alkyl-alkoxy aluminum, or dialkylaluminum chlorides, and the precursor includes at least one of bis(tert-butoxy)(isopropoxy)silanol, bis(isopropoxy)(tert-butoxy)silanol, bis(tert-pentoxy)(isopropoxy)silanol, bis(isopropoxy)(tert-pentoxy)silanol, bis(tert-pentoxy)(tert-butoxy)silanol, bis(tert-butoxy)(tert-pentoxy)silanol, tris(tert-butoxy)silanol, or tris(tert-pentoxy)silanol. wherein the catalyst includes at least one of aluminum alkyls ( Illiberi, [0009], metal catalyst comprises trimethyl aluminum (TMA) ), aluminum dialkylamides, aluminum alkoxides, mixed alkyl-alkoxy aluminum, or dialkylaluminum chlorides, and the precursor includes at least one of bis(tert-butoxy)(isopropoxy)silanol, bis(isopropoxy)(tert-butoxy)silanol, bis(tert-pentoxy)(isopropoxy)silanol, bis(isopropoxy)(tert-pentoxy)silanol, bis(tert-pentoxy)(tert-butoxy)silanol, bis(tert-butoxy)(tert-pentoxy)silanol, tris(tert-butoxy)silanol, or tris(tert-pentoxy)silanol ( Illiberi, [0009], the silicon reactant comprises tris(tert-butoxy)silanol (TBS), tris(isopropoxy)silanol (TIS), or tris(tert-pentoxy)silanol (TPS) ). Regarding Independent Claim 20, Illiberi teaches a method of manufacturing a semiconductor device, the method comprising: placing, in a cleaning liquid ( Illiberi, [0064], the substrate may be pretreated or cleaned prior to or at the beginning of the deposition process ), a structure comprising a first insulating pattern ( Illiberi, FIG. 2A, dielectric surface 220; [0043], [0226] – [0227] ) and a metal pattern ( Illiberi, FIG. 2A, metal surface 210; [0043] and [0226] – [0227] ) disposed on a substrate; performing a cleaning process ( Illiberi, [0064], the substrate may be pretreated or cleaned prior to or at the beginning of the deposition process … the substrate may be subjected to a plasma cleaning process prior to or at the beginning of the deposition process ) on the structure; disposing the structure within a deposition equipment ( Illiberi, [0042], Examples of suitable reactors that may be used in the selective deposition processes described herein include commercially available atomic layer deposition (ALD) equipment. In addition to ALD reactors, many other kinds of reactors capable of growth of polymer passivation layers, including chemical vapor deposition (CVD) reactors, vapor deposition polymerization (VDP) reactors, and molecular layer deposition (MLD) reactors, can be employed ); exposing the structure to a reducing agent ( Illiberi, [0029], A polymer passivation layer may be selectively formed on the metal surface relative to the dielectric surface. In some embodiments the passivation agent on the dielectric surface inhibits or prevents formation of the polymer passivation layer on the dielectric surface; [0030], A plasma treatment may be used to activate the dielectric surface. For example, the silylated dielectric surface may be exposed to a H2 plasma; [0041], The passivation layer on the dielectric surface may facilitate selectivity for the subsequent passivation of the metal surface by a polymer. In addition, the passivation layer on the dielectric can serve to functionalize the surface such that the catalyst is able to chemisorb on the dielectric surface … passivation layer on the dielectric surface can be activated, such as by exposure to a plasma reactant, for example H2 plasma ) in a first process chamber ( Illiberi, [0042] ) included in the deposition equipment; forming, selectively, a passivation layer on the metal pattern ( Illiberi, FIG. 2C, 240; [0036], metal surface is passivated 120 by exposure to one or more second passivation agents, leading to selective formation of a polymer layer on the metal surface; [0087], metal surface 210 that has been passivated with a polymer layer 240; [0226], selective polymer passivation 240 of the metal surface 210 relative to the dielectric surface 220 ) in a second process chamber ( Illiberi, [0042] ) included in the deposition equipment different from the first process chamber ( Illiberi, [0042] ) ; forming, selectively, a second insulating pattern on the first insulating pattern ( Illiberi, FIG. 2E, 260; [0088], silicon oxide film 260 typically comprises multiple molecular layers; [0266], elective deposition of silicon oxide 260 on the dielectric surface 220 relative to the polymer passivated metal surface; [0231], silicon oxide 260 is formed by exposing the substrate to a silanol reactant, such as tris(tert-pentoxy)silanol. The silanol reactant may decompose on the aluminum atoms on the catalyzed dielectric surface, leading to the deposition of silicon oxide 260 on the dielectric surface 220 ); and performing thermal processing on the structure ( Illiberi, [0234], Additional treatments, such as heat or chemical treatment, can be conducted prior to, after or between the foregoing processes. For example, treatments may modify the surfaces or remove portions of the metal, silicon oxide, passivation and metal oxide surfaces exposed at various stages of the process ), wherein the exposing of the structure to the reducing agent and the forming of the passivation layer on the metal pattern include disconnecting the first process chamber and the second process chamber from each other ( Illiberi, [0063], However, in some embodiments the silylation and/or plasma treatment may be carried out in a separate reaction chamber from one or more other processing steps. In some embodiments the reaction chamber in which the silylation is carried out is part of a cluster tool, including one or more additional reaction chambers. For example, such a cluster tool may include additional reaction chambers for the plasma treatment of the silylated dielectric surface, for formation of a polymer passivation layer on the metal surface, for the deposition of the aluminum catalyst on the dielectric surface, for the deposition of silicon oxide on the dielectric surface, and/or for etching one or more layers ). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Illiberi, in view of Clark (Pub. No. 20190295903 A1), hereinafter Clark. Regarding claim 6, Illiberi teaches the method as claimed in claim 1, Illiberi fails to disclose: wherein the reducing agent includes at least one of methanol, ethanol, n-propanol, or isopropanol. However, Clark teaches: wherein the reducing agent includes at least one of methanol, ethanol, n-propanol, or isopropanol ( Clerk, [0058], For example, the treatment gas can include … isopropyl alcohol … The treatment gas can clean or alter the surface of either the target dielectric surface 220 or the non-target metal surface 230 to improve subsequent ASD (area-selective deposition) ). Illiberi and Clark are both considered to be analogous to the claimed invention because they are forming selective deposition of silicon oxide films on dielectric surfaces relative to metal surfaces. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Illiberi ( [0030], A plasma treatment may be used to activate the dielectric surface; [0041], The passivation layer on the dielectric surface may facilitate selectivity for the subsequent passivation of the metal surface by a polymer ), to incorporate the teachings of Clark ( [0058], For example, the treatment gas can include … isopropyl alcohol … to improve subsequent ASD (area-selective deposition) ), to implement that the reducing agent includes isopropanol. Doing so would provide a specific component for the reducing agent, and therefore the selective deposition of silicon oxide films on dielectric surfaces relative to metal surfaces can be improved. Claims 12, 13 are rejected under 35 U.S.C. 103 as being unpatentable over Illiberi, in view of Reid (Pub. No. 20050064726A1), hereinafter Reid. Regarding claim 12, Illiberi teaches the method as claimed in claim 1, Illiberi fails to disclose: wherein the performing of the thermal processing on the structure includes performing rapid thermal processing (RTP), wherein a temperature increase rate of the RTP is about 20 °C/s to about 30 °C/s, and the RTP is performed for about 25 minutes to about 35 minutes. However, Reid teaches: wherein the performing of the thermal processing on the structure includes performing rapid thermal processing (RTP) ( Reid, [0041], rapid thermal curing (RTD) ), wherein a temperature increase rate of the RTP is about 20 °C/s to about 30 °C/s ( Reid, [0043], Typically, the temperature is increased at 10 to 70° C. per second ), and the RTP is performed for about 25 minutes to about 35 minutes ( Reid, [0044], it is cured for extensive periods of at least 15 minutes, typically more than 30 minutes ). Illiberi and Reid are both considered to be analogous to the claimed invention because they are forming dielectric structures and conducting heat treatment in semiconductor devices. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Illiberi ( [0234], heat … treatment, can be conducted prior to, after or between the foregoing processes … modify the surfaces or remove portions of the metal, silicon oxide, passivation and metal oxide surfaces ), to incorporate the teachings of Reid ( [0041], rapid thermal curing (RTD); [0043], Typically, the temperature is increased at 10 to 70° C. per second; [0044], it is cured for extensive periods of at least 15 minutes, typically more than 30 minutes ), to implement that “ wherein the performing of the thermal processing on the structure includes performing rapid thermal processing (RTP), wherein a temperature increase rate of the RTP is about 20 °C/s to about 30 °C/s, and the RTP is performed for about 25 minutes to about 35 minutes ”. Doing so would provide that the dielectric constant of the same material will be decreased by more than 0.2 because of the rapid thermal curing ( Reid, [0044] ), and therefore to reduce the parasitic capacitance and increase the speed of semiconductor devices. Regarding claim 13, Illiberi and Reid teach the method as claimed in claim 12, Reid further teaches: wherein the thermal processing on the structure is performed in a temperature range of about 350 °C to about 400 °C ( Reid, [0049], It is particularly preferred to apply the rapid thermal curing at least in the higher temperature ranges of the curing process--such temperatures range from 300°C or more up to the final curing temperature. The latter temperature is 400°C or more ), wherein the RTP is performed for about 25 minutes to about 35 minutes at a highest temperature used in the RTP ( Reid, [0044], it is cured for extensive periods of at least 15 minutes, typically more than 30 minutes ). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Da-Wei Lee whose telephone number is 703-756-1792. The examiner can normally be reached M -̶ F 8:00 am -̶ 6:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DA-WEI LEE/Examiner, Art Unit 2817 /MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
Read full office action

Prosecution Timeline

Sep 06, 2024
Application Filed
Sep 17, 2026
Non-Final Rejection mailed — §102, §103
Oct 01, 2026
Interview Requested

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12751057
TRANSISTOR STRUCTURE WITH GATE ISOLATION STRUCTURES AND METHOD OF FABRICATING THEREOF
3y 7m to grant Granted Sep 29, 2026
Patent 12733165
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
4y 3m to grant Granted Sep 08, 2026
Patent 12713627
PACKAGE WITH A SUBSTRATE COMPRISING EMBEDDED STACKED TRENCH CAPACITOR DEVICES
4y 0m to grant Granted Aug 18, 2026
Patent 12701931
METHOD OF SELECTIVELY FORMING PHOSPHOROUS-DOPED EPITAXIAL MATERIAL ON A SURFACE
3y 3m to grant Granted Aug 04, 2026
Patent 12672309
SEMICONDUCTOR STRUCTURES WITH WRAP-AROUND CONTACT STRUCTURE
4y 6m to grant Granted Jun 30, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
80%
Grant Probability
96%
With Interview (+15.4%)
3y 6m (~1y 5m remaining)
Median Time to Grant
Low
PTA Risk
Based on 46 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month