DETAILED ACTION
This action is responsive to the following communications: the Application filed on September 6, 2024, the Continuation of application No. 17/948,423 filed on September 20, 2022 and the Information Disclosure Statement filed on September 6, 2024.
Claims 1-20 are pending. Claims 1, 8 and 14 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statement (IDS) filed on September 6, 2024. This IDS has been considered.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
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Claims 1-5, 8-10, 12-17 and 19-20 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 5-6, 8-9, 12, 14-18 and 25 of U.S. Patent No. 12,087,391. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims in the U.S. Patent No. 12,087,391 disclose the subject matter of the claims in the instant application.
Claims of instant application are compared to claims of the U.S. Patent No. 12,087,391 in the following table:
Instant Application
U.S. Patent 12087391
1. An apparatus, comprising:
a memory device, comprising:
an array of memory cells; and
circuitry configured to:
sense a codeword stored in the array of memory cells;
determine a value of a cell metric of each memory cell of the sensed codeword,
determine which cell metric of each of the memory cells has a lowest value;
input the cell metric determined to have the lowest value to a Pearson detector; and
determine originally programmed data of the codeword using the Pearson detector.
2. The apparatus of claim 1, wherein the value of the cell metric of each of the memory cells is determined based on a summation of a threshold voltage value of each of the memory cells.
3. The apparatus of claim 1, wherein the value of the cell metric of each of the memory cells is determined based on:
a mean of threshold voltage values of the memory cells; and
a value proportional to the mean of the threshold voltage values of the memory cells.
1. An apparatus, comprising:
a memory device, comprising:
an array of memory cells; and
circuitry configured to:
sense a codeword stored in the array of memory cells;
determine a value of a cell metric of each memory cell of the sensed codeword, wherein the value of the cell metric of each of the memory cells is determined based on:
a summation of a threshold voltage value of each of the memory cells;
a mean of the threshold voltage values of the memory cells; and
a value proportional to the mean of the threshold voltage values of the memory cells;
determine which cell metric of each of the memory cells has a lowest value;
input the cell metric determined to have the lowest value to a Pearson detector; and
determine originally programmed data of the codeword using the Pearson detector.
4. The apparatus of claim 1, wherein the cell metric determined to have the lowest value is a weight estimator.
14. The apparatus of claim 13, wherein the Pearson detector determines the lowest Pearson distance using a weight estimator.
5. The apparatus of claim 1, wherein each of the memory cells has a respective switching event time.
6. The method of claim 5, further comprising determining the threshold voltage value of each of the memory cells after a switching event occurs in each of the memory cells.
8. A method, comprising:
sensing a codeword stored in an array of memory cells of a memory device;
determining, by the memory device, for each memory cell of the sensed codeword, a value of a cell metric of each of the memory cells of the sensed codeword;
determining, by the memory device, which cell metric of each of the memory cells has a lowest value;
inputting the cell metric determined to have the lowest value to a Pearson detector; and
determining originally programmed data of the codeword using the Pearson detector.
5. A method, comprising:
sensing a codeword stored in an array of memory cells of a memory device;
determining, by the memory device, for each memory cell of the sensed codeword, a value of a cell metric of each of the memory cells of the sensed codeword, wherein the value of the cell metric of each of the memory cells of the sensed codeword is determined based on:
a summation of a threshold voltage value of each of the memory cells;
a mean of the threshold voltage values of the memory cells; and
a value proportional to the mean of the threshold voltage values of the memory cells;
determining, by the memory device, which cell metric of each of the memory cells has a lowest value;
inputting the cell metric determined to have the lowest value to a Pearson detector; and
determining originally programmed data of the codeword using the Pearson detector.
9. The method of claim 8, further comprising dividing sorted threshold voltage values of the memory cells into a first distribution and a second distribution, wherein a height and width of the first threshold distribution is equal to a height and width of the second threshold distribution.
9. The method of claim 8, further comprising dividing the sorted threshold voltage values into a first distribution and a second distribution.
10. The method of claim 9, wherein the threshold voltage values included in the first distribution are less than the threshold voltage values included in the second distribution.
8. The method of claim 5, further comprising sorting the threshold voltage values of each of the memory cells in ascending order.
12. The method of claim 8, further comprising adding a data bit having a value of 0 to the sensed codeword if the sensed codeword only comprises data bits having a value of 1.
25. The method of claim 21, further comprising adding a data bit having a first value to the codeword if the sensed codeword only comprises data bits having a second value.
13. The method of claim 8, further comprising adding a data bit having a value of 1 to the sensed codeword if the sensed codeword only comprises data bits having a value of 0.
25. The method of claim 21, further comprising adding a data bit having a first value to the codeword if the sensed codeword only comprises data bits having a second value.
14. An apparatus, comprising:
a memory device comprising an array of memory cells; and
a controller coupled to the memory device and configured to:
sense a codeword stored in the array of memory cells;
determine, for each memory cell of the sensed codeword in the memory device, a value of a cell metric of each of the memory cells of the sensed codeword;
determine which cell metric of each of the memory cells has a lowest value;
input the cell metric determined to have the lowest value to a Pearson detector; and
determine originally programmed data of the codeword using the Pearson detector.
12. An apparatus, comprising:
a memory device comprising an array of memory cells; and
a controller coupled to the memory device and configured to:
sense a codeword stored in the array of memory cells;
determine, for each memory cell of the sensed codeword in the memory device, a value of a cell metric of each of the memory cells of the sensed codeword, wherein the value of the cell metric of each of the memory cells of the codeword is determined based on:
a summation of a threshold voltage value of each of the memory cells;
a mean of the threshold voltage values of the memory cells;
and a value proportional to the mean of the threshold voltage values of the memory cells;
determine which cell metric of each of the memory cells has a lowest value; and
input the cell metric determined to have the lowest value to a Pearson detector; and
determine originally programmed data of the codeword using the Pearson detector.
15. The apparatus of claim 14, wherein the memory device includes a plurality of switches configured to couple the memory cells to a plurality of connectors.
15. The apparatus of claim 12, wherein the memory device includes a plurality of switches, wherein each respective one of the plurality of switches is configured to couple a different one of the memory cells to a different one of a plurality of connectors.
16. The apparatus of claim 15, wherein a memory cell of the memory cells is coupled to a ramp voltage line when the memory cell is coupled to a first connector of the plurality of connectors.
16. The apparatus of claim 15, wherein each of the memory cells is coupled to a ramped voltage when its respective switch is coupled to a first connector of the plurality of connectors.
17. The apparatus of claim 16, wherein the memory cell stores a voltage of the memory cell when the memory cell is coupled to a second connector of the plurality of connectors.
17. The apparatus of claim of claim 16, wherein each respective one of the plurality of switches is configured to decouple from the first connector and couple to a second connector of the plurality of connectors once its respective memory cell experiences a switching event.
19. The apparatus of claim 15, wherein a time at which the memory cells couple to the plurality of connectors is based on a time at which a switching even occurs in the memory cells.
17. The apparatus of claim of claim 16, wherein each respective one of the plurality of switches is configured to decouple from the first connector and couple to a second connector of the plurality of connectors once its respective memory cell experiences a switching event.
20. The apparatus of claim 17, wherein the plurality of switches are configured to couple the memory cells to a third connector in response to every memory cell in the codeword being coupled to a respective second connector.
18. The apparatus of claim 17, wherein each respective one of the plurality of switches is configured to decouple from the second connector and couple to a third connector when each of the plurality of memory cells experiences the switching event.
Allowable Subject Matter
Claims 6-7, 11 and 18 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 6, the closest prior art, Mittelholzer et al. (US 20130086457), describes a method for detecting codewords from read signals in solid-state memory and doing robustly to drift by emphasizing information and by estimating reference levels for detection. However, Mittelholzer et al. do not teach or suggest a first memory cell of the memory cells has a first switching event time and a second memory cell of the memory cells has a second switching event time that is different than the first switching event time.
Thus, there is no teaching or suggestion in the prior art of record to provide the recited wherein a first memory cell of the memory cells has a first switching event time and a second memory cell of the memory cells has a second switching event time that is different than the first switching event time.
With respect to claim 7, there is no teaching or suggestion in the prior art of record to provide the recited wherein the respective switching event time of each of the memory cells is a time at which a value of a ramp up voltage being applied to the memory cell equals a threshold voltage of the memory cell.
With respect to claim 11, there is no teaching or suggestion in the prior art of record to provide the recited further comprising determining a mean of threshold voltage values of the memory cells by measuring a total voltage value of the memory cells coupled to a mean voltage line and dividing the total voltage value by a number of the memory cells coupled to the mean voltage line.
With respect to claim 18, there is no teaching or suggestion in the prior art of record to provide the recited wherein each of the plurality of switches is configured to couple the memory device to the plurality of connectors at a first time and an additional memory device of the apparatus to the plurality of connectors at a second time that is different than the first time.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY H LUONG whose telephone number is (571)270-5088. The examiner can normally be reached Mon-Fri. 9am-6pm.
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/DUY H LUONG/ Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/ Supervisory Patent Examiner, Art Unit 2825