DETAILED ACTION
This action is responsive to the amendments filed July 2, 2026. Prior to entry, claims 1-20 were pending. Claims 9, 13, 15 and 20 have been cancelled. Claims 1, 4-6, 8, 10-11, and 16-17 have been amended. Claims 21-24 are new. Thus, claims 1-8, 10-12, 14, 16-19, and 21-24 are currently pending. Claims 1, 11, and 16 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
Applicant’s cancellation of claims 9, 13 and 20 render the drawing objections of the previous Office action moot. The drawing objections are therefore withdrawn.
Response to Amendment
Claims 11-20 were rejected under 35 U.S.C. § 101 as directed to a judicial exception (the natural phenomenon of PCM resistance drift) implemented by the limitation that the programmed ones be allowed to degrade to zeros after a predetermined time period. Similarly, claims 11-20 were also rejected under 35 U.S.C. § 112(b) for the same phrase because it is a relative term that the specification does not define with objective bounds.
Independent claims 11 and 16 have been amended to delete that limitation and therefore the § 101 and § 112(b) rejections due to those issues have been withdrawn.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The current title is “Using Phase Change Memory (PCM) Drift to Erase Hyperdimensional (HD) Model for Secure Edge Computing”. That title describes using resistance drift to erase a hyperdimensional model after some interval. Independent claims 1, 11, and 16 as amended, no longer recite erasing a model by drift, a hyperdimensional model, security, or an edge device. They are directed to a dual-device PCM cell whose devices have unequal drift, and to programming one device to a near-reset resistance as logic one and the other to a set resistance as logic one. The title is therefore not specific to the invention now claimed.
The following title is suggested: Phase-Change Memory Array with Unequal Drift Devices and Method of Programming Same.
Claim Rejections - 35 USC § 112 – Written Description
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 1–8, 10–12, 14, 16–19, and 21–24 are rejected under 35 U.S.C. § 112(a) as failing to comply with the written description requirement. The claims contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, at the time the application was filed, had possession of the claimed invention.
Independent claims 1, 11, and 16, as amended, require that both devices of the cell be programmed to logic one: the higher-drift device to a near-reset resistance “based at least in part on the first drift,” and the lower-drift device to a set resistance lower than that near-reset resistance. The remaining rejected claims inherit that limitation.
For this rejection, “logic one” is a binary label assigned to a programmed resistance; “near-reset resistance” is a resistance in the reset / partial-reset regime; and “based at least in part on the first drift” requires that the near-reset target on the first device be selected, at least in part, because of that device’s higher drift. The dual-device cell of FIGS. 4–6 is described. The claimed cooperative programming of both devices to logic one is not.
The specification programs the dual-device cell in three alternative modes. [0045]: only the no-liner device is programmed to near-reset (Mode A) or near-set (Mode B); or only the liner device is programmed, and the other is left as a reference (Mode C). No mode programs the high-drift device to near-reset and the low-drift device to set, and no mode assigns logic one to both devices.
Zeroes and ones are instead both encoded in a near-reset state on the programmed device. [0007], [0046], [0071], FIG. 8. The specification distinguishes that choice from the prior-art convention of logic one at set. [0070]. The amended claims apply near-reset to one device and set to the other, and call both “logic one.” That composite is not described.
The specification also does not describe using the first drift as an input that sets the programmed resistance. [0039] and [0045] state only that the high-drift device is put in near-reset “to ‘forget’ faster.” The phrase “based at least in part on the first drift,” and the term “logic one,” do not appear in the original disclosure as now claimed.
The amendment therefore introduces new matter. Additionally, applicant’s reply does not identify support as required by MPEP § 714.02.
Dependent claims 2–8, 10, 12, 14, 17–19, and 21–24 add liner / material, connection, inferencing, HD, or edge features that appear in the specification. They do not supply the missing dual-program-to-logic-one limitation.
This written description rejection is independent of the prior art rejections below. For those rejections the amended language is given its broadest reasonable interpretation. Application of art under that interpretation is not a concession that the specification describes the limitation. MPEP § 2173.06.
Claim Rejections - 35 USC § 112 - Indefiniteness
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1–8, 10–12, 14, 16–19, and 21–24 are rejected under 35 U.S.C. § 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
1. “a first / second phase change memory device of the plurality of cells” — claims 1, 11, 16
Each independent claim first recites that each cell comprises “a first phase change memory device having a first drift” and “a second phase change memory device having a second drift.” The amended language of the claim then recites programming “a first phase change memory device of the plurality of cells” to logic one at a near-reset resistance and “a second phase change memory device of the plurality of cells” to logic one at a set resistance.
It is unclear whether those later phrases refer to
(1) the first-drift and second-drift devices of a given cell,
(2) one first-drift device and one second-drift device selected from different cells, or
(3) any two devices in the array.
The claimed cooperative configuration cannot be determined. See MPEP § 2173.05(e).
Claims 2–8, 10, 12, 14, 17–19, and 21–24 depend from claims 1, 11, or 16 and are indefinite for the same reason.
2. “based at least in part on the first drift” — claims 1, 11, 16
The independent claims require that the first device be programmed to a near-reset resistance “based at least in part on the first drift.” The specification does not define what relationship that phrase requires. It is unclear whether the programmer must measure the first drift and compute a target resistance from it, select near-reset solely because the first device is the higher-drift device of the pair, or apply any near-reset pulse to a device that happens to have higher drift. A person of ordinary skill cannot determine the metes and bounds of the limitation. MPEP § 2173.05(b).
3. Claim 16 — incomplete cooperative configuration
Claim 16 recites that the model control and the array program and read circuit are cooperatively configured to cause:
the memory array to be programmed with a model including a plurality of zeroes and ones, wherein a first phase change memory device of the plurality of cells is programmed to logic one by programming the first phase change memory device to a near-reset resistance based at least in part on the first drift a second phase change memory device of the plurality of cells to be programmed to logic one by programming the second phase change memory device to a set resistance lower than the near-reset resistance; and the memory array to carry out inferencing
The second program clause is not joined to the “wherein” clause and shifts from “is programmed” to “to be programmed.” It is unclear whether the second-device program is part of programming the model of zeroes and ones, a separate required operation, or an intended result. Claims 17–19 and 23–24 inherit the defect.
For prior-art purposes the independent claims are interpreted, under their broadest reasonable interpretation, as requiring that the higher-drift device of a cell be placed in a near-reset resistance and the lower-drift device of that same cell be placed in a lower set resistance, with both states treated as logic one. See MPEP § 2173.06
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, and 4-5 are rejected under 35 U.S.C. § 102(a)(1) as being anticipated by Lung (US 20110063902 – of record), as evidenced by Wimmer et al. ("Role of activation energy in resistance drift of amorphous phase change materials"; "Wimmer" – of record).
Regarding independent claim 1, notwithstanding the rejections for written description and indefiniteness above, Lung discloses a system comprising:
a memory array comprising (Fig. 3A where it illustrates memory array 212):
a plurality of word lines (Fig. 3A word lines 216a and 216b for example);
a plurality of bit lines intersecting the plurality of word lines at a plurality of cell locations (Fig. 3A bit lines 220a and 220b for example);
and a plurality of cells respectively located at the plurality of cell locations (Fig. 3A where it illustrates device 302 and 304 as comprising a 2T2R cell. See also para. 39; “Four memory cells 301-304 are illustrated in FIG. 3A”, “each memory cell in the array 212 can be operated in a single mode”, “using the difference in the resistance of the corresponding memory elements of the pair of memory cells to store a data value.”);
wherein each cell of the plurality of cells in turn comprises:
a first phase change memory device having a first drift; and a second phase change memory device having a second drift (Fig. 3A memory elements 312 and 314 of the pair 302,304. See also para. 11; " A memory device as described herein includes an array of programmable resistance memory cells such as phase change memory cells". Regarding the phase change memory device having a first /second drift, Lung’s pair inherently has a first (higher) drift on the partial-reset device and a second (lower) drift on the set device, as evidenced by Wimmer’s power-law for amorphous PCM (Wimmer p. 4; “the resistance drift effect in amorphous phase change materials is described by an empirically found power-law.”) See power-law formula below.)
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wherein the first drift is higher than the second drift (para. 13; "In the dual mode a data value is stored in the pair by setting one of the memory cells in the pair to a lower resistance state and setting the resistance of the other memory cell to a higher resistance state". See also para. 14; “the higher resistance state for the dual mode can be a "partial reset" or "partial set" state”. As stated above, Wimmer’s power-law demonstrates the reset state (amorphous) is the high resistance state and exhibits pronounced resistance drift while the set state (crystalline) is the low resistance state and shows minimal to negligible drift.).
and a model control coupled to the plurality of word lines and an array program and read circuit coupled to the plurality of bit lines (para. 34; “A controller 234 implemented in this example, using a bias arrangement state machine, controls the application of bias arrangement supply voltages and current sources 236, to apply bias arrangements such read, program, erase, erase verify, program verify, and refresh to the memory cells of the array 212.”, “The controller 234 also provides control signals to the bit line decoder 218”, “and also provides control signals to block 224 to control the operation of the single and dual mode sense amplifiers during read operations.”. It is noted that under the broadest reasonable interpretation, controller + WL decoder = “model control” and BL decoder + program/sense block = “array program and read circuit”.),
wherein the model control and the array program and read circuit are cooperatively configured to:
program a first phase change memory device of the plurality of cells by programming the first phase change memory device to a near-reset resistance based at least in part on the first drift (para. 13; “the dual mode a data value is stored in the pair by setting one of the memory cells in the pair to a lower resistance state and setting the resistance of the other memory cell to a higher resistance state”. And see para. 14; “the higher resistance state for the dual mode can be a "partial reset" or "partial set" state”. It is noted that Lung’s programming the device to partial-reset is programing it to near-reset resistance based at least in part on the first drift. “Logic one” is merely a label for that programed resistance. Lung stores a value in the pair; the claim term does not require a different pulse or a different resistance than Lung’s partial-reset state.);
and program a second phase change memory device of the plurality of cells to logic one by programming the second phase change memory device to a set resistance lower than the near-reset resistance (Id. and for the same reasons. It is noted that the dual-mode lower-resistance state is the set state. It is lower than the partial-reset / near-reset resistance of the first device (para. 14). Again, “Logic one” is merely a label. The second device is programmed to set; that is all the limitation requires beyond the label.).
Wimmer is not a combining reference. It is cited only to show that the amorphous / partial-reset device of Lung’s pair inherently has a higher drift that the set device. See MPEP § 2131.01, 2112
Regarding claim 4, Lung as evidenced by Wimmer discloses the limitations of claim 1.
As applied, Lung further discloses wherein the first phase change memory device and the second phase change memory device are connected in parallel and each of the plurality of cells is electrically connected to a corresponding bit line and selectively grounded under control of a corresponding one of the word lines (Fig. 3B. It is noted that this limitation appears to be directed to Fig. 4 which merely depicts the first and second devices as line and dotted line symbols to infer general parallel connectivity (rather than terminal for terminal parallel connectivity of the cells). Also, applicant's specification indicates that the word lines actually connect to FETs which then connects to the PCM cells (para. 59) and are therefore analogous to Lang's structure.).
Regarding claim 5, Lung as evidenced by Wimmer discloses the limitations of claim 4.
As applied, Lung further discloses wherein the model control (Fig. 2A: controller 234. See also para 34; "A controller 234 implemented in this example, using a bias arrangement state machine, controls the application of bias arrangement supply voltages and current sources 236, to apply bias arrangements such read, program, erase, erase verify, program verify, and refresh to the memory cells of the array 212")
is configured to select given ones of the plurality of cells for reset (para. 50; "In a reset (erase) operation of the memory cell 302, a reset pulse (or pulses) is (are) applied to the word line 216b and bit line 220b of suitable amplitude and duration to induce a current through the memory element 312 to cause a transition of an active region of the memory element 312 into an amorphous phase". It is noted that selecting a cell for reset is selecting it’s word line and bit line and applying the reset pulse).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6, 11, 16 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Lung (US 20110063902 – of record), as evidenced by Wimmer et al. ("Role of activation energy in resistance drift of amorphous phase change materials"; "Wimmer" – of record), in view of Le Gallo et al. ("A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference"; "Le Gallo 1"- of record)
Regarding claim 6, Lung, as evidenced by Wimmer, discloses the limitations of claim 5.
As applied, Lung further discloses further comprising an array program and read circuit coupled to the bit lines (Lung's block 224 discloses sense amplifiers 345 to read the bit lines)
Lung is silent with respect to the nature and type of information stored within the array.
However, Le Gallo 1 teaches and configured to program the cells and read out inferencing results (pgs. 2-3, sect II The computational Memory Core where it teaches also using A/D converters, summers, digital processing units and other circuitry to read out inferencing result from the array. See also Fig. 1c schematic. It is noted that while applicant indicates the array program and read circuit can "include A/D converters, shifters, summers, sense amplifier, etc." (Spec. 38), there is no specific configuration or proprietary timing logic for these components. The mere recitation of generic components performs predictable functions and does not patentably distinguish the claim from Le Gallo's computational memory core.).
Lung, and Le Gallo 1 are from the same field of endeavor as applicant' s invention directed to using and improving emerging technology of PCM storage to study complex physical systems that process information. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lung's PCM array with Le Gallo's inference operation to overcome the "memory wall" in traditional computing. Doing so would be more energy efficient because computation happens directly within the memory cells.
Regarding independent claim 11, notwithstanding the rejections for written description and indefiniteness above, Lung discloses method of operating a phase change memory array, comprising:
providing a phase change memory array including (Fig. 3A where it illustrates memory array 212):
a plurality of word lines (Fig. 3A word lines 216a and 216b for example);
a plurality of bit lines intersecting the plurality of word lines at a plurality of cell locations (Fig. 3A bit lines 220a and 220b for example);
and a plurality of cells respectively located at the plurality of cell locations (Fig. 3A where it illustrates device 302 and 304 as comprising a 2T2R cell. See also col. 6, ln. 65-66; "operated in a dual mode as part of a pair of memory cells 302, 304");
wherein each cell of the plurality of cells in turn comprises: a first phase change memory device having a first drift; and a second phase change memory device having a second drift (Fig. 3A memory elements 312 and 314 of the pair 302,304. See also para. 11; " A memory device as described herein includes an array of programmable resistance memory cells such as phase change memory cells". Regarding the phase change memory device having a first /second drift, Lung’s pair inherently has a first (higher) drift on the partial-reset device and a second (lower) drift on the set device, as evidenced by Wimmer’s power-law for amorphous PCM (Wimmer p. 4; “the resistance drift effect in amorphous phase change materials is described by an empirically found power-law.”) See power-law formula above.);
wherein the first drift is higher than the second drift (para. 13; "In the dual mode a data value is stored in the pair by setting one of the memory cells in the pair to a lower resistance state and setting the resistance of the other memory cell to a higher resistance state". See also para. 14; “the higher resistance state for the dual mode can be a "partial reset" or "partial set" state”. As stated above, Wimmer’s power-law demonstrates the reset state (amorphous) is the high resistance state and exhibits pronounced resistance drift while the set state (crystalline) is the low resistance state and shows minimal to negligible drift.).
programming the phase change memory array with a model including a plurality of zeroes and ones (Fig. 3A. See also col. 7, ln. 63-65; "The current through the memory cell 302 is dependent upon the resistance of the memory element 312 and thus the data value stored in the memory cell 302." It is well understood in the art that the data stored in memory cells is binary which is conventionally represented as zeros and ones),
wherein programming the phase change memory array with the model includes programming a first phase change memory device of the plurality of cells to logic one by programming the first phase change memory device to a near-reset resistance based at least in part on the first drift (para. 13; “the dual mode a data value is stored in the pair by setting one of the memory cells in the pair to a lower resistance state and setting the resistance of the other memory cell to a higher resistance state”. And see para. 14; “the higher resistance state for the dual mode can be a "partial reset" or "partial set" state”. It is noted that Lung’s programming the device to partial-reset is programing it to near-reset resistance based at least in part on the first drift. “Logic one” is merely a label for that programed resistance. Lung stores a value in the pair; the claim term does not require a different pulse or a different resistance than Lung’s partial-reset state.);
programming a second phase change memory device of the plurality of cells to logic one by programming the second phase change memory device to a set resistance lower than the near- reset resistance (Id. and for the same reasons. It is noted that the dual-mode lower-resistance state is the set state. It is lower than the partial-reset / near-reset resistance of the first device (para. 14). Again, “Logic one” is merely a label. The second device is programmed to set; that is all the limitation requires beyond the label.);
Lung, discloses a PCM 2T2R array programmed with set + partial-reset data values, but are silent with respect to carrying out inferencing with the array.
However, Le Gallo 1 teaches and carrying out inferencing with the phase change memory array (pg. 2, sect. I; "Each core contains a PCM crossbar array". See also pg. 2, intro. "The chip delivers simultaneously four key advances", "High MVM and inference accuracy are achieved". As noted in the rejection for indefiniteness above, the phrase "no more than a predetermined time period" will be interpreted to mean "some time period of any length".);
Lung along with Le Gallo 1 are from the same field of endeavor as applicant' s invention directed to using and improving emerging technology of PCM storage to study complex physical systems that process information. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lung’s PCM array with the teachings of Le Gallo 1' s inference and other DNN models to create an improved artificial intelligence system. Doing so would speed up complex computations that are difficult for traditional computers.
Regarding independent claim 16, notwithstanding the rejections for written description and indefiniteness above, Lung discloses a system comprising:
a memory array comprising (Fig. 3A where it illustrates memory array 212):
a plurality of word lines (Fig. 3A word lines 216a and 216b for example);
a plurality of bit lines intersecting the plurality of word lines at a plurality of cell locations (Fig. 3A bit lines 220a and 220b for example);
and a plurality of cells respectively located at the plurality of cell locations (Fig. 3A where it illustrates device 302 and 304 as comprising a 2T2R cell. See also col. 6, ln. 65-66; "operated in a dual mode as part of a pair of memory cells 302, 304");
wherein each cell of the plurality of cells in turn comprises: a first phase change memory device having a first drift; and a second phase change memory device having a second drift (Fig. 3A memory elements 312 and 314 of the pair 302,304. See also para. 11; " A memory device as described herein includes an array of programmable resistance memory cells such as phase change memory cells". Regarding the phase change memory device having a first /second drift, Lung’s pair inherently has a first (higher) drift on the partial-reset device and a second (lower) drift on the set device, as evidenced by Wimmer’s power-law for amorphous PCM (Wimmer p. 4; “the resistance drift effect in amorphous phase change materials is described by an empirically found power-law.”) See power-law formula above.);
wherein the first drift is higher than the second drift (para. 13; "In the dual mode a data value is stored in the pair by setting one of the memory cells in the pair to a lower resistance state and setting the resistance of the other memory cell to a higher resistance state". See also para. 14; “the higher resistance state for the dual mode can be a "partial reset" or "partial set" state”. As stated above, Wimmer’s power-law demonstrates the reset state (amorphous) is the high resistance state and exhibits pronounced resistance drift while the set state (crystalline) is the low resistance state and shows minimal to negligible drift.);
and a model control coupled to the word lines and an array program and read circuit coupled to the bit lines (para. 34; “A controller 234 implemented in this example, using a bias arrangement state machine, controls the application of bias arrangement supply voltages and current sources 236, to apply bias arrangements such read, program, erase, erase verify, program verify, and refresh to the memory cells of the array 212.”, “The controller 234 also provides control signals to the bit line decoder 218”, “and also provides control signals to block 224 to control the operation of the single and dual mode sense amplifiers during read operations.”. It is noted that under the broadest reasonable interpretation, controller + WL decoder = “model control” and BL decoder + program/sense block = “array program and read circuit”.),
wherein the model control and the array program and read circuit are cooperatively configured to cause:
the memory array to be programmed with a model including a plurality of zeroes and ones (Fig. 3A. See also col. 7, ln. 63-65; "The current through the memory cell 302 is dependent upon the resistance of the memory element 312 and thus the data value stored in the memory cell 302." It is well understood in the art that the data stored in memory cells is binary which is conventionally represented as zeros and ones),
wherein a first phase change memory device of the plurality of cells is programmed to logic one by programming the first phase change memory device to a near-reset resistance based at least in part on the first drift (para. 13; “the dual mode a data value is stored in the pair by setting one of the memory cells in the pair to a lower resistance state and setting the resistance of the other memory cell to a higher resistance state”. And see para. 14; “the higher resistance state for the dual mode can be a "partial reset" or "partial set" state”. It is noted that Lung’s programming the device to partial-reset is programing it to near-reset resistance based at least in part on the first drift. “Logic one” is merely a label for that programed resistance. Lung stores a value in the pair; the claim term does not require a different pulse or a different resistance than Lung’s partial-reset state.);
a second phase change memory device of the plurality of cells to be programmed to logic one by programming the second phase change memory device to a set resistance lower than the near-reset resistance (Id. and for the same reasons. It is noted that the dual-mode lower-resistance state is the set state. It is lower than the partial-reset / near-reset resistance of the first device (para. 14). Again, “Logic one” is merely a label. The second device is programmed to set; that is all the limitation requires beyond the label.);
Lung discloses a PCM 2T2R array programmed with set + partial-reset data values, but are silent with respect to carrying out inferencing with the array.
However, Le Gallo 1 teaches and the memory to carrying out inferencing (pg. 2, sect. I; "Each core contains a PCM crossbar array". See also pg. 2, intro. "The chip delivers simultaneously four key advances", "High MVM and inference accuracy are achieved". As noted in the rejection for indefiniteness above, the phrase "no more than a predetermined time period" will be interpreted to mean "some time period of any length".).
Lung along with Le Gallo 1 are from the same field of endeavor as applicant' s invention directed to using and improving emerging technology of PCM storage to study complex physical systems that process information. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lung’s PCM array with the teachings of Le Gallo 1' s inference and other DNN models to create an improved artificial intelligence system. Doing so would speed up complex computations that are difficult for traditional computers.
Regarding claim 17, Lung, as evidenced by Wimmer, and Le Gallo 1 combined disclose the limitations of claim 16.
As applied, Lung further discloses wherein each of the plurality of cells is electrically connected to a corresponding bit line and selectively grounded under control of a corresponding one of the word lines (Figs. 3A & 3B, See also para. 44 “In the illustrated embodiments the memory cells of the array 212 are coupled in a common collector configuration. In a common collector configuration”, “In FIGS. 3A and 3B the collector terminals are coupled to ground.”).
Claims 7, 12 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Lung (US 20110063902 – of record), as evidenced by Wimmer et al. ("Role of activation energy in resistance drift of amorphous phase change materials"; "Wimmer" – of record), in view of Le Gallo et al. ("A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference"; "Le Gallo 1" – of record), and further in view of Le Gallo et al. (US 20200381048; "Le Gallo 2" – of record)
Regarding claim 7, Lung, as evidenced by Wimmer, and Le Gallo 1 combined disclose the limitations of claim 6.
Lung and Le Gallo 1 are silent with respect to hyperdimensional models.
However, Le Gallo 2 teaches wherein the model control comprises a hyperdimensional (HD) encoding control (Absr. "The device comprises a resistive memory device for storing elements of hyper-dimensional vectors, in particular digital hyper-dimensional, as conductive statuses in components in particular in 2D-memristors". It is well understood in the art that the term digital means data represented by zeros and ones. It is further understood that the hyperdimensional (HD) model referred to in the instant application (para. 3 for example) is comprised of an array of hyperdimensional vectors.).
Lung and Le Gallo 1 combined, along with Le Gallo 2 are from the same field of endeavor as applicant' s invention directed to using and improving emerging technology of PCM storage to study complex physical systems that process information. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lung's PCM array with Le Gallo's inference operation within a hyperdimensional model to create an improved artificial intelligence system. Doing so would speed up complex computations that are difficult for traditional computers.
Regarding claim 12, Lung, as evidenced by Wimmer, and Le Gallo 1 combined disclose the limitations of claim 11.
Lung, and Le Gallo 1 are silent with respect to hyperdimensional models.
However, Le Gallo 2 teaches wherein, in the step of programming the phase change memory array with the model, the model comprises a hyperdimensional (HD) model (Absr. "The device comprises a resistive memory device for storing elements of hyper-dimensional vectors, in particular digital hyper-dimensional, as conductive statuses in components in particular in 2D-memristors". It is well understood in the art that the term digital means data represented by zeros and ones. It is further understood that the hyperdimensional (HD) model referred to in the instant application (para. 3 for example) is comprised of an array of hyperdimensional vectors.).
Lung, and Le Gallo 1 combined, along with Le Gallo 2 are from the same field of endeavor as applicant' s invention directed to using and improving emerging technology of PCM storage to study complex physical systems that process information. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lung's PCM array with Le Gallo's inference operation within a hyperdimensional model to create an improved artificial intelligence system. Doing so would speed up complex computations that are difficult for traditional computers.
Regarding claim 19, Lung, as evidenced by Wimmer, and Le Gallo 1, combined disclose the limitations of claim 17.
Lung, and Le Gallo 1 are silent with respect to hyperdimensional models.
As applied, Le Gallo 2 further discloses wherein the model comprises a hyperdimensional (HD) model (Absr. "The device comprises a resistive memory device for storing elements of hyper-dimensional vectors, in particular digital hyper-dimensional, as conductive statuses in components in particular in 2D-memristors". It is well understood in the art that the term digital means data represented by zeros and ones. It is further understood that the hyperdimensional (HD) model referred to in the instant application (para. 3 for example) is comprised of an array of hyperdimensional vectors.).
Lung, and Le Gallo 1 combined, along with Le Gallo 2 are from the same field of endeavor as applicant' s invention directed to using and improving emerging technology of PCM storage to study complex physical systems that process information. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lung's PCM array with Le Gallo's inference operation within a hyperdimensional model to create an improved artificial intelligence system. Doing so would speed up complex computations that are difficult for traditional computers.
Claims 8, 21, and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Lung (US 20110063902 – of record), as evidenced by Wimmer et al. ("Role of activation energy in resistance drift of amorphous phase change materials"; "Wimmer" – of record), in view of Le Gallo et al. ("A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference"; "Le Gallo 1” – of record), and further in view of Li et al (US 20220102626; "Li" – of record).
Regarding claim 8, Lung, as evidenced by Wimmer, and Le Gallo 1 combined disclose the limitations of claim 6.
Lung, as evidenced by Wimmer, and Le Gallo are silent with respect to the specific internal physical structure of the PCM cell.
However, Li teaches wherein the first phase change memory device and the second phase change memory device each include a top electrode, a bottom electrode, and phase change material (Fig. 2. See also para. 28; " the PCM 102 comprises a top electrode 201", "a phase change material 202/205 (e.g., GST)", "and bottom electrode 204").
Lung and Le Gallo 1 combined, along with Li are from the same field of endeavor as applicant' s invention directed to using and improving emerging technology of PCM storage to study complex physical systems that process information. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lung's PCM array using Li's internal physical structure along with Le Gallo's inference operation cells to create an improved artificial intelligence system. Doing so would speed up complex computations that are difficult for traditional computers.
Regarding claim 21 and 23, Lung, as evidenced by Wimmer, and Le Gallo 1 combined disclose the limitations of claim 11.
Lung discloses a differential PCM pair (Fig. 3B) where one cell may be a reference (para. 28; "For example, the collectors may be coupled to bias circuits such as voltage sources and current sources, and decoding circuits for applying bias arrangements to the collector terminals") but Lung and Le Gallo 1 are silent with respect to PCM cells with an explicit projection liner.
However, Li teaches wherein the first phase change memory device does not have a liner and wherein the second phase change memory device has a liner (Fig. 2: 203. See also para. 28; "PCM 102 comprises", "a conductive oxide liner material 203").
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the PCM pair of Lung by using one cell that has a projection liner instead of using one cell coupled to a current source. Choosing an obvious variant would merely be a matter of a routine engineering design choice for selecting a stable reference point within the differential pair, providing a predictable result.
Claims 14 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Lung (US 20110063902 – of record), as evidenced by Wimmer et al. ("Role of activation energy in resistance drift of amorphous phase change materials"; "Wimmer" – of record), and further in view of Le Gallo et al. ("A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference"; "Le Gallo 1” – of record), and further in view of Carissimi et al. (US 20220068380; "Carissimi" – of record).
Regarding claim 14, Lung, as evidenced by Wimmer, and Le Gallo 1 combined disclose the limitations of claim 11.
Lung, Wimmer and Le Gallo 1 also disclose using a PCM array in a device as neuromorphic processor elements but are silent with regard to its classification and use in a wider system.
However, Carissimi teaches further comprising locating the phase change memory array on an edge computing device (Fig. 1A where it illustrates memory device 100A comprised of memory cells 105. See also para. 39; "memory cells 105 comprise PCM (“Phase Change Memory”) memory cells". Further, see para. 9; "In-memory computing (IMC) is the storage and the computation of information in a random-access memory device (e.g. a random-access memory device of dedicated servers or of edge devices".)
that is coupled to a network (Fig. 4: 415. See also para. 104; "the electronic system 400 comprises a wireless interface 415 for exchanging messages with a wireless communication network (not shown)").
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the PCM chip of Lung, Wimmer and Le Gallo 1 into the network connected edge device of Carissimi to solve the "von Neumann bottleneck' and energy constraints inherent in edge computing devices. The PCM chip of Lung and Le Gallo 1 explicitly provides a low-power, high-speed and non-volatile data retention component required in edge computing devices thereby applying a known technique to a known device are naturally complimentary and would yield predictable results.
Regarding claim 18, Lung, as evidenced by Wimmer, and Le Gallo 1 combined disclose the limitations of claim 17.
Lung, and Le Gallo 1 also disclose using a PCM array in a device as neuromorphic processor elements but are silent with regard to its classification and use in a wider system.
However, Carissimi teaches further comprising a network (Fig. 4: 415. See also para. 104; "the electronic system 400 comprises a wireless interface 415 for exchanging messages with a wireless communication network (not shown)"),
wherein the memory array is located on an edge computing device that is coupled to the network (Fig. 1A where it illustrates memory device 100A comprised of memory cells 105. See also para. 39; "memory cells 105 comprise PCM (“Phase Change Memory”) memory cells". Further, see para. 9; "In-memory computing (IMC) is the storage and the computation of information in a random-access memory device (e.g. a random-access memory device of dedicated servers or of edge devices".).
Claims 22 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Lung (US 20110063902 – of record), as evidenced by Wimmer et al. ("Role of activation energy in resistance drift of amorphous phase change materials"; "Wimmer" – of record), in view of Le Gallo et al. ("A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference"; "Le Gallo 1” – of record), and further in view of Soeya et al. (US 20150144865; "Soeya" – of record).
Regarding claim 22 and 24, Lung, as evidenced by Wimmer, and Le Gallo 1 disclose the limitations of claims 11 and 16 respectively.
Lung discloses a differential PCM pair (Fig. 3B) where one cell may be a reference (para. 28; "For example, the collectors may be coupled to bias circuits such as voltage sources and current sources, and decoding circuits for applying bias arrangements to the collector terminals") but Lung and Le Gallo 1 are silent with respect to PCM cells with an explicit superlattice structure
However, Soeya teaches wherein the first phase change memory device includes GST phase change material and wherein the second phase change memory device includes superlattice phase change material (para. 4; "superlattice phase-change memory composed of GeTe(111)/Sb.sub.2Te.sub.3(001) superlattice film and called "interfacial Phase-Change Memory (iPCM)" has been suggested").
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the PCM pair of Lung with the inferencing of Le Gallo 1, by using one cell that has a superlattice instead of using one cell coupled to a current source. Choosing an obvious variant would merely be a matter of a routine engineering design choice for selecting a stable reference point within the differential pair, providing a predictable result.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Lung (US 20110063902 – of record), as evidenced by Wimmer et al. ("Role of activation energy in resistance drift of amorphous phase change materials"; "Wimmer" – of record), in view of Li et al (US 20220102626; "Li" – of record).
Regarding claim 2, Lung as evidenced by Wimmer discloses the limitations of claim 1.
Lung, as evidenced by Wimmer, discloses a differential PCM pair (Fig. 3B) where one cell may be a reference (para. 28; "For example, the collectors may be coupled to bias circuits such as voltage sources and current sources, and decoding circuits for applying bias arrangements to the collector terminals") but is silent with respect to PCM cells with an explicit projection liner.
However, Li teaches wherein the first phase change memory device does not have a liner and wherein the second phase change memory device has a liner (Fig. 2: 203. See also para. 28; "PCM 102 comprises", "a conductive oxide liner material 203").
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the PCM pair of Lung by using one cell that has a projection liner instead of using one cell coupled to a current source. Choosing an obvious variant would merely be a matter of a routine engineering design choice for selecting a stable reference point within the differential pair, providing a predictable result.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Lung (US 20110063902 – of record), as evidenced by Wimmer et al. ("Role of activation energy in resistance drift of amorphous phase change materials"; "Wimmer" – of record), in view of Soeya et al. (US 20150144865; "Soeya" – of record).
Regarding claim 3, Lung, as evidenced by Wimmer, discloses the limitations of Claim 1.
Lung discloses a differential PCM pair (Fig. 3B) where one cell may be a reference (para. 28; "For example, the collectors may be coupled to bias circuits such as voltage sources and current sources, and decoding circuits for applying bias arrangements to the collector terminals") but is silent with respect to PCM cells with an explicit superlattice structure
However, Soeya teaches wherein the first phase change memory device includes GST phase change material and wherein the second phase change memory device includes superlattice phase change material (para. 4; "superlattice phase-change memory composed of GeTe(111)/Sb.sub.2Te.sub.3(001) superlattice film and called "interfacial Phase-Change Memory (iPCM)" has been suggested").
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the PCM pair of Lung by using one cell that has a superlattice instead of using one cell coupled to a current source. Choosing an obvious variant would merely be a matter of a routine engineering design choice for selecting a stable reference point within the differential pair, providing a predictable result.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Lung (US 20110063902 – of record), as evidenced by Wimmer et al. ("Role of activation energy in resistance drift of amorphous phase change materials"; "Wimmer" – of record), in view of Carissimi et al. (US 20220068380; "Carissimi" – of record).
Regarding claim 10, Lung, as evidenced by Wimmer, disclose the limitations of claim 1.
Lung discloses using a PCM array in a device as neuromorphic processor elements but is silent with regard to its classification and use in a wider system.
However, Carissimi teaches further comprising a network (Fig. 4: 415. See also para. 104; "the electronic system 400 comprises a wireless interface 415 for exchanging messages with a wireless communication network (not shown)"),
wherein the memory array is located on an edge computing device that is coupled to the network (Fig. 1A where it illustrates memory device 100A comprised of memory cells 105. See also para. 39; "memory cells 105 comprise PCM (“Phase Change Memory”) memory cells". Further, see para. 9; "In-memory computing (IMC) is the storage and the computation of information in a random-access memory device (e.g. a random-access memory device of dedicated servers or of edge devices".).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the PCM chip of Lung into the network connected edge device of Carissimi to solve the "von Neumann bottleneck' and energy constraints inherent in edge computing devices. The PCM chip of Lung and Le Gallo 1 explicitly provides a low-power, high-speed and non-volatile data retention component required in edge computing devices thereby applying a known technique to a known device are naturally complimentary and would yield predictable results.
Response to Arguments
Applicant's arguments have been fully considered but they are not persuasive.
Applicant contends on pg. 10 of Remarks that the anticipation rejection of independent claim 1 is improper because Lung does not disclose programming the first device to logic one at a near-reset resistance based at least in part on the first drift, and programming the second device to logic one at a set resistance lower than that near-reset resistance.
As set forth in the rejection above, Lung programs one device of the pair to a dual-mode higher-resistance / “partial reset” state and the other to a lower-resistance (set) state. That is near-reset and set. The partial-reset device is the amorphous device of the pair and therefore the higher-drift device, as evidenced by Wimmer. “Logic one” is a label for those programmed resistances. It does not require a different pulse or a different resistance than Lung already applies.
Claim 1 remains rejected under § 102(a)(1) over Lung as evidenced by Wimmer. Wimmer is not a combining reference. It is cited as evidence of the inherent drift differential of Lung’s pair, which the amendment made express. That evidence was necessitated by the amendment and forms a new ground of rejection. MPEP § 706.07(a).
Applicant contends on pg. 11 of Remarks that the obviousness rejection for claim 11 is improper because the cited combination does not disclose the dual-device cell with unequal drift, or programming both devices to logic one at near-reset and set.
As set forth in the rejection above, the array, the pair, the unequal drift, and the two programmed resistances are Lung as evidenced by Wimmer, for the same reasons as claim 1. Wimmer is not combined. Le Gallo 1 is applied only to “carrying out inferencing,” which Lung does not teach. Applicant does not address that inferencing teaching or the reason to run Le Gallo 1 inference on Lung’s programmed array.
Claim 11 remains rejected under § 103 over Lung as evidenced by Wimmer, in view of Le Gallo 1.
Applicant contends on pg. 12 of Remarks that the obviousness rejection for claim 16 is improper based on the same assertion as claim 11 and cites Le Gallo 2 as part of the combination that fails.
Le Gallo 2 is not applied to claim 16. Claim 16 is rejected over Lung as evidenced by Wimmer, in view of Le Gallo 1, on the same map as claims 1 and 11: Lung supplies the system, the pair, and the two resistances; Le Gallo 1 supplies inferencing. Applicant’s argument does not address that application.
Applicant asserts patentability of the dependent claims solely from the parents and of new claims 21-24 solely from claims 11 and 16. The independents stand rejected, therefore all claims remain rejected.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/James S. Wells/Examiner, Art Unit 2825
/Alfredo Bermudez Lozada/Primary Examiner, Art Unit 2825
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