DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1–16 are rejected under 35 U.S.C. § 103 as being unpatentable over Sah et al. (U.S. 10,540,759 B2) in view of Sankar (WO2022225545 A1).
Regarding claim 1, Sah discloses a metrology system comprising:
a stage configured support a bonded wafer, wherein the bonded wafer has a top wafer disposed on a carrier wafer; and (Through Figs. 14–15, Sah discloses a stage 101 where a carrier wafer 107 and a top wafer 108 have different dimensions to form a bonded wafer 102. Sah col. 8 lines 14–21. [t]he carrier wafer 107 and top wafer 108 can both be device wafers or more than the carrier wafer 107 and top wafer 108 can form the bonded wafer 102.)
an imaging system configured to generate wafer edge profile images of a circumferential edge of the bonded wafer, (Per Fig. 14, Sah’s system 100 discloses a circumferential edge of a wafer 102. Ibid. col. 7 line 66 – col. 8 line 13. System 100 is configured to perform metrology of a bonded wafer by acquiring images that are shadowgrams. A shadowgram applies a shadowgraph technique and visualizes or images a shadow of the bonded wafer 102, such as a circumferential edge of the bonded wafer 102.) wherein the imaging system includes a light source configured to generate collimated light (Per Fig. 14, Sah discloses a light source 103 comprising a collimated light 104. Ibid. col. 8 lines 22–45. A light source 103 is configured to direct collimated light 104 at an edge of the bonded wafer 102.) and a detector configured to generate the wafer edge profile images; and (Per Fig. 14, Sah discloses a detector 105 is placed to generate wafer edge profile images. Ibid. col. 8 lines 46–63.)
a processor in electronic communication with the imaging system, wherein the processor is programmed to: (Fig. 15, a processor 109)
receive the wafer edge profile images; (Per Fig. 14, Sah’s detector 105 discloses myriad wafer edge profile images of the wafer 102. Ibid. col. 8 lines 46–63. The detector 105 can be configured to collect hundreds of wafer edge profile images of the bonded wafer 102 for high sampling.)
determine an offset between the top wafer and the carrier wafer. (Per Fig. 13 at step 202, Sah discloses a displacement between the top wafer and the carrier wafer in accordance with an offset curve. Ibid. col. 7 lines 24–33. At 202, displacement of the top wafer to the carrier wafer is determined based on the offset curve.)
However, Sah fails to specifically disclose convert the wafer edge profile images from black and white to greyscale; determine an edge of the bonded wafer in each of the wafer edge profile images based on bright pixels and dark pixels in the wafer edge profile images; and convert pixels of the edge in the wafer edge profile images to a dimension scale in a grid.
In related art, Sankar discloses convert the wafer edge profile images from black and white to greyscale; (Through Figs. 4A–4B, Sankar discloses binarizing edge profile image of the wafer. Sankar Spec. ¶28. Binarizing can convert the image to black and white from greyscale.)
determine an edge of the bonded wafer in each of the wafer edge profile images based on bright pixels and dark pixels1 in the wafer edge profile images; (Per Fig. 1, Sankar discloses extracting pixels from the edge profile image. Ibid. ⁋32. [e]xtracting pixels from the profile image that are a distance beyond an edge of the distance transform image thereby generating an extracted track;)
convert pixels of the edge in the wafer edge profile images to a dimension scale in a grid. (Per Fig. 6A, Sankar discloses a one-dimensional average filter where related pixels from the edge are extracted applying distance transform. Ibid. ¶34. A one-dimensional average filter can be applied on the extracted track.)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Sankar into the teachings of Sah to avoid dissimilar reference image analyzing a potential defective image. Ibid. ¶39.
Regarding claim 6, Sah discloses a method comprising:
receiving the wafer edge profile images; (Per Fig. 14, Sah’s detector 105 discloses myriad wafer edge profile images of the wafer 102. Ibid. col. 8 lines 46–63. The detector 105 can be configured to collect hundreds of wafer edge profile images of the bonded wafer 102 for high sampling.)
determining an offset between the top wafer and the carrier wafer. (Per Fig. 13 at step 202, Sah discloses a displacement between the top wafer and the carrier wafer in accordance with an offset curve. Ibid. col. 7 lines 24–33. At 202, displacement of the top wafer to the carrier wafer is determined based on the offset curve.)
However, Sah fails to specifically disclose converting the wafer edge profile images from black and white to greyscale; determining an edge of the bonded wafer in each of the wafer edge profile images based on bright pixels and dark pixels in the wafer edge profile images; and converting pixels of the edge in the wafer edge profile images to a dimension scale in a grid.
In related art, Sankar discloses converting the wafer edge profile images from black and white to greyscale; (Through Figs. 4A–4B, Sankar discloses binarizing edge profile image of the wafer. Sankar Spec. ¶28. Binarizing can convert the image to black and white from greyscale.)
determining an edge of the bonded wafer in each of the wafer edge profile images based on bright pixels and dark pixels in the wafer edge profile images; (Per Fig. 1, Sankar discloses extracting pixels from the edge profile image. Ibid. ⁋32. [e]xtracting pixels from the profile image that are a distance beyond an edge of the distance transform image thereby generating an extracted track;)
converting pixels of the edge in the wafer edge profile images to a dimension scale in a grid. (Per Fig. 6A, Sankar discloses a one-dimensional average filter where related pixels from the edge are extracted applying distance transform. Ibid. ¶34. A one-dimensional average filter can be applied on the extracted track.)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Sankar into the teachings of Sah to avoid dissimilar reference image analyzing a potential defective image. Ibid. ¶39.
Regarding claim 12, Sah discloses a non-transitory computer-readable storage medium, comprising one or more programs for executing the following steps on one or more computing devices:
receive the wafer edge profile images; (Per Fig. 14, Sah’s detector 105 discloses myriad wafer edge profile images of the wafer 102. Ibid. col. 8 lines 46–63. The detector 105 can be configured to collect hundreds of wafer edge profile images of the bonded wafer 102 for high sampling.)
determine an offset between the top wafer and the carrier wafer. (Per Fig. 13 at step 202, Sah discloses a displacement between the top wafer and the carrier wafer in accordance with an offset curve. Ibid. col. 7 lines 24–33. At 202, displacement of the top wafer to the carrier wafer is determined based on the offset curve.)
However, Sah fails to specifically disclose convert the wafer edge profile images from black and white to greyscale; determine an edge of the bonded wafer in each of the wafer edge profile images based on bright pixels and dark pixels in the wafer edge profile images; and convert pixels of the edge in the wafer edge profile images to a dimension scale in a grid.
In related art, Sankar discloses convert the wafer edge profile images from black and white to greyscale; (Through Figs. 4A–4B, Sankar discloses binarizing edge profile image of the wafer. Sankar Spec. ¶28. Binarizing can convert the image to black and white from greyscale.)
determine an edge of the bonded wafer in each of the wafer edge profile images based on bright pixels and dark pixels in the wafer edge profile images; (Per Fig. 1, Sankar discloses extracting pixels from the edge profile image. Ibid. ⁋32. [e]xtracting pixels from the profile image that are a distance beyond an edge of the distance transform image thereby generating an extracted track;)
convert pixels of the edge in the wafer edge profile images to a dimension scale in a grid. (Per Fig. 6A, Sankar discloses a one-dimensional average filter where related pixels from the edge are extracted applying distance transform. Ibid. ¶34. A one-dimensional average filter can be applied on the extracted track.)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Sankar into the teachings of Sah to avoid dissimilar reference image analyzing a potential defective image. Ibid. ¶39.
Regarding claim 2, Sah as modified by Sankar, discloses the metrology system, wherein the wafer edge profile images received by the processor are shadowgram images. (Per Fig. 13, Sah discloses that the wafer profile images are shadowgram images. Sah col. 7 lines 24–33. The wafer edge profile images may be shadowgram images.)
Regarding claim 3, Sah as modified by Sankar, discloses the metrology, wherein the processor is further configured to crop the wafer edge profile images prior to determining the boundary. (Per Fig. 2, Sah discloses a contour to extract the profile image cropping the image. Sah col. 4 lines 60–67. Scale bars may be removed by, for example, cropping the image.)
Regarding claim 4, Sah as modified by Sankar, discloses the metrology system, wherein the grid is a spreadsheet. (Through Figs. 4A–4B, Sah discloses an offset curve on a graph. Sah col. 5 lines 32–49. [a]ll wafer edge profile images (e.g., every 10 degrees around the circumference of the bonded wafer) and an offset curve is generated.)
Regarding claim 5, Sah as modified by Sankar, discloses the metrology system, wherein the wafer edge profile images include from 20 to 30 of the wafer profile images for the bonded wafer. (Per Fig. 14, Sah’s detector 105 discloses myriad wafer edge profile images of the wafer 102. Sah col. 8 lines 46–63. The detector 105 can be configured to collect hundreds of wafer edge profile images of the bonded wafer 102 for high sampling.)
Regarding claim 11, Sah as modified by Sankar, discloses the method, further comprising imaging a circumferential edge of the bonded wafer using an imaging system to generate the wafer edge profile images, wherein the imaging system includes a light source configured to generate collimated light (Per Fig. 14, Sah discloses a light source 103 comprising a collimated light 104. Sah col. 8 lines 22–45. A light source 103 is configured to direct collimated light 104 at an edge of the bonded wafer 102.) and a detector configured to generate the wafer edge profile images. (Per Fig. 14, Sah discloses a detector 105 is placed to generate wafer edge profile images. Ibid. col. 8 lines 46–63.)
Regarding claim 7, it has been rejected in the same manner as claim 2.
Regarding claim 8, it has been rejected in the same manner as claim 3.
Regarding claim 9, it has been rejected in the same manner as claim 4.
Regarding claim 10, it has been rejected in the same manner as claim 5.
Regarding claim 13, it has been rejected in the same manner as claim 2.
Regarding claim 14, it has been rejected in the same manner as claim 3.
Regarding claim 15, it has been rejected in the same manner as claim 4.
Regarding claim 16, it has been rejected in the same manner as claim 5.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
McLaurin et al. (U.S. 11,710,944 B2) discloses a multi-wavelength light emitting device.
Contact
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENEDICT LEE whose telephone number is (571)270-0390. The examiner can normally be reached 10:00-16:00 (EST).
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/BENEDICT E LEE/Examiner, Art Unit 2665
/Stephen R Koziol/Supervisory Patent Examiner, Art Unit 2665
1 Examiner construes that bright pixels and dark pixels as greyscale.
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