DETAILED ACTION
Status of Application
Claims 1-20 are pending in the present application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/12/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 10, and 19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 2, 10, and 15, respectively, of U.S. Patent No. 12099848 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because every claim limitation in the application under examination is recited in the conflicting reference patent claims. The differences between the claims are highlighted below by italicizing all limitations that differ and bolding limitations that conflict.
Please note that in the interest of time, the examiner is selecting only one of the independent claims from the instant application and U.S. Patent for the table below.
Instant Application
U.S. Patent No. 12099848 B2
1. A method comprising:
receiving, by a first processor, a multi-dimensional data structure and an operation to be performed on at least a first element of the multi-dimensional data structure;
generating, by the first processor and using at least one of template metaprogramming or operator overloading, one or more operators to perform the operation on at least the first element of the multi-dimensional data structure; and
generating, by the first processor, a kernel that comprises the one or more operators, wherein the kernel is executable by a second processor.
1. A method comprising:
receiving, by a first processor of a computer system, one or more operations for a kernel;
automatically generating, by the first processor, one or more operators that perform the one or more operations on one or more elements of one or more tensors using at least one of template metaprogramming or operator overloading for defining the one or more operators, wherein using operator overloading for defining the one or more operators comprises performing the one or more operators on each element of the one or more tensors, and wherein using template metaprogramming for defining the one or more operators comprises constructing a sequence of operators on the one or more tensors; and
automatically generating, by the first processor, the kernel that comprises the one or more operators.
2. The method of claim 1, further comprising:
transmitting the kernel to a second processor of the computer system; and executing, by the second processor, the kernel to execute the one or more operators and perform the one or more operations on the one or more elements of the one or more tensors.
Claims 2, 11, and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 2, 10, and 15, respectively, of U.S. Patent No. 12099848 B2.
Claims 3 and 12 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 2 and 10, respectively, of U.S. Patent No. 12099848 B2.
Claims 4 and 13 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 2 and 10, respectively, of U.S. Patent No. 12099848 B2.
Claims 5 and 14 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 2 and 10, respectively, of U.S. Patent No. 12099848 B2.
Claims 6 and 15 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 3 and 11, respectively, of U.S. Patent No. 12099848 B2.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-7, 10, 12-16, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bebee et al (hereinafter Bebee), US 10409560 B1, in view of "C++ meta-programming: overloading of arithmetic operators for types” (hereinafter C++ meta-programming).
Referring to claim 1, Bebee discloses a method comprising:
receiving, by a first processor, a multi-dimensional data structure and an operation to be performed on at least a first element of the multi-dimensional data structure structures [fig. 6, col. 14, lines 2-7, examples of operators for which hardware-platform-specific kernels may be generated for graph algorithms, according to at least some embodiments. A supported operator set 620 may include, among others, vector operators 632, matrix operators 634, and matrix-vector operators 634 in the depicted embodiment; col. 14, lines 57-60, “For example, with respect to architecture A1, CUDA-based kernels 642 may be generated—kernels 642A for vector operators, kernels 643A for matrix operators, and kernels 644A for matrix-vector operators in one embodiment”; hence a processor would receive the generated compute kernel with the generated operator set (see fig. 6), for operation on an element of a multidimensional matrix];
generating, by the first processor one or more operators to perform the operation on at least the first element of the multi-dimensional data structure [fig. 6, col. 14, lines 2-7, examples of operators for which hardware-platform-specific kernels may be generated for graph algorithms, according to at least some embodiments. A supported operator set 620 may include, among others, vector operators 632, matrix operators 634, and matrix-vector operators 634 in the depicted embodiment (the examiner notes that a matrix is a multidimensional data structure and that matrix operators and matrix-vector operators would operate on an element of a matrix (multi-dimensional data structure)); col. 14, lines 57-60, “For example, with respect to architecture A1, CUDA-based kernels 642 may be generated—kernels 642A for vector operators, kernels 643A for matrix operators, and kernels 644A for matrix-vector operators in one embodiment”; operators may be generated and thereafter, a kernel will be generated with the generated operator set (see fig. 6), for operation on an element of a multidimensional matrix]; and
generating, by the first processor, a kernel that comprises the one or more operators [fig. 7, col. 14, line 1 – col. 16, line 40, “FIG. 6 illustrates examples of operators for which hardware-platform-specific kernels may be generated for graph algorithms, according to at least some embodiments”; “Corresponding to each of the operators of set 620, in one embodiment respective tuned compute kernels may be generated for each hardware/software architecture at which the graph analysis computations are expected to be performed”; in one embodiment source code of a graph analysis program and an indication of an input graph data set which is to be analyzed (which may be included in the source code, or supplied as a parameter of the program) may be obtained; “The source code may be parsed, and an abstract syntax tree may be generated”; “From the abstract syntax tree (either the original tree or an optimized version), in one embodiment a dependency graph of tasks may be generated (element 710). In one embodiment, individual nodes or tasks of the graph may comprise potentially parallelizable operators, such as vector, matrix or matrix-vector operators”; “At least one executable representation of the program, comprising compute kernels optimized/tuned for the selected execution platform may be generated in the depicted embodiment (element 719)”], wherein the kernel is executable by a second processor [col. 4, lines 23-38, “In one embodiment, a distributed platform such as a multi-node cluster, with each node equipped with one or more CPUs and/or GPUs, may be used”; “Any of a number of different approaches towards inter-node communication may be employed in various embodiments”; col. 10, lines 20-21, “In one embodiment the executable representation may then be run at the selected parallel programming platform”; figs. 6; fig. 7 steps 719, 722].
Bebee does not explicitly disclose the generating one or more operators using at least one of template metaprogramming or operator overloading.
However, C++ meta-programming discloses the generating one or more operators using at least one of template metaprogramming or operator overloading [pp. 1-2, the examiner notes that page 1 poses the question of overloading the operator /. The answer to the question is on page 2 where sections of code pertain to “each operator you want to handle”; also see the title on page 1: “C++ meta-programming: overloading of arithmetic operators for types, and;
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of C++ meta-programming in the method of Bebee to implement, the generating one or more operators using at least one of template metaprogramming or operator overloading, in order to allow the code to become more readable [C++ meta-programming, p. 1].
Referring to claim 3 and 12, taking claim 3 as exemplary, the modified Bebee discloses the method of claim 1, wherein the generating the one or more operators comprises generating the one or more operators using operator overloading, the operator overloading including performing the one or more operators on at least the first element of the multi- dimensional data structure [C++ meta-programming, pp. 1-2; Bebee, fig. 6, col. 14, lines 2-7, examples of operators for which hardware-platform-specific kernels may be generated for graph algorithms, according to at least some embodiments. A supported operator set 620 may include, among others, vector operators 632, matrix operators 634, and matrix-vector operators 634 in the depicted embodiment (the examiner notes that a matrix is a multidimensional data structure and that matrix operators and matrix-vector operators would operate on at least a first element of a matrix (multi-dimensional data structure)); col. 14, lines 57-60, “For example, with respect to architecture A1, CUDA-based kernels 642 may be generated—kernels 642A for vector operators, kernels 643A for matrix operators, and kernels 644A for matrix-vector operators in one embodiment”; operators may be generated and thereafter, a kernel will be generated with the generated operator set (see fig. 6), for operation on an element of a multidimensional matrix].
Referring to claim 4 and 13, taking claim 4 as exemplary, the modified Bebee discloses the method of claim 3, wherein the multi-dimensional data structure further comprises one or more additional elements, and wherein the generating the one or more operators using operator overloading further comprises performing the one or more operators on the one or more additional elements of the multi-dimensional data structure [C++ meta-programming, pp. 1-2; Bebee, fig. 6, col. 14, lines 2-7, examples of operators for which hardware-platform-specific kernels may be generated for graph algorithms, according to at least some embodiments. A supported operator set 620 may include, among others, vector operators 632, matrix operators 634, and matrix-vector operators 634 in the depicted embodiment (the examiner notes that a matrix comprising a vector has more than one element, hence operating on one or more additional elements of the matrix). In addition, it has been held that “that mere duplication of parts has no patentable significance unless a new and unexpected result is produced” [MPEP 2144.04, VI., B.] Hence, performing the one or more operators on an additional element is an obvious variant since it is merely duplicating an already known operator on an additional element as opposed to an operator on a single element)].
Referring to claim 5 and 14, taking claim 5 as exemplary, the modified Bebee discloses the method of claim 1, further comprising:
transmitting the kernel to the second processor [Bebee, col. 4, lines 23-38, “In one embodiment, a distributed platform such as a multi-node cluster, with each node equipped with one or more CPUs and/or GPUs, may be used”; “Any of a number of different approaches towards inter-node communication may be employed in various embodiments”; col. 10, lines 20-21, “In one embodiment the executable representation may then be run at the selected parallel programming platform”; fig. 7]; and
executing, by the second processor, the kernel to execute the one or more operators and perform the operation on at least the first element of the multi-dimensional data structure [Bebee, col. 4, lines 23-38, “In one embodiment, a distributed platform such as a multi-node cluster, with each node equipped with one or more CPUs and/or GPUs, may be used”; “Any of a number of different approaches towards inter-node communication may be employed in various embodiments”; col. 10, lines 20-21, “In one embodiment the executable representation may then be run at the selected parallel programming platform”; fig. 7].
Referring to claim 6 and 15, taking claim 6 as exemplary, the modified Bebee discloses the method of claim 1, wherein the first processor comprises a central processing unit (CPU) and the second processor comprises a graphical processing unit (GPU) [Bebee, col. 2, lines 54-56; fig. 9].
Referring to claim 7 and 16, taking claim 7 as exemplary, the modified Bebee discloses the method of claim 1, wherein the first processor and the second processor are components of a first computer system, the method further comprising:
executing an application comprising the kernel [Bebee, fig. 7, step 719] by a first processor of a second computer system [Bebee, col. 4, lines 23-38, “In one embodiment, a distributed platform such as a multi-node cluster, with each node equipped with one or more CPUs and/or GPUs, may be used”; “Any of a number of different approaches towards inter-node communication may be employed in various embodiments”; fig. 9];
transmitting the kernel to a second processor of the second computer system [Bebee, col. 4, lines 23-38, “In one embodiment, a distributed platform such as a multi- node cluster, with each node equipped with one or more CPUs and/or GPUs, may be used”; “Any of a number of different approaches towards inter-node communication may be employed in various embodiments’; fig. 9]; and
executing, by the second processor of the second computer system, the kernel to execute the one or more operators and perform the operation on at least the first element of the multi- dimensional data structure [Bebee, fig. 7, step 722].
Referring to claims 10 and 19, taking claim 10 as exemplary, Bebee discloses a system comprising:
a memory device [fig. 9, element 9020]; and
one or more processors [col. 4, lines 23-38, “In one embodiment, a distributed platform such as a multi-node cluster, with each node equipped with one or more CPUs and/or GPUs, may be used”; “Any of a number of different approaches towards inter-node communication may be employed in various embodiments”] to:
receive, by a first processor of the one or more processors, a multi-dimensional data structure and an operation to be performed on at least a first element of the multi-dimensional data structure [fig. 6, col. 14, lines 2-7, examples of operators for which hardware-platform-specific kernels may be generated for graph algorithms, according to at least some embodiments. A supported operator set 620 may include, among others, vector operators 632, matrix operators 634, and matrix-vector operators 634 in the depicted embodiment; col. 14, lines 57-60, “For example, with respect to architecture A1, CUDA-based kernels 642 may be generated—kernels 642A for vector operators, kernels 643A for matrix operators, and kernels 644A for matrix-vector operators in one embodiment”; hence a processor would receive the generated compute kernel with the generated operator set (see fig. 6), for operation on an element of a multidimensional matrix];
generate, by the first processor, one or more operators to perform the operation on at least the first element of the multi-dimensional data structure [fig. 6, col. 14, lines 2-7, examples of operators for which hardware-platform-specific kernels may be generated for graph algorithms, according to at least some embodiments. A supported operator set 620 may include, among others, vector operators 632, matrix operators 634, and matrix-vector operators 634 in the depicted embodiment; col. 14, lines 57-60, “For example, with respect to architecture A1, CUDA-based kernels 642 may be generated—kernels 642A for vector operators, kernels 643A for matrix operators, and kernels 644A for matrix-vector operators in one embodiment”; operators may be generated and thereafter, a kernel will be generated with the generated operator set (see fig. 6), for operation on an element of a multidimensional matrix]; and
generate, by the first processor, a kernel that comprises the one or more operators [fig. 7, col. 14, line 1 – col. 16, line 40, “FIG. 6 illustrates examples of operators for which hardware-platform-specific kernels may be generated for graph algorithms, according to at least some embodiments”; “Corresponding to each of the operators of set 620, in one embodiment respective tuned compute kernels may be generated for each hardware/software architecture at which the graph analysis computations are expected to be performed”; in one embodiment source code of a graph analysis program and an indication of an input graph data set which is to be analyzed (which may be included in the source code, or supplied as a parameter of the program) may be obtained; “The source code may be parsed, and an abstract syntax tree may be generated”; “From the abstract syntax tree (either the original tree or an optimized version), in one embodiment a dependency graph of tasks may be generated (element 710). In one embodiment, individual nodes or tasks of the graph may comprise potentially parallelizable operators, such as vector, matrix or matrix-vector operators”; “At least one executable representation of the program, comprising compute kernels optimized/tuned for the selected execution platform may be generated in the depicted embodiment (element 719)”], wherein the kernel is executable by a second processor [col. 4, lines 23-38, “In one embodiment, a distributed platform such as a multi-node cluster, with each node equipped with one or more CPUs and/or GPUs, may be used”; “Any of a number of different approaches towards inter-node communication may be employed in various embodiments”; col. 10, lines 20-21, “In one embodiment the executable representation may then be run at the selected parallel programming platform”].
Bebee does not explicitly disclose the generating using at least one of template metaprogramming or operator overloading.
However, C++ meta-programming discloses generating using at least one of template metaprogramming or operator overloading [pp. 1-2, the examiner notes that page 1 poses the question of overloading the operator /. The answer to the question is on page 2 where sections of code pertain to “each operator you want to handle”; also see the title on page 1: “C++ meta-programming: overloading of arithmetic operators for types, and;
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of C++ meta-programming in the system of Bebee to implement, the generating using at least one of template metaprogramming or operator overloading, in order to allow the code to become more readable [C++ meta-programming, p. 1].
Claim(s) 8-9 and 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bebee, in view of C++ meta-programming, as applied to claims 1 and 10 above, and further in view of Andersen et al (hereinafter Andersen), US 20080209394 A1.
Referring to claims 8 and 17, taking claim 8 as exemplary, the modified Bebee does not explicitly disclose the method of claim 1, wherein the operation comprises one or more variables having unspecified data types, the method further comprising determining a data type for the one or more variables.
However, Andersen discloses wherein the operation comprises one or more variables having unspecified data types, the method further comprising determining a data type for the one or more variables [paragraph 1, “In dynamically typed languages, a variable can be used without specifying what data type it represents (i.e. without declaring a data type). At runtime, the system determines what data type the variable represents”].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Andersen in the method of the modified Bebee to implement, wherein the operation comprises one or more variables having unspecified data types, the method further comprising determining a data type for the one or more variables, in order to use a variable without specifying what data type it represents, thereby making the programming less complex for the programmer [Andersen, paragraph 1].
Referring to claims 9 and 18, taking claim 9 as exemplary, the modified Bebee discloses the method of claim 8, wherein the operation comprises one or more mathematical expressions represented in a single function [Bebee, fig. 3, col. 3, lines 48-52, The nodes of the AST may comprise, for example, the linear algebra primitives used in the algorithm, user defined functions, assignment operators, variables to which values are being assigned, and the like], and wherein the kernel comprises a plurality of lines of code that implement the one or more mathematical expressions on the data type [Bebee, fig. 7, steps 710, 719, 722; col. 16, lines 34-40].
Allowable Subject Matter
Claims 2, 11, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if the double patenting rejection is overcome AND if rewritten in independent form including all of the limitations of the base claim and any intervening claims
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record taken alone or in combination fails to teach and/or fairly suggest wherein the generating the one or more operators comprises generating the one or more operators using template metaprogramming, the template metaprogramming including constructing a sequence of operators on the multi-dimensional data structure, in combination with other recited limitations in claim 2.
The prior art of record taken alone or in combination fails to teach and/or fairly suggest wherein to generate the one or more operators, the one or more processors are to generate the one or more operators using template metaprogramming, the template metaprogramming including constructing a sequence of operators on the multi- dimensional data structure, in combination with other recited limitations in claim 11.
The prior art of record taken alone or in combination fails to teach and/or fairly suggest wherein to generate the one or more operators, the one or more processors are to generate the one or more operators using template metaprogramming, the template metaprogramming including constructing a sequence of operators on the multi- dimensional data structure, in combination with other recited limitations in claim 20.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Papakipos et al, US 20120144162 A1, discloses preparing compute kernels for an application in a parallel-processing computer system includes: a front end that is configured to receive one or more operation requests directed to a parallel-processing computer system that includes one or more types of processing elements; a compiler scheduler that is configured to dynamically select at least one of the one or more types of processing elements for at least one of the one or more operation requests; and a program generator that is configured to dynamically prepare one or more compute kernels for at least one of the one or more operation requests, wherein the one or more compute kernels are configured to execute on the selected type or types of processing elements [paragraph 27].
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FARLEY J ABAD whose telephone number is (571)270-3425. The examiner can normally be reached Mon-Fri 8:30 AM - 7 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached at (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Farley Abad/ Primary Examiner, Art Unit 2181
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