DETAILED ACTION
Examiner’s Note
The examiner has cited particular passages including column and line numbers, paragraphs as designated numerically and/or figures as designated numerically in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claims, other passages, paragraphs and figures of any and all cited prior art references may apply as well. It is respectfully requested from the applicant, in preparing an eventual response, to fully consider the context of the passages, paragraphs and figures as taught by the prior art and/or cited by the examiner while including in such consideration the cited prior art references in their entirety as potentially teaching all or part of the claimed invention. MPEP 2141.02 VI: “PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS." MPEP 2123 (I): “PATENTS ARE RELEVANT AS PRIOR ART FOR ALL THEY CONTAIN.”
Additionally, in an effort to provide a timely Office response to amendments the Applicant may file in response to this Office Action, it is respectfully requested that, on accompanying remarks/arguments papers, every effort be made to provide specific (page No., paragraph No., FIG. No., etc.) Specification/Drawings support for such amendments, particularly claim amendments.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim(s) 1 is objected to because of the following informalities: the claim includes XaY’bSec, X≠Y. The second Y does not have a corresponding punctuation mark apostrophe. Appropriate correction is required.
Allowable Subject Matter
Claim(s) 6 and 18 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the pertinent prior art of record does not teach or suggest the whole of the claimed limitations, in complete combination with the base claim and any and all intervening claim limitations: wherein a width of a space charge region in the memory layer due to a reset operation of the memory cell is greater than or equal to 2 nm; while in regard to claim 18, the pertinent prior art of record does not teach or suggest the whole of the claimed limitations, in complete combination with the base claim and any and all intervening claim limitations: further comprising: a plurality of word planes that extend along a plane including the first direction and the second direction, the plurality of word planes being spaced apart from each other in the third direction; a vertical bit line passing through the plurality of word planes and extending in the third direction; and a memory cell string extending in the third direction while surrounding the vertical bit line, wherein one memory cell is defined by a corresponding one of the plurality of word planes surrounding a portion of the memory cell string surrounding a portion of the vertical bit line.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 7-15 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent/Publication No. 20220246847 to Nugent et al. (“Nugent”) in view of U.S. Patent/Publication No. 8982604 to Lee et al. (“Lee”).
As to claim 1, Nugent teaches substantially the claimed invention, including: A chalcogenide-based memory material comprising: a ternary semiconductor compound having a composition represented by XaY’bSec (As found in at least FIG. 7 and at least [0058], [0086] and [0087]), wherein the chalcogenide-based memory material has an ovonic threshold-switching (OTS) characteristic (As found in at least [0059]), a threshold voltage of the chalcogenide-based memory material changes according to a polarity and an intensity of an applied voltage (As found in at least [0063-9964]).
Nugent may not expressly teach that XaY’bSec, X≠Y, a+b+c=1, a>0.12, b>0.18, c≥0.4, and X and Y’ are independently different ones of In, Sb, Ga, Sn, Al, Ge, Si, and P.
However, relevantly and complementarily, in the relevant art of chalcogenide memory, Lee teaches XaY’bSec, X≠Y, a+b+c=1, a>0.12, b>0.18, c≥0.4, and X and Y’ are independently different ones of In, Sb, Ga, Sn, Al, Ge, Si, and P (As found in at least claims 5-6).
Nugent and Lee are analogous art because they are from the same field of endeavor, and/or are reasonably pertinent to the inventor’s problem to be solved: chalcogenide memory devices that may include a ternary chemical compound.
At the time of invention, it would have been obvious to a person of ordinary skill in the art to complement the teachings of Nugent as set forth in this Office action and as found in the reference with the relevant and complementary teachings of Lee also as set forth in this Office action and as found in the reference(s). The suggestion/motivation would have been obvious to one of ordinary skill in the art before the effective filing date of the present Application: it would have been obvious, without having to resort to any inventive skill or undue experimentation, to include the particular compound composition of the ternary semiconductor compound in the chalcogenide memory.
Therefore, it would have been obvious to combine Nugent with Lee to make the above modification.
As to claim 2, Lee teaches wherein a concentration of X is greater than 12 at% and less than or equal to 40 at% in the ternary semiconductor compound (As found in at least claims 5-6).
As to claim 3, wherein a concentration of Y’ is greater than 18 at% and less than or equal to 40 at% in the ternary semiconductor compound (As found in at least claims 5-6).
As to claim 4, wherein a concentration of Se is greater than or equal to 40 at% and less than 75 at% in the ternary semiconductor compound (As found in at least claims 5-6).
As to claim 5, see rejection to at least claim 1; moreover, at least Nugent in at least FIG. 3 provides evidence of each of the plurality of memory cells includes a first electrode and a second electrode spaced apart from each other and facing each other, and a memory layer between the first electrode and the second electrode (first and second electrodes 308 and 310, and memory layer 302 between them); relevantly, Lee teaches in at least FIG. 6 similar electrode-memory arrangement: 101 between 105 and 103; such Lee arrangement within an array of memory cells 510, as in FIG. 10.
As to claim 7, see rejection to at least claim 2.
As to claim 8, see rejection to at least claim 3.
As to claim 9, see rejection to at least claim 4.
As to claim 10, Nugent teaches a first state of the memory layer has a first threshold voltage, a second state of the memory layer has a second threshold voltage, and the second threshold voltage is greater than the first threshold voltage (As found in at least [0068]).
As to claim 11-12, Nugent teaches when the memory layer is in the first state, the memory layer converts from the first state to the second state in response to applying a negative bias voltage to the memory layer so that a current flows from the first electrode to the second electrode; when the memory layer is in the second state, the memory layer converts from the second state into the first state in response to applying a positive bias voltage that is greater than or equal to the second threshold voltage to the memory layer so that a current flows from the second electrode to the first electrode. (As found in at least [0065]).
As to claim 13, Nugent teaches wherein a read voltage between the first threshold voltage and the second threshold voltage is applied to the memory layer in a read operation (As found in at least [0068]).
As to claim 14, Nugent teaches wherein the memory device has a three-dimensional cross point structure (As found in at least [0001], [0005], [0014]).
As to claim 15, Nugent teaches a plurality of bit lines extending in a first direction; and a plurality of word lines extending in a second direction, the second direction crossing the first direction, wherein the plurality of memory cells are respectively provided at points where the plurality of bit lines and the plurality of word lines cross each other (As found in at least FIG. 2: WL 215, BL 217 and cells 207 at cross points).
As to claim 19, Nugent teaches An electronic apparatus comprising: the memory device (As found in at least FIG. 1: 100).
Claim(s) 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent/Publication No. 20220246847 to Nugent et al. (“Nugent”) in view of U.S. Patent/Publication No. 8982604 to Lee et al. (“Lee”), and further in view of US 20240176740 to Simmadhari et al. (“Simma”).
As to claim 16, while at least Nugent teaches the memory device has a 3D crosspoint structure, with one axis of such 3D being in the vertical (V) direction, Nugent as modified may not expressly teach the memory device has a VNAND structure, where V is merely indicative of Vertical;
Yet, Simma teaches memory device has a VNAND structure (As found in at least [0027]: Three dimensional (3D, including vertical direction) NAND chalcogenide memory).
Nugent as modified and Simma are analogous art because they are from the same field of endeavor, and/or are reasonably pertinent to the inventor’s problem to be solved: chalcogenide memory devices that may include a ternary chemical compound within a 3D memory.
At the time of invention, it would have been obvious to a person of ordinary skill in the art to complement the teachings of Nugent as modified as set forth in this Office action and as found in the reference with the relevant and complementary teachings of Simma also as set forth in this Office action and as found in the reference(s). The suggestion/motivation would have been obvious to one of ordinary skill in the art before the effective filing date of the present Application: at least Nugent teaches a 3D cross point chalcogenide memory; this is non-volatile memory, and this type of memory can be arranged, as well-known in the art, into a NAND structure.
Therefore, it would have been obvious to combine Nugent as modified with Simma to make the above modification.
As to claim 17, Nugent teaches the plurality of memory cells are arranged in a third direction, and the third direction is perpendicular to a plane including the first direction and the second direction (As found in at least FIG. 2, word lines and bit lines are arranged in a plane, while as found in at least FIG. 4 memory cells are arranged vertically, perpendicular to the plane).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO N HIDALGO whose telephone number is (571)270-3306. The examiner can normally be reached M-F 9:00-7:30 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 5712721852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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FERNANDO N. HIDALGO
Primary Examiner
Art Unit 2827
/Fernando Hidalgo/Primary Examiner, Art Unit 2827