DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 and 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Patent No. 6,383,858 to Gupta et al. (hereinafter Gupta).
With respect to claim 1, Gupta discloses a method (e.g., forming interdigitated capacitor structure) (Gupta, Figs. 2A-2B, 4, 4A-4C, Col. 1, lines 58-67; Col. 2, lines 1-52; Cols. 4-5), comprising:
depositing a metal layer (420a) (Gupta, Fig. 4B, Col. 5, lines 15-19),
etching the metal layer (420a) (Gupta, Figs. 4, 4C, Col. 2, lines 45-50; Col. 5, lines 31-34) into at least a first structure (e.g., an electrode element 110) and a second structure (e.g., an electrode element 120), wherein the first and second structures are distinct from each other; and
depositing a non-conductive layer (e.g., dielectric layer 430) (Gupta, Figs. 4, 4C, Col. 2, lines 51-52; Col. 5, lines 45-49) between the first structure (110) and the second structure (120), wherein the first structure (110) and the second structure (120) form a first electrode and a second electrode of a capacitor, respectively.
Regarding claim 2, Gupta discloses the method of claim 1. Further, Gupta discloses the method, wherein the non-conductive layer (e.g., the dielectric layer including Ta2O5 having a permittivity greater than 6) (Gupta, Figs. 4, 4C, Col. 2, lines 51-52; Col. 4, lines 1-3) has a permittivity of at least 6.
Regarding claim 3, Gupta discloses the method of claim 1. Further, Gupta discloses the method, wherein the non-conductive layer (e.g., the dielectric layer including silicon nitride (SiN)) (Gupta, Figs. 4, 4C, Col. 2, lines 51-52; Col. 4, lines 1-3).
Regarding claim 8, Gupta discloses the method of claim 1. Further, Gupta discloses the method, further comprising: depositing one or more layers (e.g., a gate insulating layer and a gate layer) (Gupta, Fig. 4, Col. 4, lines 43-57) for a transistor (410); forming the transistor (410) using the one or more layers such that the transistor is monolithically integrated with the capacitor (e.g., an integrated circuit IC (400) including a transistor (410) coupled to the interconnect (420) including a capacitor structure 100); and coupling the transistor to the capacitor.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over US Patent No. 6,383,858 to Gupta in view of Henry et al. (US Patent No. 6,465,297, cited in IDS of 09/09/2024, hereinafter Henry).
Regarding claims 4 and 5, Gupta discloses the method of claim 3. Further, Gupta does not specifically disclose the method, wherein the non-conductive layer further includes a tetraethoxysilane (TEOS) layer (as claimed in claim 4); wherein the TEOS layer is disposed between the silicon nitride layer and the first structure and between the silicon nitride layer and the second structure (as claimed in claim 5).
However, Henry teaches forming integrated capacitors for high current, high frequency application (Henry, Fig. 4, Col. 3, lines 4-24; Col. 4, lines 24-29, lines 58-67; Col. 5, lines 1-44, lined 58-62) comprising an interlayer dielectric (250) as a capacitor dielectric layer, wherein the interlayer dielectric (250) includes a high density TEOS material (251) and the nitride layer (252) on the TEOS layer, and the TEOS layer (251) is disposed directly on the interconnect layer (140), to provide better protection of the interconnect layer (140).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Gupta by forming an interlayer dielectric serving as a capacitor dielectric layer including a high density TEOS material as taught by Henry, such that the non-conductive layer includes TEOS oxide layer and the silicon nitride layer and the TEOS layer is disposed directly on the interconnect layer including the first structure and the second structure to have the method, wherein the non-conductive layer further includes a tetraethoxysilane (TEOS) layer (as claimed in claim 4); wherein the TEOS layer is disposed between the silicon nitride layer and the first structure and between the silicon nitride layer and the second structure (as claimed in claim 5), in order to provide better protection of the interconnect layer, and to provide improved interlayer dielectric layer having a high density material and a higher dielectric constant nitride material to improve capacitance value of the capacitor for high current and high frequency applications (Henry, Col. 3, lines 4-24; Col. 4, lines 58-67; Col. 5, lines 1-44, lines 58-62).
Claims 6-7 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over US Patent No. 6,383,858 to Gupta in view of Haeberlen et al. (US 2021/01349687, cited in IDS of 09/09/2024, hereinafter Haeberlen).
Regarding claim 6, Gupta discloses the method of claim 1. Further, Gupta discloses the method, wherein the metal layer (420a) (Gupta, Figs. 4, 4B, Col. 5, lines 15-19) is deposited on top of a stack including a semiconductor substrate (418) (Gupta, Figs. 4, 4B, Col. 4, lines 43-57), and a dielectric layer (430) over the semiconductor substrate (418), but does not specifically disclose the method, wherein a III-nitride layer is over the semiconductor substrate, and a dielectric layer over III-nitride layer.
However, Haeberlen teaches forming an integrated circuit (Haeberlen, Figs. 1, 5A-5B, ¶0002-¶0004, ¶0037, ¶0044, ¶0080-¶0091, ¶0100-¶0109) comprising a lateral transistor (61) and a capacitor (101) integrated into a metallization structure over a Group III nitride-based semiconductor body (66) on a substrate, wherein a III-nitride layer (e.g., GaN channel layer 68) is over the substrate, and a dielectric layer (85/84) is over III-nitride layer (68), to provide a power semiconductor device with better control of turn on/turn off speed (Haeberlen, Figs. 1, 5A-5B, ¶0002-¶0004, ¶0037, ¶0044, ¶0080-¶0091, ¶0105-¶0107).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Gupta by forming an integrated circuit comprising a lateral transistor and a capacitor integrated into a metallization structure over a Group III nitride-based semiconductor body as taught by Haeberlen to have the method, wherein a III-nitride layer is over the semiconductor substrate, and a dielectric layer over III-nitride layer, in order to provide a power semiconductor device with better control of turn on/turn off speed (Haeberlen, ¶0002-¶0004, ¶0037, ¶0044, ¶0080-¶0091, ¶0109).
Regarding claim 7, Gupta in view of Haeberlen discloses the method of claim 6. Further, Gupta discloses the method, wherein: the dielectric layer (430/130) (Gupta, Figs. 4, 4B, Col. 4, lines 1-3, 43-57) includes a silicon nitride layer, but does not specifically disclose the method, wherein: the III-nitride layer includes a gallium nitride (GaN) layer.
However, Haeberlen teaches forming an integrated circuit (Haeberlen, Figs. 1, 5A-5B, ¶0002-¶0004, ¶0037, ¶0044, ¶0080-¶0091, ¶0100-¶0109) comprising a lateral transistor (61) and a capacitor (101) integrated into a metallization structure over a Group III nitride-based semiconductor body (66) on a substrate, wherein a III-nitride layer (e.g., GaN channel layer 68) is over the substrate, and a dielectric layer (85/84) is over III-nitride layer (68), to provide a power semiconductor device with better control of turn on/turn off speed (Haeberlen, Figs. 1, 5A-5B, ¶0002-¶0004, ¶0037, ¶0044, ¶0080-¶0091, ¶0105-¶0107).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Gupta/Haeberlen by forming an integrated circuit comprising a lateral transistor and a capacitor integrated into a metallization structure over a Group III nitride-based semiconductor body as taught by Haeberlen to have the method, wherein: the III-nitride layer includes a gallium nitride (GaN) layer, in order to provide a power semiconductor device with better control of turn on/turn off speed (Haeberlen, ¶0002-¶0004, ¶0037, ¶0044, ¶0080-¶0091, ¶0109).
Regarding claim 9, Gupta discloses the method of claim 8. Further, Gupta does not specifically disclose the method, wherein at least one of the one or more layers for the transistor includes a GaN layer.
However, Haeberlen teaches forming an integrated circuit (Haeberlen, Figs. 1, 5A-5B, ¶0002-¶0004, ¶0037, ¶0044, ¶0080-¶0091, ¶0100-¶0109) comprising a lateral transistor (61) and a capacitor (101) integrated into a metallization structure over a Group III nitride-based semiconductor body (66) on a substrate, wherein a III-nitride layer (e.g., GaN channel layer 68) is over the substrate, and a dielectric layer (85/84) is over III-nitride layer (68), to provide a power semiconductor device with better control of turn on/turn off speed (Haeberlen, Figs. 1, 5A-5B, ¶0002-¶0004, ¶0037, ¶0044, ¶0080-¶0091, ¶0105-¶0107).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Gupta by forming an integrated circuit comprising a lateral transistor and a capacitor integrated into a metallization structure over a Group III nitride-based semiconductor body as taught by Haeberlen to have the method, wherein at least one of the one or more layers for the transistor includes a GaN layer, in order to provide a power semiconductor device with better control of turn on/turn off speed (Haeberlen, ¶0002-¶0004, ¶0037, ¶0044, ¶0080-¶0091, ¶0109).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATALIA GONDARENKO whose telephone number is (571)272-2284. The examiner can normally be reached 9:30 AM-7:30 PM.
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/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891
