DETAILED ACTION
This non-final action is responsive to communications: application filed on 09/09/2024.
Claims 1-20 are pending. Claims 1, 16, and 20 are independent.
Examiner Notes
A) Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. B) Per MPEP 2173.04 “If the claim is too broad because it reads on the prior art, a rejection under either 35 U.S.C. 102 or 103 would be appropriate”. C) Examiner cites particular paragraphs or columns and lines in the references as applied to Applicant's claims for the convenience of the Applicant. Other passages and figures may apply as well. Per MPEP 2141.02 VI prior art must be considered in its entirety. D) Per MPEP 2112 and 2112 V, express, implicit, and inherent disclosures of a prior art reference may be relied upon in the rejection of claims under 35 U.S.C. 102 or 103.
Notice of Pre-AIA or AIA Status
3. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
4. Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
5. Acknowledgment is made of applicant's Information Disclosure Statement (IDS) filed on 09/09/2024. This IDS has been considered.
Specification Objections
6. The title is objected to because the title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:
“Memory system capable of efficiently coping with changes in a power rail”
Claim Rejections - 35 USC § 102
7. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
8. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
9. Claims 1-2, 4-6, 9-10, 12, 14, 16-17, and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by YANG et al. (US 2017/0083034 A1).
Regarding independent claim 1, YANG teaches a semiconductor device (Fig. 18: 900A electronic device. See Fig. 1-Fig. 19 for illustrated components and functionality) comprising:
a first voltage terminal (Fig. 18: VIN3 terminal output from 53);
a second voltage terminal (Fig. 18: VIN2 terminal output from 52. See also Fig. 1 showing VIN2 terminal);
a voltage regulator (Fig. 18: 101, 130 combined “voltage regulator”) configured to convert a first power supply voltage (Fig. 18: VIN3) provided through the first voltage terminal (Fig. 18: VIN3 terminal output from 53) to a second power supply voltage (Fig. 18: Vout) lower than the first power supply voltage (in context of para [0123]: VIN3 is higher than both VIN1, VIN2; and VIN3 is thus higher than Vout);
a first internal circuit (Fig. 18: 950 “memory”) configured to:
receive the first power supply voltage (Fig. 18: VIN3) from the first voltage terminal (Fig. 18: VIN3 terminal output from 53), and operate based on the first power supply voltage (para [0130]); and
a second internal circuit (Fig. 18: 930 “logic circuit”) configured to:
receive the second power supply voltage (Fig. 18: Vout) from the second voltage terminal (Fig. 18: VIN2 terminal output from 52. VIN2 supplied as Vout See Fig. 7 switch configuration. Para [0066]) or the voltage regulator (Fig. 18: VIN1 supplied as Vout. See Fig. 8 switch configuration. Para [0072]), based on a mode signal (para [0009]: “power sequence” signal) indicating (indicating interpreted as signifying an indirect weak correlation) a single power rail mode (SPRM) or a dual power rail mode (DPRM) (in context of para [0134], para [0009]: power sequence signals PSEQ1, PSEQ2 enable different power supply voltages and associated operation modes), and
operate based on the second power supply voltage (para [0127], Fig. 18: 930 uses Vout for operation).
Regarding claim 2, YANG teaches the semiconductor device of claim 1, wherein the voltage regulator is configured to be disabled in the DPRM (Fig. 6: period I during when VIN1 is low and PSEQ1 low) and enabled in the SPRM (Fig. 6: period II, IV during when VIN1 is high and PSEQ1, VIN1 is high).
Regarding claim 4, YANG teaches the semiconductor device of claim 1, further comprising a voltage monitor (Fig. 1: 200 monitors VFED) configured to generate the mode signal by monitoring a voltage of the second voltage terminal (Fig. 1 and para [0037]: controls signals related to feedback output also changes the power sequence signals).
Regarding claim 5, YANG teaches the semiconductor device of claim 1, wherein, in the DPRM, the semiconductor device is configured to:
receive the first power supply voltage via a first power rail connected to the first voltage terminal (Fig. 1, Fig. 18: VIN3 is supplied to memory for system function of DRAM memory), and
receive the second power supply voltage via a second power rail connected to the second voltage terminal (Fig. 7, Fig. 6: VIN2 during period I of Fig. 6).
Regarding claim 6, YANG teaches the semiconductor device of claim 1, wherein, in the DPRM, the voltage regulator is further configured to be disabled (Fig. 6: period I),
wherein the first internal circuit is further configured to receive the first power supply voltage from the first voltage terminal (Fig. 1, Fig. 18: VIN3 is supplied to memory for system function of DRAM memory), and
wherein the second internal circuit is further configured to receive the second power supply voltage from the second voltage terminal (See Fig. 7 circuitry configuration).
Regarding claim 9, YANG teaches the semiconductor device of claim 1, wherein, in the SPRM, the voltage regulator is further configured to be enabled to generate the second power supply voltage (Fig. 8 configuration and Fig. 6),
wherein the first internal circuit (Fig. 18: 950) is further configured to receive the first power supply voltage (Fig. 18: VIN3) from the first voltage terminal (Fig. 18: VIN3 terminal), and
wherein the second internal circuit (Fig. 8: 160) is further configured to receive the second power supply voltage (Fig. 8: Vout) from the voltage regulator (Fig. 8).
Regarding claim 10, YANG teaches the semiconductor device of claim 1, further comprising a voltage disconnection switch (Fig. 7: 400, 500) configured to control an electrical connection between the second voltage terminal (Fig. 7: VIN2) and the second internal circuit (Fig. 7: 160), based on the mode signal (based on power sequence signals PSEQ2, PSEQ1).
Regarding claim 12, YANG teaches the semiconductor device of claim 1, further comprising a regulator input switch (Fig. 18: 53) configured to control an electrical connection between the first voltage terminal (Fig. 18: output terminal of 53) and the voltage regulator (Fig. 18: 101, 130), based on the mode signal (based on power sequence signal which activates regulator switches).
Regarding claim 14, YANG teaches the semiconductor device of claim 1, further comprising a regulator output switch (Fig. 7: 300, 400, 500) configured to control an electrical connection between the voltage regulator and the second internal circuit (Fig. 7: 160), based on the mode signal (based on power sequence signal which activates regulator switches).
Regarding independent claim 16, YANG teaches a semiconductor memory device (Fig. 18: 900A electronic device. See Fig. 1-Fig. 19 for illustrated components and functionality) comprising:
a first voltage terminal (Fig. 18: VIN3 terminal output from 53);
a second voltage terminal (Fig. 18: VIN2 terminal output from 52. See also Fig. 1 showing VIN2 terminal);
a voltage regulator (Fig. 18: 101, 130 combined “voltage regulator”) configured to convert a first power supply voltage (Fig. 18: VIN3) provided through the first voltage terminal (Fig. 18: VIN3 terminal output from 53) to a second power supply voltage (Fig. 18: Vout) lower than the first power supply voltage (in context of para [0123]: VIN3 is higher than both VIN1, VIN2; and VIN3 is thus higher than Vout);
a memory core circuit (Fig. 18: 950 memory) configured to:
receive the first power supply voltage (Fig. 18: VIN3) from the first voltage terminal (Fig. 18: VIN3 terminal output from 53), and operate based on the first power supply voltage (para [0130]); and
a peripheral circuit (Fig. 18: 930 “logic circuit”) configured to:
receive the second power supply voltage (Fig. 18: Vout) from either the second voltage terminal (Fig. 18: VIN2 terminal output from 52. VIN2 supplied as Vout See Fig. 7 switch configuration. Para [0066]) or the voltage regulator (Fig. 18: VIN1 supplied as Vout. See Fig. 8 switch configuration. Para [0072]), based on a mode signal (para [0009]: “power sequence” signal) indicating (indicating interpreted as signifying an indirect weak correlation) a single power rail mode (SPRM) or a dual power rail mode (DPRM) (in context of para [0134], para [0009]: power sequence signals PSEQ1, PSEQ2 enable different power supply voltages and associated operation modes), and
operate based on the second power supply voltage (para [0127], Fig. 18: 930 uses Vout for operation).
Regarding claim 17, YANG teaches the semiconductor memory device of claim 16, wherein, in the DPRM, the semiconductor memory device is configured to:
receive the first power supply voltage via a first power rail connected to the first voltage terminal (Fig. 1, Fig. 18: VIN3 is supplied to memory for system function of DRAM memory), and
receive the second power supply voltage via a second power rail connected to the second voltage terminal (Fig. 7, Fig. 6: VIN2 during period I of Fig. 6), and
wherein, in the DPRM, the voltage regulator is further configured to be disabled (Fig. 6: period I during when VIN1 is low and PSEQ1 low),
wherein the memory core circuit is further configured to receive the first power supply voltage from the first voltage terminal (Fig. 1, Fig. 18: VIN3 is supplied to memory for system function of DRAM memory), and
wherein the peripheral circuit is further configured to receive the second power supply voltage from the second voltage terminal (See Fig. 7 circuitry configuration where Vout/ VIN2 is received by logic circuit).
Regarding claim 19, YANG teaches the semiconductor memory device of claim 16, wherein the semiconductor memory device is in compliance with a Low Power Double Data Rate (LPDDR) standard (Claim language is very broad and does not describe specific of LPDDR standard. See e.g., para [0035]: low power mode of operation e.g., sleep mode is in LPDDR standard).
Regarding independent claim 20, YANG teaches a memory system (system employing Fig. 18: 900A. See Fig. 1-Fig. 19 for illustrated components and functionality) comprising:
a semiconductor memory device (Fig. 18: 900A electronic device);
a memory controller configured to control the semiconductor memory device (Fig. 18: 100A memory controller controls memory device);
one or more power rails (para [0009]); and
a power management integrated circuit (Fig. 18: 50A PMIC) configured to supply power to the semiconductor memory device and the memory controller via the one or more power rails (Fig. 18 in context of para [0121-para [0122]),
wherein the semiconductor memory device comprises,
a first voltage terminal (Fig. 18: VIN3 terminal output from 53);
a second voltage terminal (Fig. 18: VIN2 terminal output from 52. See also Fig. 1 showing VIN2 terminal);
a voltage regulator (Fig. 18: 101, 130 combined “voltage regulator”) configured to convert a first power supply voltage (Fig. 18: VIN3) provided through the first voltage terminal (Fig. 18: VIN3 terminal output from 53) to a second power supply voltage (Fig. 18: Vout) lower than the first power supply voltage (in context of para [0123]: VIN3 is higher than both VIN1, VIN2; and VIN3 is thus higher than Vout);
a memory core circuit (Fig. 18: 950 “memory”) configured to:
receive the first power supply voltage (Fig. 18: VIN3) from the first voltage terminal (Fig. 18: VIN3 terminal output from 53), and operate based on the first power supply voltage (para [0130]); and
a peripheral circuit (Fig. 18: 930 “logic circuit”) configured to:
receive the second power supply voltage (Fig. 18: Vout) from either the second voltage terminal (Fig. 18: VIN2 terminal output from 52. VIN2 supplied as Vout See Fig. 7 switch configuration) or the voltage regulator (Fig. 18: VIN1 supplied as Vout. See Fig. 8 switch configuration), based on a mode signal (para [0009]: “power sequence” signal) indicating (indicating interpreted as signifying an indirect weak correlation) a single power rail mode (SPRM) or a dual power rail mode (DPRM) (in context of para [0134], para [0009]: power sequence signals PSEQ1, PSEQ2 enable different power supply voltages and associated operation modes), and
operate based on the second power supply voltage (para [0127], Fig. 18: 930 uses Vout for operation).
Allowable Subject Matter
Claims 3, 7-8, 11, 13, 15, and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claims listed, the prior art of record does not appear to teach, suggest, or provide motivation for combination for the limitations described in details in the following:
3. The semiconductor device of claim 1, further comprising: a controller; and a mode register configured to store control values for controlling operations of the semiconductor device, wherein the controller is configured to generate the mode signal based on the control values stored in the mode register.
7. The semiconductor device of claim 1, wherein, in the SPRM, the semiconductor device is configured to receive the first power supply voltage via a power rail connected, in common, to the first voltage terminal and the second voltage terminal.
8. The semiconductor device of claim 1, wherein, in the SPRM, the semiconductor device is configured to receive the first power supply voltage via a power rail connected to the first voltage terminal, and wherein the second voltage terminal is floated without being connected to the power rail.
11. The semiconductor device of claim 10, wherein the voltage disconnection switch is further configured to: be turned on, in the DPRM, to electrically connect the second voltage terminal and the second internal circuit, and be turned off, in the SPRM, to electrically disconnect the second voltage terminal and the second internal circuit.
13. The semiconductor device of claim 12, wherein the regulator input switch is further configured to: be turned on, in the SPRM, to electrically connect the first voltage terminal and the voltage regulator, and be turned off, in the DPRM, to electrically disconnect the first voltage terminal and the voltage regulator.
15. The semiconductor device of claim 14, wherein the regulator output switch is further configured to: be turned on, in the SPRM, to electrically connect the voltage regulator and the second internal circuit, and be turned off, in the DPRM, to electrically disconnect the voltage regulator and the second internal circuit.
18. The semiconductor memory device of claim 16, wherein, in the SPRM, the semiconductor memory device is configured to receive the first power supply voltage via a power rail connected, in common, to the first voltage terminal and the second voltage terminal, and wherein, in the SPRM, the voltage regulator is further configured to be enabled to generate the second power supply voltage, wherein the memory core circuit is further configured to receive the first power supply voltage from the first voltage terminal, and wherein the peripheral circuit is further configured to receive the second power supply voltage from the voltage regulator.
Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure (MPEP § 707.05): CHOI (US 2014/0313819 A1): Fig. 1-Fig. 15 disclosure applicable for all claims. KENKARE (US 2015/0036446 A1): Fig. 1-Fig. 6 disclosure applicable for all claims. Daga (US 2005/0219903 A1): Fig. 1-Fig. 10 disclosure applicable for all claims.
It is suggested that applicant consider all prior arts made of record.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUSHFIQUE SIDDIQUE whose telephone number is (571)270-0424. The examiner can normally be reached on 7:00 am-4:00 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander George Sofocleous can be reached on (571) 272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MUSHFIQUE SIDDIQUE/
Examiner, Art Unit 2825