DETAILED ACTION
Claims 1-20 are presented for examination.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 9/9/24 has been considered by the examiner.
Drawings
The drawings are objected to because descriptive labels other than numerical are needed for figures 1B. See 37 CFR 1.84(o). A proposed drawing correction or corrected drawings are required in reply to the Office action to avoid abandonment of the application. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 2, 4-6, 15-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2011/0271159 to Ahn et al.
As per claim 1 Ahn et al. substantially teach the claimed circuit (Fig 2) comprising:
at least one first input/output (I/O) device (Fig 2 element 132);
at least one boundary scan element coupled to the at least one first I/O device (Paragraph [0044] when JTAG signals are used the boundary scan cells would be implied as in this context represents the IEEE 1149 standard for boundary scan);
at least one second I/O device (Fig 2 element 133); and
test circuitry configured to selectively couple (Fig 2 element 131) the at least one second I/O device to the at least one boundary scan element (the examiner would like to point on that the test signals in the IEEE 1149 (JTAG) standard are propagated through a test path of boundary scan elements), the test circuitry comprising a test controller (Fig 2 elements 132a and 133a) coupled to the at least one boundary scan element and configured to control the at least one boundary scan element (Fig 2 test path) to drive the at least one first I/O device and the at least one second I/O device with a binary test signal (boundary scan signals are binary).
Not explicitly disclosed is that there are two separate test controllers however this is merely a design choice as separate controllers would be functionally equivalent to having a single controller. Therefore it would have been obvious to a person having ordinary skill in the art at the time of filing of the present application to have two test controllers instead of just one.
Claim 15 is the method claim corresponding to circuit of claim 1 and is rejected for the same reasoning.
As per claim 2, Ahn et al. teach the at least one first I/O device comprises a plurality of first I/O devices arranged adjacent to one another (Fig 2 132b boundary scan cells including scan registers);
wherein the at least one second I/O device comprises a plurality of second I/O devices (Fig 2 133b_1 – 133b_n); and
wherein the binary test signal comprises a series of bits having alternating binary values such that adjacent first I/O devices and adjacent second I/O devices are driven with bits having opposite binary values (Paragraph [0048]).
As per claim 4, Ahn et al. teach the at least one second I/O device comprises a plurality of second I/O devices (Fig 2 133b_1 – 133b_n); the circuit further comprising: at least one switch that selectively couples the plurality of second I/O devices to the at least one boundary scan element (Fig 2 element 131).
As per claim 5, Ahn et al. teach at least one latch device coupled to the at least one second I/O device (scan elements on the test path Fig 2 are functionally equivalent to latches).
As per claim 6, Ahn et al. teach at least one switch (Fig 2 element 131)that selectively couples the at least one latch device to the at least one first I/O device (scan elements on the test path Fig 2 are functionally equivalent to latches).
As per claim 16, Ahn et al. teach observing the second state signals comprises reading a plurality of latch devices coupled to the plurality of second I/O devices (Paragraph [0048] TDO).
As per claim 17 Ahn et al teach observing the second state signals comprises: controlling another plurality of switches to couple the plurality of latch devices to a subset of the plurality of first I/O devices; and observing the second state signals via the subset of the plurality of first I/O devices (Paragraph [0049] through TDO terminal).
As per claim 18, Ahn et al. teach driving the plurality of first I/O devices comprises driving adjacent first I/O devices with opposite binary values (Paragraph [0048]).
As per claim 19, Ahn et al. teach driving the plurality of second I/O devices comprises driving adjacent second I/O devices with opposite binary values (Paragraph [0048]).
Claim(s) 8-12, and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2011/0271159 to Ahn et al. in view of US 7328387 to Whetsel.
As per claim 8, Ahn et al. substantially teach the claimed circuit comprising: a circuit board; a plurality of first input/output (I/O) devices (Fig 2 element 132) disposed on the circuit board; a corresponding plurality of boundary scan elements (Paragraph [0044] when JTAG signals are used the boundary scan cells would be implied as in this context represents the IEEE 1149 standard for boundary scan) disposed on the circuit board, individual boundary scan elements of the plurality of boundary scan elements coupled to respective individual first I/O devices (Fig 2 element 132) of the plurality of first I/O devices; and a plurality of second I/O devices (Fig 2 element 132) disposed on the circuit board and coupled to one or more of the plurality of boundary scan elements (the examiner would like to point on that the test signals in the IEEE 1149 (JTAG) standard are propagated through a test path of boundary scan elements).
Not taught by Ahn et al. is that the circuits being tested are on a circuit board. However in an analogous art Whetsel teaches multiple devices to be selectively boundary scan tested on a board (Column 14 lines 43-53). Therefore it would have been obvious to a person having ordinary skill in the art at the time of filing of the present application to have used the board of Whetsel with the circuitry of Ahn et al. as boundary scan testing would work the same in embedded cores as it does on a printed circuit board.
As per claim 9 Ahn et al. in view of Whetsel teaches the limitations of claim 8 as shown above and Ahn et al. also teach a plurality of latch elements (scan elements on the test path Fig 2 are functionally equivalent to latches) coupled to the plurality of second I/O devices; wherein the plurality of first I/O devices comprises a first subset of first I/O devices and a second subset of first I/O devices; and wherein the plurality of second I/O devices are coupled to the one or more boundary scan elements coupled to the first subset of first I/O devices (Fig 2 the test paths are made up of scan elements also Paragraph [0049]).
As per claim 10, Ahn et al. teach switches that selectively couple the plurality of latch elements to the second subset of first I/O devices (Figure 2 element 131 – having multiple switches instead of a single switch would still be a functional equivalent).
As per claim 11 Ahn et al. teach a test controller coupled to the plurality of boundary scan elements and configured to control the plurality of boundary scan elements to drive the plurality of first I/O devices and the plurality of second I/O devices with a binary test signal (Figure 2 elements 132a and 133a scan test signals are binary).
As per claim 12, Ahn et al. teach the binary test signal comprises a series of bits having alternating binary values such that adjacent first I/O devices of the plurality of first I/O devices and adjacent second I/O devices of the plurality of second I/O devices are driven with bits having opposite binary values (Paragraph [0048]).
As per claim 14, Ahn et al. teach the plurality of boundary scan elements comprises a plurality of shift register cells (Paragraph [0049]).
Allowable Subject Matter
Claims 3, 7, 13, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 8438439 to Xie teaches an IC with a scan chain and a first and second interface group and a scan data selector. The first and second interface group each have at least two input/output (I/O) interfaces which can be packaged as external pins of the IC. The I/O interfaces of the first interface group are connected to input terminals of the scan data selector in one-to-one correspondence, and an output terminal of the scan data selector is connected to a scan data input terminal of the scan chain. A scan data output terminal of the scan chain is directly connected to the I/O interfaces of the second interface group. The scan data selector, according to a package type, indicates signal inputted to a control terminal, select data in one of the I/O interfaces of the first interface group that corresponds to the package type indicating signal for output to the scan data input terminal. In each package type of the IC, at least one of the I/O interfaces of the first and second interface group is packaged as an external pin.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CYNTHIA H BRITT whose telephone number is (571)272-3815. The examiner can normally be reached Monday - Thursday 8-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mark Featherstone can be reached at (571)270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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CYNTHIA H. BRITT
Primary Examiner
Art Unit 2111
/CYNTHIA BRITT/Primary Examiner, Art Unit 2111