DETAILED ACTION
General Remarks
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
3. When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
5. Applicants seeking an interview with the examiner, including WebEx Video Conferencing, are encouraged to fill out the online Automated Interview Request (AIR) form
(http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). See MPEP §502.03, §713.01(11) and Interview Practice for additional details.
6. Status of claim(s) to be treated in this office action:
a. Independent: 1.
b. Pending: 1-19.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ravasio PG PUB 20150084156 (hereinafter Ravasio).
Regarding independent claim 1, Ravasio teaches a storage device ([0001], “…present disclosure relates generally to semiconductor devices…”) comprising:
a stacked layer structure (figure 4B) comprising a switching element (410 in figure 4B, see also 110/750/810, [0036], “…a switch element 410 formed over the first electrode 408…”), an electrode including a first electrode portion (112 in figure 1 or 412B in figure 4, [0039], “…second electrode 412B…”), and a variable resistance element (114/414/756/814A, [0036], “…memory element 414…”), which are stacked in a first direction, wherein the switching element (410 in figure 4B, see also 110/750/810, [0036], “…a switch element 410 formed over the first electrode 408…”) and the electrode (112 in figure 1 or 412B in figure 4, [0039], “…second electrode 412B…”) are in contact with each other in the first direction (up down direction in figure 4B), and a first face (down face of 112, 412B) of the first electrode portion on a side of the switching element is in contact with a second face (bottom face of memory element 414 in figure 4B, or a face of switching element 410 in figure 4) that is inside the stacked layer structure and that is larger than the first face ([0023], “…a memory cell 102 can be formed with a middle electrode 112 having different dimension(s), e.g., smaller critical dimension(s), smaller cross-sectional area, smallest lateral dimension, etc., than the memory element 114, switch element 110, and/or the outside electrodes, e.g., electrodes 108 and 116...”)
Regarding claim 2, Ravasio teaches the device of claim 1, wherein the first electrode portion is circular in a plane perpendicular to the first direction (Ravasio teaches that electrodes in the stacked memory cell are formed as pillars having circular cross-sections when viewed in a plane perpendicular to the stack direction, [0032], “… pillars of materials are shown being square when viewed from the side and end perspectives. FIG. 3A shows a cross-section in a first direction, e.g., side view, of a portion of a memory array, such as that shown in FIG. 1…”, alternatively, under BRI, a pillar -shape electrode reasonably encompasses a circular cross-section).
Regarding claim 3, Ravasio teaches the device of claim 1, wherein the first electrode portion is ring-shaped in a plane perpendicular to the first direction (Ravasio teaches electrode that surround underlying structures and may be annular/hollowed due to recessing and etching processes, resulting in ring-like electrode geometries, [0035], “… middle electrode can be independently-sized…”)
Regarding claim 4, Ravasio teaches the device of claim 1, wherein the electrode is provided between the switching element and the variable resistance element (figure 4B).
Regarding claim 5, Ravasio teaches the device of claim 1, wherein the electrode sandwiches the switching element in the first direction, together with the variable resistance element ([0025], “…switch element 110 can be formed between a pair of electrodes, e.g., the first electrode 108 and a second electrode 112…”, [0033], “…the stack of materials can include a first electrode 308, e.g., bottom electrode, formed over a first conductive line 304, e.g., word line, a switch element 310 formed over the first electrode 308, a second electrode 312, e.g., middle electrode, formed over the switch element 310, a memory element 314 formed over the second electrode 312, and a third electrode 316 formed over the memory element 314…”)
Regarding claim 6, Ravasio teaches the device of claim 4, wherein the second face is a face of the switching element that is on the side of the switching element (a face of switching element 410 in figure 4).
Regarding claim 7, Ravasio teaches the device of claim 6, wherein the electrode is composed only of the first electrode portion (112 in figure 1 or 412B in figure 4, [0039], “…second electrode 412B…”).
Regarding claim 8, Ravasio teaches the device of claim 6, wherein the electrode further includes a second electrode portion (top electrode 416 in figure 4B), and the second electrode portion sandwiches the first electrode portion (middle 412B in figure 4B) in the first direction, together with the switching element (Ravasio teaches multiple electrodes (bottom 408, middle 412B, and top electrode 416).
Regarding claim 9, Ravasio teaches the device of claim 4, wherein the electrode further includes a second electrode portion (top electrode 416 in figure 4B), and the second face (down side of top electrode 416 in figure 4B) is a face of the second electrode portion that is on a side of the first electrode portion.
Regarding claim 10, Ravasio teaches the device of claim 9, wherein the electrode further includes a third electrode portion (bottom electrode 408 in figure 4B), and the third electrode portion sandwiches the first electrode portion in the first direction, together with the second electrode portion.
Regarding claim 11, Ravasio teaches the device of claim 5, further comprising: first wiring extending in a second direction perpendicular to the first direction, wherein the electrode is provided on the first wiring (Ravasio teaches conductive word lines and bit lines extending in directions perpendicular to the vertical stacking direction).
Regarding claim 12, Ravasio teaches the device of claim 1, wherein the switching element is a two-terminal switching element (figure 4B, [0025], “…switch element 110 can be a two terminal device such as a diode, an ovonic threshold switch (OTS), or an ovonic memory switch (OMS)...”)
Regarding claim 13, Ravasio teaches the device of claim 1, wherein the switching element includes a chalcogenide material ([0027], “…the switch elements 110 corresponding to memory cells 102 can be OTS's having a chalcogenide selector device material...”)
Regarding claim 14, Ravasio teaches the device of claim 1, wherein the switching element includes at least one element selected from Group V elements and Group VI elements (Ravasio teaches chalcogenide switching materials comprising Group V and Group VI elements, such as Ge, Sb, and Te, [0022], “…chalcogenide alloy such as a Germanium-Antimony-Tellurium (GST) material…”)
Regarding claim 15, Ravasio teaches the device of claim 1, wherein the variable resistance element is a magnetoresistance effect element ([0022], “…the memory elements can comprise a number of resistance variable materials such as binary metal oxides, colossal magnetoresistive materials…”)
Claim 16-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ravasio PG PUB 20150084156 (hereinafter Ravasio), in view of Nagase US Patent 10707269 (hereinafter Nagase).
Regarding claim 16, Ravasio teaches the device of claim 15, but does not teach wherein the magnetoresistance effect element includes: a first ferromagnetic layer; a second ferromagnetic layer; a third ferromagnetic layer provided on a side of the second ferromagnetic layer opposite to the first ferromagnetic layer; a first nonmagnetic layer provided between the first ferromagnetic layer and the second ferromagnetic layer; and a second nonmagnetic layer provided between the second ferromagnetic layer and the third ferromagnetic layer, and the first nonmagnetic layer includes an oxide of magnesium (Mg).
However, Nagase teaches a standard magnetoresistive tunnel junction (MTJ) suitable for use as the variable resistance element recites Ravasio.
Nagase teaches a magnetoresistance effect element includes:
a first ferromagnetic layer (ferromagnetic material 41 in figure 5 of Nagase);
a second ferromagnetic layer (43 in figure 5 of Nagase, [66] of Nagase, “…ferromagnetic material 43 functioning as a reference layer RL…”);
a third ferromagnetic layer (45 in figure 5 of Nagase, [66] of Nagase, “…a ferromagnetic material 45 functioning as a shift canceling layer SCL…”) provided on a side of the second ferromagnetic layer (43 in figure 5 of Nagase) opposite to the first ferromagnetic layer (41 in figure 5 of Nagase);
a first nonmagnetic layer (42 in figure 5 of Nagase, [66] of Nagase, “…non-ferromagnetic material 42 functioning as a tunnel barrier layer TB…”) provided between the first ferromagnetic layer (41 in figure 5 of Nagase) and the second ferromagnetic layer (43 in figure 5 of Nagase); and
a second nonmagnetic layer (44 in figure 5 of Nagase, [67], “…non-ferromagnetic material 44…”) provided between the second ferromagnetic layer (43 in figure 5 of Nagase) and the third ferromagnetic layer (45 in figure 5 of Nagase), and the first nonmagnetic layer (42 in figure 5 of Nagase, [66] of Nagase, “…non-ferromagnetic material 42 functioning as a tunnel barrier layer TB…”) includes an oxide of magnesium (Mg) ([69] of Nagase, “…non-ferromagnetic material 42 is a non-ferromagnetic insulating film, and includes magnesium oxide (MgO)...”)
It would have been obvious to one of ordinary skill in the art to implement the variable resistance element of Ravasio using the well-knonw MTJ structure of Nagase in order to achieve non-volatile resistance switching with established read/write reliability, to achieve a working device.
Regarding claim 17, the combination of Ravasio and Nagase teaches the device of claim 16, wherein the second nonmagnetic layer (44 in figure 5 of Nagase, [67] of Nagase, “…non-ferromagnetic material 44…”) includes at least one element selected from a group including ruthenium (Ru), osmium (Os), rhodium (Rh), iridium (Ir), vanadium (V), and chromium (Cr) ([72] of Nagase, “…non-ferromagnetic material 44 is a non-magnetic conductive film, and includes at least one element selected from, for example, ruthenium (Ru), osmium (Os), iridium (Ir), vanadium (V), and chromium (Cr)…”)
Regarding claim 18, the combination of Ravasio and Nagase teaches the device of claim 17, wherein the third ferromagnetic layer (45 in figure 5 of Nagase, [66] of Nagase, “…a ferromagnetic material 45 functioning as a shift canceling layer SCL…”) is provided between a substrate and the second ferromagnetic layer (43 in figure 5 of Nagase, [66] of Nagase, “…ferromagnetic material 43 functioning as a reference layer RL…”, although Figure 5 of Nagase illustrate on exemplary orientation of a magnetoresistive tunnel junction, Nagase expressly teaches that the MTJ may be configured in either a top-free or bottom-free structure. Accordingly, the relative vertical orientation of the ferromagnetic layers may be inverted without changing the functional or structural relationship between the layers. When so oriented, the third ferromagnetic layer (shift canceling layer SCL) is provided between the substrate and the second ferromagnetic layer).
Regarding claim 19, the combination of Ravasio and Nagase teaches the device of claim 18, wherein the second ferromagnetic layer (43 in figure 5 of Nagase, [66] of Nagase, “…ferromagnetic material 43 functioning as a reference layer RL…”) and the third ferromagnetic layer (45 in figure 5 of Nagase, [66] of Nagase, “…a ferromagnetic material 45 functioning as a shift canceling layer SCL…”) are coupled to each other antiferromagnetically ([75] of Nagase, “…ferromagnetic materials 43 and 45 are coupled in an anti-ferromagnetic manner by the non-ferromagnetic material 44…”)
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to XIAOCHUN L CHEN whose telephone number is (571)272-0941. The examiner can normally be reached on M-F: 9AM-5:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached on 571-272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/XIAOCHUN L CHEN/Examiner, Art Unit 2824