Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Response to Amendment
Applicant' s amendment dated 02/20/2025 in which claims 1-18 were cancelled, and claims 19-29 were added has been entered of record. Currently, claims 19-29 are pending in light of the amendment.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless -
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 19-24, 28, and 29 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Chang (Patent Application Publication 2017/0040050).
Claim 19. A memory device comprising: a plurality of stacked high bandwidth memory layers (A stack of DRAM cores 1210-1225 Chang Fig 12); a plurality of channels (channels withing DRAM banks), each channel including a plurality of input/output (I/O) contacts and a plurality of command and address (CA) contacts (DRAM banks have a plurality of input/output (I/O) contacts and a plurality of command and address (CA) contacts); and a mode register configured to (configured to is functional language) enable or disable a selected one of the plurality of channels (logic layer 1235 Fig 13 smart refreshes thus enables or disables channels in banks, Chang Abstract); wherein the plurality of I/O contacts and the plurality of CA contacts of the selected one of the plurality of channels are configured to (configured to is functional language) be logically or electrically disconnected when disabled (channels are configured to be logically or electrically disconnected to a processor when disabled through interface 1305 Chang Fig 13, Abstract).
Claim 20. The memory device as claimed in claim 19 further comprising a logic layer including the plurality of I/O contacts and the plurality of CA contacts for each one of the plurality of channels (1235 Chang Fig 13 is the logic layer including the plurality of I/O contacts and the plurality of CA contacts for each one of the plurality of channels).
Claim 21. The memory device as claimed in claim 20 wherein the logic layer includes the mode register (as addressed in claim 19 logic layer 1235 Fig 13 comprises the smart mode, Chang Abstract).
Claim 22. The memory device as claimed in claim 19 wherein the mode register includes a bit configured to (configured to is functional language) enable the selected channel when set to a first value and to disable the selected channel when set to a second value opposite the first value (configured to with logic high or low signals which trigger the smart refresh 305 in Chang Fig 13).
Claim 23. The memory device as claimed in claim 22 wherein data for the selected channel is configured to (configured to is functional language) be redistributed to the I/O contacts of another channel when the bit is set to the second value (configured to be redistributed to the I/O contacts of another channel of the DRAM cores 1210-1225 using processor 120 Chang Fig 12 when the bit is set to the second value).
Claim 24. The memory device as claimed in claim 19 wherein each channel of the plurality of channels includes a clock contact configured to (configured to is functional language) receive a clock signal which determines an I/O transfer rate (configured to receive clock signal from processor to memory through interface 1305 Chang Fig 13, [0064]).
Claim 28. The memory device as claimed in claim 19 wherein the total number of I/O contacts and CA contacts is about 1000 (about is a relative term, the total number of I/O contacts and CA contacts is about 1000 in 1205 Chang Fig 12).
Claim 29. The memory device as claimed in claim 19 further comprising a package substrate (1205 Chang Fig 12 is in a package substrate).
Allowable Subject Matter
Claims 25-27 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 25-27. wherein the mode register includes a bit configured to enable the selected channel when set to a first value and to disable the selected channel when set to a second value opposite the first value, wherein data for the selected channel is configured to be redistributed to the I/O contacts of another channel when the bit is set to the second value, and wherein the clock signal for the another channel operates at a first frequency when the bit is set to the first value and a second frequency when the bit is set to the second value, in combination with other limitations.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jason Lappas whose telephone number is (571) 270-1272. The examiner can normally be reached on M-F 7:30AM-5:00PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Amir Zarabian can be reached on (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JASON LAPPAS/
Primary Examiner, Art Unit 2827
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