DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 08/07/2026 has been entered.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot in view of the new ground of rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hahn et al (US 10,558,376 B2) in view of Guterman et al (US 7,739,472 B2) and further in view of Mizushima (US 2008/0126712 A1) (“Mizushima”).
Claim 1: Hahn et al teach a memory system comprising (see Abstract; Fig. 1):
one or more memory devices, each memory device including a first memory area (e.g. Shared namespace- fig. 3) and a second memory area (e.g. private namespace- fig. 3; col. 7, lines13-17, describing namespace allocation), wherein a number of host devices that are accessible to the first memory area is equal to or greater than a number of host devices that are accessible to the second memory area (Shared namespace → accessible by multiple hosts and Private namespace → accessible by only one host- Col. 6, lines 17-21);
and a controller configured to, upon receiving a first command for a first address included in the first memory area, control an operation according to the first command based on an indirect mapping table that includes (e.g. Hahn et al teach a controller that receives commands from hosts targeting addresses within namespaces and uses a logical-to-physical translation mechanism (host-ID-to-namespace mapping and LBA→PBA mapping) to control access operations. The namespace mapping table and logical-address translation structure together form an indirect mapping table, Figs. 2–4): shared status information indicating a shared status of the first address to indicate whether the first address is a memory area that is shared by a plurality of host devices or dedicated to a specific host device (e.g. Hahn et al explicitly teach metadata indicating whether a namespace is shared or private, and whether a given region/address is accessible by multiple hosts or dedicated to a single host. Col. 6, lines 17-43 discussing namespace attributes and host-access permissions); accessibility status information indicating whether a specific host device is accessible to the first address (e.g. discloses that each namespace contains host-access permissions, stored in metadata, indicating which specific host(s) may access that namespace or address range- col. 7, lines 13-67, controlling access per host-ID ).
Not explicitly taught by Hahn et al is “overwrite status information indicating usage statuses of at least two data areas corresponding to the first address to indicate whether data in the at least two data areas is overwritten data, wherein the overwrite status information indicates whether all of the at least two data areas corresponding to the first address are used or only a part of the at least two data areas corresponding to the first address is used.”
However, Guterman et al teach controller-maintained overwrite-status metadata and mapping information associated with multiple physical data areas corresponding to logical addresses. Specifically, Guterman teaches, in Figures 6A-8:
logical-to-physical mapping structures,
Header flags,
overwrite-related metadata,
and controller-maintained status information stored in mapping tables.
Guterman teaches: “status information that the legacy host expect[s] to update on the header of a sector is instead maintained and updated in a table stored with the non-legacy memory device’s controller.” See col. 4, ll. 31-34. Guterman further teaches: “the non-legacy memory device does not support partial overwrites of previously written bytes or sectors.” See col. 4, ll. 34-37. Guterman additionally teaches maintaining logical-to-physical mapping information in controller-managed tables (e.g., see Guterman, col. 10, ll. 25-31) and that overwrite-related header information is maintained in mapping tables within the controller rather than in overwritten memory locations themselves. See Guterman, col. 11, ll. 3-6 and FIG. 8, disclosing “Header Flags” stored in the directory/mapping table. Furthermore, Guterman explains that: “status information that the legacy host expect[s] to update on the header of a sector is instead maintained and updated in a table stored with the non-legacy memory device’s controller.” See col. 4, ll. 31-34.
Therefore, it would have been obvious to a POSITA, before the effective filing date of the claimed invention, to incorporate the overwrite-status metadata and mapping-table management techniques of Guterman into the namespace accessibility mapping system of Hahn in order to improve overwrite tracking, consistency management, validity management, and logical-to-physical mapping control in a multi-host shared namespace environment. The modification merely combines known controller-managed overwrite-status tracking techniques with known namespace accessibility mapping techniques to yield predictable results, consistent with KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398 (2007).
Furthermore, Hahn et al and Guterman et al fail to teach that the controller is configured to check request status information received from one of the plurality of host devices, and determine one of the at least two data areas where the operation according to the first command is performed based on the overwrite status information and the request status information. However, Mizushima teaches an address-conversion table that stores physical addresses of at least two pages corresponding to one logical address. Its abstract states that latest data and past data can both be read for a single logical address designated by a host. Mizushima, in ¶¶ 0037-0039, further teaches that address-conversion table 1031 associates one logical address with a first physical address storing the latest data; and a second physical address storing data corresponding to the snapshot or earlier version. Thus, Mizushima teaches: “at least two data areas corresponding to the first address.”
Additionally, Mizushima, in ¶¶ 0040-0046, teaches page-status register 1032 containing status values indicating:
0: latest data;
1: data before updating/not latest;
8: invalid data; and
F: unwritten.
Accordingly, Mizushima tracks whether the corresponding data areas are written, unwritten, current, prior, or invalid. Mizushima initially has logical addresses for which no second physical address is set, meaning only the first physical-area entry is used. Later, after snapshot/update processing, a second physical address is populated while the first physical address identifies the newly updated data. Thus, Mizushima teaches the functional condition that, for the set of corresponding physical areas, only part of the available data-area entries may be used at one time, while multiple entries may be used when prior and updated data coexist. When combined with Guterman’s explicit overwrite/update-status information, this renders obvious the claimed: “overwrite status information indicates whether all of the at least two data areas corresponding to the first address are used or only a part of the at least two data areas … is used.”
Mizushima, in ¶ 0011, teaches a request judgment unit that determines whether a received read request is a latest-data read request or a snapshot read request. Mizushima further teaches an access-destination deciding unit that refers to:
address-conversion information;
status-setting information; and
snapshot-management information,
and determines the physical page to be accessed according to the received request. Mizushima’s claims provide an especially direct mapping. Claim 13 states that when the request is a latest-data read request, the access-destination deciding unit selects an address from the first physical-address group. And claim 14 states that when the request is a snapshot read request, the access-destination deciding unit selects an address from the appropriate second physical-address group corresponding to the generation instructed by the host. The second embodiment further teaches a read-data selection register storing a type value identifying latest data or a particular snapshot generation.
Mizushima, in ¶¶ 0159-0164, teaches that:
type value 1 results in reading from the second PA;
type value 2 results in reading from the third PA; and
type value 0 results in reading from the first PA corresponding to latest data.
Mizushima, in ¶¶ 0182-0183, likewise explains that if “latest” is selected, the first physical address is accessed, whereas if snapshot data is selected, the corresponding additional physical address is accessed. Accordingly, Mizushima teaches the claimed concept of:
“check request status information received from one of the plurality of host devices, and determine one of the at least two data areas where the operation according to the first command is performed based on the overwrite status information and the request status information.”
A POSITA therefore, before the effective filing date of the claimed invention, would have had reason to incorporate Mizushima’s multiple-version selection mechanism into Hahn’s multi-host storage controller, as modified by Guterman, to enable the controller to retrieve either current or prior data associated with a host logical address while retaining Hahn’s multi-host access restrictions and Guterman’s overwrite/update management.
As per claim 15, as discussed above for claim 1, Hahn teaches a storage system including a controller and multiple addressable memory regions/namespaces and controls host operations directed to those regions. Hahn further teaches host/queue-to-memory-region associations and shared/private memory regions. Guterman teaches indirect logical-to-physical address mapping and controller-maintained overwrite/update-status information. Mizushima teaches an address-conversion table in which a logical address corresponds to at least first and second physical data areas, page-status information identifying the usage/update state of those areas, and selection of one of the physical data areas according to information identifying the type of data requested by the host. See the rejection of claim 1 above.
Accordingly, the combined teachings of Hahn, Guterman, and Mizushima render obvious the limitations of claim 15 requiring:
an indirect mapping table including information on at least two data areas corresponding to the first address;
overwrite-status information indicating whether all of the at least two data areas are used or only part thereof is used; and
checking request-status information received from a host device and determining one of the at least two data areas where the operation is performed based on the overwrite-status information and the request-status information.
For the additionally recited second memory area and operation on one data area therein, Hahn teaches multiple separately addressable namespaces/memory regions, including shared and private namespaces, to which host commands are directed.
As per claim 18, As discussed above for claim 1, Hahn teaches a storage controller serving external host devices and maintaining host/queue-to-memory-region associations that indicate shared/private status and host-specific accessibility. Guterman teaches controller-maintained indirect logical-to-physical mapping information and overwrite/update-status information. Mizushima teaches multiple physical data areas corresponding to a single logical address and selecting one of those data areas according to host-request information and stored status information. See the rejection of claim 1 above.
Hahn teaches a storage controller associated with nonvolatile memory and serving multiple hosts. Hahn’s controller controls access to memory based on host/queue associations and shared/private namespace information. Guterman teaches controller 200 including address-translation component 230 and block manager 240 and maintaining HPB-to-LB and LB-to-MB mapping information. Guterman further teaches maintaining overwrite-status information in the controller mapping table. Mizushima teaches a memory controller that uses address-conversion information, page-status information, and request information to determine the physical page to be accessed according to the received host request.
Thus, for the reasons explained in detail above with respect to claim 1, the combined teachings render obvious the limitations of claim 18 requiring the controller to:
store an indirect mapping table including shared-status, accessibility-status, and overwrite-status information;
check those status values in response to a command from an external device; and
check request-status information and determine one of the at least two data areas where the operation is performed based on the overwrite-status information and the request-status information.
Claim 2: Hahn et al, Guterman et al and Mizushima teach the memory system according to claim 1, but fail to teach that upon receiving a read command as the first command, the controller checks the overwrite status information for the first address, and upon determination that the overwrite status information corresponds to a first overwrite status value, performs a read operation on a first data area of the at least two data areas corresponding to the first address. However, Hahn et al teach that the controller receives read commands and consults mapping information before reading data (e.g. Figs. 2-4, namespace read path). And Guterman et al teach that upon receiving a read command, the controller checks overwrite-status bits for a logical address and if the overwrite bit indicates “first” (e.g., valid), the controller reads from the first physical data area associated with the logical address (e.g. Figs. 5-6). Therefore, it would have been obvious to a POSITA, before the effective filing date of the claimed invention, to use Guterman’s overwrite-status read-selection logic in Hahn et al to improve version tracking and ensure the most recent valid data is read.
Claim 3: Hahn et al, Guterman et al and Mizushima teach the memory system according to claim 2, but fail to teach that the controller: checks the request status information according to the first command upon determination that the overwrite status information corresponds to a second overwrite status value; performs a read operation on the first data area upon determination that the request status information corresponds to a first request status value; and performs a read operation on a second data area of the at least two data areas corresponding to the first address upon determination that the request status information corresponds to a second request status value. However, Hahn et al teach Controller receives commands and may use metadata to control access and Guterman et al teach that when overwrite-status indicates “second version,” the controller may check request-type/status information (e.g., read-modify-write, sequential read, cached read). Based on this status, the controller chooses which physical copy to read (e.g. col. 10, lines 49-67; col 11, lines 1-42). Therefore, it would have been obvious to a POSITA, before the effective filing date of the claimed invention, that using request-status metadata to decide which physical version to read is well-known in SSD firmware to optimize access behavior.
Claim 4: Hahn et al, Guterman et al and Mizushima teach the memory system according to claim 3, wherein a point in time at which data is written to the first data area precedes a point in time at which data is written to the second data area (e.g. Guterman et al expressly teach multi-version data structures where first physical version is written at time T1 and second (newer) physical version is written at time T2 > T1, col. 7, lines 35-67).
Claim 5: Hahn et al, Guterman et al and Mizushima teach the memory system according to claim 1, wherein upon receiving a write command as the first command, in a case that the write command is a first write command for the first address, the controller performs a write operation on a first data area of the at least two data areas corresponding to the first address, and sets the overwrite status information for the first address to a first overwrite status value (e.g. Guterman teaches that on first write to an address, controller writes to the first data area and sets overwrite bits to a defined value indicating first version or valid- col. 10, lines 40-67).
Claim 6: Hahn et al, Guterman et al and Mizushima teach the memory system according to claim 5, wherein in a case that the write command is a write command for the first address subsequent to the first write command, the controller: performs a write operation on a second data area corresponding to the first address; and sets the overwrite status information for the first address to a second overwrite status value (e.g. (e.g. Guterman teaches that a second write goes to a second physical location and mapping entry is updated to show new overwrite-status value- Fig. 5A).
Claim 7: Hahn et al, Guterman et al and Mizushima teach the memory system according to claim 6, wherein an auxiliary data area corresponding to the first address has a size that is smaller than at least one of a size of the first data area or a size of the second data area (e.g. Guterman et al describe auxiliary/temporary metadata or buffer areas used during copy or update operations. These auxiliary areas often have smaller size than primary data blocks (e.g. col. 11, lines 1-26).
Claim 8: Hahn et al, Guterman et al and Mizushima teach the memory system according to claim 7, wherein the controller: performs a write operation on the auxiliary data area according to the first command; copies data from the second data area to the first data area; and copies data from the auxiliary data area to the second data area (e.g. Guterman: multi-step update process, Figs. 5-7).
Claim 9: Hahn et al, Guterman et al and Mizushima teach the memory system according to claim 1, wherein upon receiving a read command as the first command, the controller checks the accessibility status information for the first address, and in a case that a host device that transmits the first command is accessible to the first address, the controller performs a read operation on a data area corresponding to the first address, and in a case that the host device that transmits the first command is not accessible to the first address, the controller provides the host device with a result value of performing a bit operation using a preset value and a preset operator on data stored in the data area corresponding to the first address (e.g. Hahan: host-access permissions per namespace; controller checking if requesting host is permitted; returning host-specific results if unauthorized (error or masked data) col. 7, lines 13-67 & Guterman: discusses data masking and returning modified/placeholder values under certain restricted states or metadata conditions (e.g., invalid version, stale copy, col. 12, lines 10-30; col 13, lines 1-30).
Claim 10: Hahn et al, Guterman et al and Mizushima teach the memory system according to claim 1, wherein upon receiving a write command as the first command, the controller checks the accessibility status information for the first address, and in a case that a host device that transmits the first command is accessible to the first address, the controller performs a write operation on a data area corresponding to the first address, and in a case that the host device that transmits the first command is not accessible to the first address, the controller returns an error value to the host device (e.g. Hahn teaches per-host access permissions and return of error/status values when host attempts disallowed writes – col. 6-7).
Claim 11: Hahn et al, Guterman et al and Mizushima teach the memory system according to claim 1, wherein in a case that the shared status information for the first address is a first shared status value and a host device that transmits the first command is accessible to the first address according to the accessibility status information for the first address, the controller performs the operation according to the first command (e.g. Hahn: Shared vs private namespace status; host-access checks and performing operations only when both conditions pass – col. 4-7).
Claim 12: Hahn et al, Guterman et al and Mizushima teach the memory system according to claim 1, wherein upon receiving a second command for a second address included in the second memory area, the controller controls an operation according to the second command, and a data area of the at least two data areas corresponding to the second address is allocated to a host device that transmits the second command (e.g. Hahn: Second memory area = private namespace and when host accesses private namespace, the data area is allocated solely to that host, col. 5–7).
Claim 13: Hahn et al, Guterman et al and Mizushima teach the memory system according to claim 12, wherein the shared status information for the first address included in the first memory area is set to a first shared status value, and the shared status information for the second address included in the second memory area is set to a second shared status value (e.g. Hahn teaches: Shared namespace = first value; private namespace = second value, col. 4–7).
Claim 14: Hahn et al, Guterman et al and Mizushima teach the memory system according to claim 13, wherein the accessibility status information for the second address is set as inaccessible to the second address for a host device other than the host device that transmits the second command (e.g. Hahn teaches that private namespace access rules explicitly disallow access by other hosts, col. 5–7).
As per claim 16, the claim repeats claim 1’s metadata structure. Hahn et al and Guterman et al teach: shared status; accessibility status and overwrite status.
As per claim 17, a number of host devices accessible to the first memory area is equal to or greater than a number of host devices accessible to the second memory area is taught by Hahn: Shared namespace (multiple hosts) and private namespace (one host).
Claim 19: Hahn et al and Guterman et al teach the controller according to claim 18, wherein the control circuit performs, in a case that the overwrite status information corresponds to a first overwrite status value, an operation according to the command on a first data area corresponding to the address (e.g. col. 8-11, Guterman).
Claim 20: Hahn et al and Guterman et al teach controller according to claim 19, wherein the controller: in a case that the overwrite status information corresponds to a second overwrite status value, checks request status information according to the command; in a case that the request status information corresponds to a first request status value, performs an operation according to the command on the first data area; and in a case that the request status information corresponds to a second request status value, performs an operation according to the command on a second data area corresponding to the address (e.g. col. 10–12; Guterman).
Conclusion
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/GUERRIER MERANT/Primary Examiner, Art Unit 2111 09/01/2026
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