DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
RESPONSE TO ARGUMENTS
Applicant's arguments filed 6/23/2026 have been fully considered but they are not persuasive.
In response to applicant’s arguments with regard to the independent claim 1 rejected under 35 U.S.C. 103(a) that the combination of the references does not teach/suggest the claimed feature “… a back-end link … a sub-back-end link … through a memory physical later …” because Chiang’s fail to disclose two structurally distinct links and also fail to teach/suggest a memory physical layer through which accelerator memory device are controlled; applicant's arguments have fully been considered, but are not found to be persuasive.
The examiner respectfully disagrees, and to further clarify, Chiang does teach/suggest two distinct links for first ENC (200A) in first additional chassis (18A), wherein the two distinct links are having one link with first back-end interface (BE I/F) and having another link with second additional chassis (18B) (Fig. 4; [0041]-[0042]), and Chiang does teach/suggest a memory physical layer for physically connecting ENC (202A) with HDD (204) (Fig. 1; Fig. 4; [0028]-[0044]; and [0055]-[0058]).
As applicant appears to be applying the above arguments for independent claim 1 towards independent claims 16 and 13, the examiner will also apply the above response for independent claim 1 towards independent claims 16 and 13.
In response to applicant’s arguments with regard to the independent claim 13 rejected under 35 U.S.C. 103(a) that the combination of the references does not teach/suggest the claimed feature “… through the bridge chip … the bridge chop includes a plurality of second bridge links configure to communicate with the plurality of back-end chips …” because Burnham does not each/suggest the above claimed features; applicant's arguments have fully been considered, but are not found to be persuasive.
The examiner respectfully disagrees, and to further clarify, the examiner is not relying on the combination of the references, not on Burnham alone, fur the teaching/suggesting of the above claimed features.
I. REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-12 and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chiang et al. (US Pub.: 2013/0191576) in view of Burger et al. (US Pub.: 2017/0147624) and Bhagavat et al. (US Pub.: 2020/0185367)
As per claim 1, Chiang teaches/suggests a storage architecture comprising: a plurality of memory devices (e.g. associated with Fig. 1, ref. 204; Fig. 4, ref. 204) and configured to perform operations on data (e.g. associated with data transferring operations with the HDD (204): [0041]-[0042]); a front-end (e.g. associated with Fig. 1, ref. 104A), and configured to perform communication with a host device (e.g. associated with Fig. 1, ref. 10A, 10B); and a plurality of back-end (e.g. associated with Fig. 1, ref. 200A and Fig. 4, ref. 200A), wherein one of the plurality of back-end is configured to communicate with the front-end through a back-end link (e.g. associated with link between first ENC (200A) in first additional chassis (18A) and first back-end interface (BE I/F): Fig. 4: [0041]-[0042]), and each of the plurality of back end is configured to communicate with at least one other back-end through a sub back-end link (e.g. associated with link between the multiple additional chassis, such as link between link between first ENC (200A) of first additional chassis (18A) and second ENC (200A) of second additional chassis (18B), link between link between second ENC (200A) of second additional chassis (18B) and third ENC (200A) of third additional chassis (18C), and so on in Fig. 4: [0041]-[0042]) and control at least a part of the plurality of memory devices through a memory physical layer (e.g. associated with physical interconnection between ENC (202A) and HDD (204) in Fig. 4), and wherein the plurality of back-end coupled to each other in series based on a daisy chain scheme by the sub back-end link (e.g. associated with daisy chain architecture of Fig. 4, ref. 200A that link the multiple additional chassis (18A-18D)) (Fig. 1; Fig. 4; [0028]-[0044]; and [0055]-[0058]).
Chiang does not teach the storage architecture comprising:
accelerator module being on a package substrate;
chip located on the package substrate; and
chips located on the package substrate, configured to operate with chip, and chips operating accordingly with chip and operate with accelerator module, chips coupled accordingly.
Burger teaches/suggests an architecture comprising: accelerator module (e.g. module associated with hardware accelerator such as FPGA: [0020]; [0128]); chip operating accordingly, chips operating accordingly, chips configured to operate with chip, and chips operating accordingly with chip and operate with accelerator module, chips coupled accordingly (e.g. by combining communication between front end processor ASIC and back end processor ASIC with Chiang’s front end and plurality of back ends, the resulting combination of the references would further teach/suggest the above claimed features: [0020]-[0022]; [0035]-[0038]; [0045]-[0058]; [0128]) ([0020]-[0022]; [0035]-[0038]; [0045]-[0058]; and [0128]).
Bhagavat teaches/suggests an architecture comprising: being on a package substrate (e.g. associated with Fig. 2, ref. 140); located on the package substrate (e.g. associated with Fig. 2, ref. 140), located on the package substrate (e.g. associated with Fig. 2, ref. 140) (Fig. 1-2; and [0019]-[0024]).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Burger’s chip interconnecting architecture and Bhagavat’s packaging architecture into Chiang’s storage architecture for the benefit of implementing a robust architecture that reduces compression time while maintaining compression quality (Burger, [0019]) and reducing warpage of encapsulated integrated circuit module (Bhagavat, [0029]) to obtain the invention as specified in claim 1.
As per claim 3, Chiang, Burger, and Bhagavat teach/suggest all the claimed features of claim 1 above, where Chiang, Burger, and Bhagavat teach/suggest the storage architecture comprising: wherein the back-end link included in one of the plurality of back-end chips is configure to communicate with the front-end chip, and back-end links included in the rest of the plurality of back-end chips are not connected to the front-end chip (Chiang, Fig. 1; Fig. 4; [0028]-[0044]; [0055]-[0058]; Burger, [0020]-[0022]; [0035]-[0038]; [0045]-[0058]; [0128]; and Bhagavat, Fig. 1-2; [0019]-[0024]).
As per claim 4, Chiang, Burger, and Bhagavat teach/suggest all the claimed features of claim 1 above, where Chiang, Burger, and Bhagavat teach/suggest the storage architecture comprising: wherein each of the plurality of back-end chips comprises: an operating buffer memory circuit configured to store data associated with data arithmetic by the plurality of accelerator memory devices (Chiang, Fig. 1; Fig. 4; [0028]-[0044]; [0055]-[0058]; Burger, [0020]-[0022]; [0035]-[0038]; [0045]-[0058]; [0128]; and Bhagavat, Fig. 1-2; [0019]-[0024]).
As per claim 5, Chiang, Burger, and Bhagavat teach/suggest all the claimed features of claim 1 above, where Chiang, Burger, and Bhagavat teach/suggest the storage architecture comprising: a host interface configured to communicate with the host device; and a plurality of front-end links configured to communicate with at least a part of the plurality of back-end chips, and wherein at least one of the plurality of front-end links is in a disabled state (Chiang, Fig. 1; Fig. 4; [0028]-[0044]; [0055]-[0060]; Burger, [0020]-[0022]; [0035]-[0038]; [0045]-[0058]; [0128]; and Bhagavat, Fig. 1-2; [0019]-[0024]).
As per claim 6, Chiang, Burger, and Bhagavat teach/suggest all the claimed features of claim 1 above, where Chiang, Burger, and Bhagavat teach/suggest the storage architecture comprising: wherein the plurality of back-end chips is disposed to surround the front-end chip, and located between the front-end chip and the plurality of accelerator memory devices (Chiang, Fig. 1; Fig. 4; [0028]-[0044]; [0055]-[0060]; Burger, [0020]-[0022]; [0035]-[0038]; [0045]-[0058]; [0128]; and Bhagavat, Fig. 1-2; [0019]-[0024]), wherein it would have been an obvious design choice to one of ordinary skilled the art to further implementing the above architecture.
As per claim 7, Chiang, Burger, and Bhagavat teach/suggest all the claimed features of claim 1 above, where Chiang, Burger, and Bhagavat teach/suggest the storage architecture comprising: wherein the plurality of back-end chips is disposed to surround the front-end chip, and the plurality of accelerator memory devices is disposed to surround the plurality of back-end chips (Chiang, Fig. 1; Fig. 4; [0028]-[0044]; [0055]-[0060]; Burger, [0020]-[0022]; [0035]-[0038]; [0045]-[0058]; [0128]; and Bhagavat, Fig. 1-2; [0019]-[0024]), wherein it would have been an obvious design choice to one of ordinary skilled the art to further implementing the above architecture.
As per claim 8, Chiang, Burger, and Bhagavat teach/suggest all the claimed features of claim 1 above, where Chiang, Burger, and Bhagavat teach/suggest the storage architecture further comprising: an interconnect chip located on the package substrate, and configured to communicate with a back-end chip corresponding to a last node of a daisy chain formed by the plurality of back-end chips (Chiang, Fig. 1; Fig. 4; [0028]-[0044]; [0055]-[0060]; Burger, [0020]-[0022]; [0035]-[0038]; [0045]-[0058]; [0128]; and Bhagavat, Fig. 1-2; [0019]-[0024]), wherein it would have been an obvious to one of ordinary skilled the art to further implementing the above claimed features.
As per claim 9, Chiang, Burger, and Bhagavat teach/suggest all the claimed features of claim 8 above, where Chiang, Burger, and Bhagavat teach/suggest the storage architecture comprising: wherein the interconnect chip is electrically connected to at least one of a plurality of solder balls located on a lower surface of the package substrate (Chiang, Fig. 1; Fig. 4; [0028]-[0044]; [0055]-[0060]; Burger, [0020]-[0022]; [0035]-[0038]; [0045]-[0058]; [0128]; and Bhagavat, Fig. 1-2; [0019]-[0024]), wherein it would have been an obvious to one of ordinary skilled the art to further implementing the above claimed features.
As per claim 10, Chiang, Burger, and Bhagavat teach/suggest all the claimed features of claim 9 above, where Chiang, Burger, and Bhagavat teach/suggest the storage architecture comprising: wherein the plurality of accelerator memory devices is electrically disconnected from the plurality of solder balls (Chiang, Fig. 1; Fig. 4; [0028]-[0044]; [0055]-[0060]; Burger, [0020]-[0022]; [0035]-[0038]; [0045]-[0058]; [0128]; and Bhagavat, Fig. 1-2; [0019]-[0024]), wherein it would have been an obvious to one of ordinary skilled the art to further implementing the above claimed features.
As per claim 11, Chiang, Burger, and Bhagavat teach/suggest all the claimed features of claim 8 above, where Chiang, Burger, and Bhagavat teach/suggest the storage architecture comprising: wherein the interconnect chip is configured to communicate with another interconnect chip which is included in a semiconductor package located outside of the storage architecture (Chiang, Fig. 1; Fig. 4; [0028]-[0044]; [0055]-[0060]; Burger, [0020]-[0022]; [0035]-[0038]; [0045]-[0058]; [0128]; and Bhagavat, Fig. 1-2; [0019]-[0024]), wherein it would have been an obvious to one of ordinary skilled the art to further implementing the above claimed features.
As per claim 12, Chiang, Burger, and Bhagavat teach/suggest all the claimed features of claim 8 above, where Chiang, Burger, and Bhagavat teach/suggest the storage architecture comprising: wherein the interconnect chip is not directly connected to the plurality of accelerator memory devices (Chiang, Fig. 1; Fig. 4; [0028]-[0044]; [0055]-[0060]; Burger, [0020]-[0022]; [0035]-[0038]; [0045]-[0058]; [0128]; and Bhagavat, Fig. 1-2; [0019]-[0024]), wherein it would have been an obvious to one of ordinary skilled the art to further implementing the above claimed features.
As per claim 16, Chiang teaches/suggests a storage architecture comprising: a front-end (e.g. associated with Fig. 1, ref. 104A), and configured to communicate with a host device (e.g. associated with Fig. 1, ref. 10A, 10B); a plurality of back-end (e.g. associated with Fig. 1, ref. 200A and Fig. 4, ref. 200A) configured to perform communication with the front-end, and the plurality of back-end coupled to each other in series based on a daisy chain scheme (e.g. associated with daisy chain architecture of Fig. 4, ref. 200A); and a plurality of back-end (e.g. associated with Fig. 1, ref. 200A and Fig. 4, ref. 200A), wherein one of the plurality of back-end is configured to communicate with the front-end through a back-end link (e.g. associated with link between first ENC (200A) in first additional chassis (18A) and first back-end interface (BE I/F): Fig. 4: [0041]-[0042]) and each of the plurality of back-end is configured to communicate with at least one other back-end through a sub back-end link (e.g. associated with link between the multiple additional chassis, such as link between link between first ENC (200A) of first additional chassis (18A) and second ENC (200A) of second additional chassis (18B), link between link between second ENC (200A) of second additional chassis (18B) and third ENC (200A) of third additional chassis (18C), and so on in Fig. 4: [0041]-[0042]), and wherein the plurality of back-end are coupled to each other in series based on a daisy chain scheme by the sub back-end link (e.g. associated with daisy chain architecture of Fig. 4, ref. 200A that link the multiple additional chassis (18A-18D)); a plurality of memory devices (e.g. associated with Fig. 1, ref. 204; Fig. 4, ref. 204), configured to communicate with at least one of the plurality of backend through a memory physical layer included in each of the plurality of back-end (e.g. associated with physical interconnection between ENC (202A) and HDD (204) in Fig. 4) (Fig. 1; Fig. 4; [0028]-[0044]; [0055]-[0058]).
Chiang does not teach the storage architecture comprising:
chip located on a package substrate;
chips disposed on the package substrate, wherein chips is operating with chip and chips operate accordingly with chip, and wherein chips are coupled accordingly;
accelerator module located outside the package substrate, and operate with chips through chips.
Burger teaches/suggests an architecture comprising: chip operate accordingly; chips operate accordingly, wherein chips is operating with chip and chips operate accordingly with chip, and wherein chips are coupled accordingly (e.g. by combining communication between front end processor ASIC and back end processor ASIC with Chiang’s front end and plurality of back ends, the resulting combination of the references would further teach/suggest the above claimed features: [0020]-[0022]; [0035]-[0038]; [0045]-[0058]; [0128]); accelerator module (e.g. module associated with hardware accelerator such as FPGA: [0020]; [0128]), and operate with chips through chips (e.g. by combining back end processor ASIC with Chiang’s plurality of back ends, the resulting combination of the references would further teach/suggest the above claimed features: [0020]-[0022]; [0035]-[0038]; [0045]-[0058]; [0128]) ([0020]-[0022]; [0035]-[0038]; [0045]-[0058]; and [0128]).
Bhagavat teaches/suggests an architecture comprising: located on the package substrate (e.g. associated with Fig. 2, ref. 140); disposed on the package substrate (e.g. associated with Fig. 2, ref. 140); and module located outside the package substrate(e.g. associated with Fig. 2, ref. 140) (Fig. 1-2; [0019]-[0024]).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Burger’s chip interconnecting architecture and Bhagavat’s packaging architecture into Chiang’s storage architecture for the benefit of implementing a robust architecture that reduces compression time while maintaining compression quality (Burger, [0019]) and reducing warpage of encapsulated integrated circuit module (Bhagavat, [0029]) to obtain the invention as specified in claim 16.
As per claim 17, Chiang, Burger, and Bhagavat teach/suggest all the claimed features of claim 16 above, where Chiang, Burger, and Bhagavat teach/suggest the storage architecture comprising: wherein each of the plurality of back-end chips comprises: a first controller configured to control an operation of the back-end chip; a second controller configured to control at least a part of the plurality of accelerator memory devices; a first buffer memory circuit configured to store data according to an operation of the first controller; and a second buffer memory circuit configured to store data associated with data arithmetic by the plurality of accelerator memory devices in response to an operation of the second controller (Chiang, Fig. 1; Fig. 4; [0028]-[0044]; [0055]-[0058]; Burger, [0020]-[0022]; [0035]-[0038]; [0045]-[0058]; [0128]; and Bhagavat, Fig. 1-2; [0019]-[0024]), wherein it would have been an obvious to one of ordinary skilled the art to further implementing the above claimed features.
As per claim 18, Chiang, Burger, and Bhagavat teach/suggest all the claimed features of claim 16 above, where Chiang, Burger, and Bhagavat teach/suggest the storage architecture comprising: wherein the front-end chip comprises a first front-end link configured to communicate with at least one of the plurality of back-end chips and a second front-end link that is in a disabled state (Chiang, Fig. 1; Fig. 4; [0028]-[0044]; [0055]-[0058]; Burger, [0020]-[0022]; [0035]-[0038]; [0045]-[0058]; [0128]; and Bhagavat, Fig. 1-2; [0019]-[0024]), wherein it would have been an obvious to one of ordinary skilled the art to further implementing the above claimed features.
As per claim 19, Chiang, Burger, and Bhagavat teach/suggest all the claimed features of claim 18 above, where Chiang, Burger, and Bhagavat teach/suggest the storage architecture comprising: wherein one of the plurality of back-end chips comprises a back-end link connected to the front-end chip, and each of the rest of the plurality of back-end chips comprises a back-end link disconnected from the front-end chip (Chiang, Fig. 1; Fig. 4; [0028]-[0044]; [0055]-[0058]; Burger, [0020]-[0022]; [0035]-[0038]; [0045]-[0058]; [0128]; and Bhagavat, Fig. 1-2; [0019]-[0024]), wherein it would have been an obvious to one of ordinary skilled the art to further implementing the above claimed features.
As per claim 20, Chiang, Burger, and Bhagavat teach/suggest all the claimed features of claim 16 above, where Chiang, Burger, and Bhagavat teach/suggest the storage architecture further comprising: an interconnect chip located on the package substrate, and configured to communicate with a back-end chip corresponding to a last node of a daisy chain formed by the plurality of back-end chips (Chiang, Fig. 1; Fig. 4; [0028]-[0044]; [0055]-[0058]; Burger, [0020]-[0022]; [0035]-[0038]; [0045]-[0058]; [0128]; and Bhagavat, Fig. 1-2; [0019]-[0024]), wherein it would have been an obvious to one of ordinary skilled the art to further implementing the above claimed features.
Claims 13 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Chiang et al. (US Pub.: 2013/0191576) in view of Burger et al. (US Pub.: 2017/0147624), Bhagavat et al. (US Pub.: 2020/0185367), and Burnham (US Patent 6,597,232).
As per claim 13, Chiang teaches/suggests a storage architecture comprising: a plurality of memory devices (e.g. associated with Fig. 1, ref. 204; Fig. 4, ref. 204) and configured to perform operation on data (e.g. associated with data transferring operations with the HDD (204): [0041]-[0042]); a front-end (e.g. associated with Fig. 1, ref. 104A), and configured to perform communication with a host device (e.g. associated with Fig. 1, ref. 10A, 10B); and a plurality of back-end (e.g. associated with Fig. 1, ref. 200A and Fig. 4, ref. 200A), and configured to communication with the front-end and control at least a part of the plurality of memory devices through a memory physical layer (e.g. associated with physical interconnection between ENC (202A) and HDD (204) in Fig. 4), being configure to communicate with the plurality of back end (Fig. 1; Fig. 4; [0028]-[0044]; [0055]-[0058]).
Chiang does not teach the storage architecture comprising:
accelerator module being on a package substrate;
chip located on the package substrate;
a bridge chip disposed on the package substrate and operate with chip through a first bridge link; and
chips located on the package substrate, and configured to operate with chip through the bridge chip and operate with accelerator module,
wherein the bridge chip include a plurality of second bridge links configured to operate with chips.
Burger teaches/suggests an architecture comprising: accelerator module (e.g. module associated with hardware accelerator such as FPGA: [0020]; [0128]); chip operating accordingly; operating with chip; and chips configured to communicate with chip and operate with accelerator module, being configured to operate with chips (e.g. by combining communication between front end processor ASIC and back end processor ASIC with Chiang’s front end and plurality of back ends, the resulting combination of the references would further teach/suggest the above claimed features: [0020]-[0022]; [0035]-[0038]; [0045]-[0058]; [0128]) ([0020]-[0022]; [0035]-[0038]; [0045]-[0058]; and [0128]).
Bhagavat teaches/suggests an architecture comprising: being on a package substrate (e.g. associated with Fig. 2, ref. 140); located on the package substrate (e.g. associated with Fig. 2, ref. 140); chip (e.g. associated with Fig. 2, ref. 132) disposed on the package substrate (e.g. associated with Fig. 2, ref. 140) and include a first link (e.g. associated link with one of the chip (114/116) in Fig. 2); and located on the package substrate (e.g. associated with Fig. 2, ref. 140), and configured to operate through chip (e.g. associated with operating via Fig. 2, ref. 132), wherein the chip (e.g. associated with Fig. 2, ref. 132) include a second link (e.g. associated link with the other one of the chip (116/114) in Fig. 2) (Fig. 1-2; [0019]-[0024]).
Burnham teaches/suggests an architecture comprising: a bridge (e.g. associated with Fig. 2, ref. 240) operate through a first bridge link (e.g. associated with link to front end director (180) in Fig. 2); and to operate through the bridge (e.g. associated with Fig. 2, ref. 240), wherein the bridge include a plurality of second bridge links (e.g. associated with link to back end directors (200) in Fig. 2) (Fig. 2; col. 4, l. 42 to col. 7, l. 60).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Burger’s chip interconnecting architecture, Bhagavat’s packaging architecture Burnham’s bridge architecture into Chiang’s storage architecture for the benefit of implementing a robust architecture that reduces compression time while maintaining compression quality (Burger, [0019]), reducing warpage of encapsulated integrated circuit module (Bhagavat, [0029]), increasing the operation bandwidth (Burnham, col. 5, ll. 43-45) to obtain the invention as specified in claim 13.
As per claim 15, Chiang, Burger, Bhagavat, and Burnham teach/suggest all the claimed features of claim 13 above, where Chiang, Burger, Bhagavat, and Burnham teach/suggest the storage architecture further comprising: an interconnect chip configured to communicate with the bridge chip, and not directly connected to the plurality of back-end chips (Chiang, Fig. 1; Fig. 4; [0028]-[0044]; [0055]-[0058]; Burger, [0020]-[0022]; [0035]-[0038]; [0045]-[0058]; [0128]; Bhagavat, Fig. 1-2; [0019]-[0024]; and Burnham, Fig. 2; col. 4, l. 42 to col. 7, l. 60), wherein it would have been an obvious to one of ordinary skilled the art to further implementing the above claimed features.
II. PERTINENT RELATED PRIOR ART
Nalamalpu et al. (US Pub.: 2022/0337251): discloses a bridge chip that is connected to two other chips for providing communication between the two chips
III. CLOSING COMMENTS
CONCLUSION
STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. 707.07(i):
CLAIMS REJECTED IN THE APPLICATION
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHUN KUAN LEE whose telephone number is (571)272-0671. The examiner can normally be reached Monday-Friday.
IMPORTANT NOTE
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached on (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHUN KUAN LEE/Primary Examiner
Art Unit 2181 July 16, 2026
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