DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
As to claim 1, the limitation of “based on available scanning capacity of a VCI scanner” recites a relative and functional expression without providing objective boundaries for determining its scope. It is noted that the claim does not specify: what constitutes “scanning capacity”, and whether capacity refers to scan time, throughput, beam parameters or data limits or how such capacity is measured or allocated. Accordingly, the metes and bounds of the claim are unclear, rendering the claim indefinite.
As to claim 3, the limitation of “wherein the layout analysis ignores redundant segments” is indefinite. It is unclear what “redundant segments” are defined?
As to claim 4, the limitation of “wherein layout analysis ignores...by VIC” is a negative limitation and does not constitute a limitation in any patentable sense because the claim fails to define the operational scope of the recited exclusion, rendering the limitation indefinite.
As to claims 5, 7-8, the term “ignore” renders the claims indefinite since the claims recite that certain features or defects are “ignored” during layout analysis. However, the term “ignore” fails to provide objective boundaries as to how such features are treated. It is unclear whether the features are excluded from scanning, excluded from analysis, deprioritized, or otherwise processed. Accordingly, the scope of the limitation cannot be determined with reasonable certain.
Furthermore, the phrase "whereby" (line 16) renders the claim indefinite because it is unclear whether the limitation(s) following the phrase are part of the claimed invention. See MPEP § 2173.05(d).
Notwithstanding the indefiniteness of the term “available scanning capacity of a VCI scanner”, the limitation has been interpreted under the broadest reasonable interpretation as referring to inherent scanning throughput limitations of an inspection system. Also, the limitation following the term “whereby” of “ the VCI scanner....in a single pass” is considered as part of the claim. Also, the term “ignored” is understood to broadly encompass excluding, omitting, deprioritizing, or otherwise not considering certain features or defects in inspection targeting or analysis. The prior art applied below is evaluated in view of this interpretation.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-11 are rejected under 35 U.S.C 103 as being unpatentable over Baek et al (U.S.Pat. 11,315,841) in view of Bae et al (U.S. 2008/0224134 A1).
With respect to claim 1, Baek discloses a method of testing a processed semiconductor wafer (110; 200), using voltage contrast inspection (VCI) for detecting manufacturing defects and comprising steps of (a) performing a computer-assisted layout analysis of the wafer’s design to identify features (such as: pattern design data, pad regions and conductive lines) on the wafer where a short or open defect would be observable by VCI (see col.8, lines 43-50); (b) based on available scanning capacity of a VCI scanner (see col.10, lines 1-11), selecting features (210-290) corresponding to a subset of the observable short and/or open defects identified in step (a) for targeting by the VCI scanner (see col.10, lines 13-24); (c) scanning only the selected features to determine the presence or absence of the observable defects (see col.12, lines 44-54) selected in step (b) and (d) whereby the VCI scanner targets and evaluates a majority of the total VCI-observable defects.
Thus, Baek discloses substantially all limitations of the claim. Baek does not expressly disclose detecting defects within a single scan pass, as recited in the claim. Bae discloses a method for testing a processed semiconductor wafer using voltage contrast inspection (see abstract) and teaches inspection structures and voltage contrast techniques enabling defect detection within a single scan operation by providing contrast-enhancing supplementary conductive pattern (see paragraph [0110]). In view of such teachings, it would have been obvious to a skilled artisan before the effective filling date of the claimed invention to combine the teachings of Baek and Bae to obtain the claimed invention. It would have been obvious to one having ordinary skill in the art to incorporate the single-scan inspection capability of Bae into Baek’s targeted inspection methodology in order to detect a majority of observable defects within a single scan pass, thereby reducing inspection time and improving throughput.
As to claim 2, wherein the layout analysis of step (a) only considers open defects (in figure 5, Baek discloses voltage contrast inspection detecting open circuit defects in conductive structures).
As to claim 3, Baek excludes the layout analysis that includes redundant segments (see the disclosure of Baek and figure 5).
As to claim 4, Bake excludes features where a distance from a line end to a via is too short to permit defect detection by VCI (see figure 5).
Claim 5 recites that layout analysis ignores features that are not grounded. Baek discloses applying bias conditions to conductive lines and pads during voltage contrast inspection and Bae discloses grounded and floating conductive structures configured to produce voltage contrast signals. It would have been obvious to a skilled artisan to incorporate the teachings of Baek and Bae to filter inspection targets and exclude ungrounded features for the purpose of detecting defects of the semiconductor.
As to claim 6, Baek discloses the layout analysis of step (a) only considers short defects (see figure 9C; col.12, lines 47-48).
As to claim 7, Baek does not disclose the layout analysis includes hard grounded features (see col.6, lines 44-54).
As to claim 8, the claim recites ignoring features lacking a brighter neighbor. Baek discloses voltage contrast imaging where brightness differences correspond to electrical states of adjacent conductive features. Thus, detectability based on relative brightness would have been obvious to one having ordinary skill in the art for the purpose of detecting the defects of the semiconductor.
Claim 9 recites performing layout analysis under reverse bias. Baek discloses applying bias conditions during voltage contrast inspection. Thus, using reverse bias inspection constitutes an obvious bias configuration for the purpose of detecting defects of the semiconductor.
As to claim 10, claim recites comparing layout analyses to determine scanning mode. Baek determines defect states using inspection data from multiple inspection conditions. Thus, integrating the single-scan detection capability of Bae into such comparative analysis of Baek would have been obvious.
As to claim 11, the claim recites determining which defects are observable under normal versus reverse bias. Baek discloses bias-dependent defect detection. Bae teaches inspection contrast behavior based on conductive bias states within a single scan. In view of such teachings, assigning defect observability to specific bias mode would have been obvious to a skilled artisan to improve the quality of the inspection as intended by Baek.
Prior Art Made of Record
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
De et al (U.S.Pat. 9,793,090 B2); Chen et al (U.S.Pat. 12,196,687B2) disclose methods for inspecting pattern defects of the semiconductors and have been cited for technical background.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUNG HENRY NGUYEN whose telephone number is (571)272-2124. The examiner can normally be reached Monday-Friday 7:00AM-4:30PM.
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HUNG HENRY NGUYEN
Primary Examiner
Art Unit 2882
Hvn
2/13/26
/HUNG V NGUYEN/Primary Examiner, Art Unit 2882