Prosecution Insights
Last updated: August 17, 2026
Application No. 18/829,431

Aliasing-Based Broadband Noise Power Estimation for Arc-Fault Detection

Non-Final OA §102§103
Filed
Sep 10, 2024
Examiner
PATEL, DHARTI HARIDAS
Art Unit
2838
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
ABB Schweiz AG
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
4m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
1103 granted / 1263 resolved
+19.3% vs TC avg
Moderate +8% lift
Without
With
+7.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
16 currently pending
Career history
1275
Total Applications
across all art units

Statute-Specific Performance

§101
1.1%
-38.9% vs TC avg
§103
42.8%
+2.8% vs TC avg
§102
43.9%
+3.9% vs TC avg
§112
2.4%
-37.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1263 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-7 and 9-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tomimbang Patent No. US 8,879,218. Regarding claims 1, 12, and 18, Tomimbang discloses a computer-implemented method for computing a parameter associated with an arc-fault in an electrical network by analyzing a current signal comprising: obtaining the current signal from a current sensor of the electrical network [Fig. 1, hall effect sensor 1; HES 1; col. 12 lines 25-26]; transforming the current signal to a voltage signal [col. 13 lines 56-57: “HES 1 output voltages are proportional to the current flow”]; selecting a certain range of frequencies of the voltage signal using a filter [Fig. 1, anti alias filter 20; col. 12 line 29]; amplifying the certain range of frequencies of the voltage signal [Fig. 1, programmable gain amplifier 7]; converting the amplified certain range of frequencies of the voltage signal from analog to an aliased digitized signal using an undersampling scheme [Fig. 1, ADC]; and computing a power of the aliased digitized signal [Fig. 1, microprocessor computing a power of the aliased digitized signal]. Regarding claims 2, 13, and 19, Tominbang further comprises providing the computed power to an external component [Fig. 1, trip and reset switching circuit 14] of the electrical network. Regarding claims 3, 14, 20, Tominbang discloses that the external component is configured to detect an arc-fault in the electrical network by comparing the computed power to a threshold [Fig. 1, the trip and reset switching circuit 14 inherently has a latching comparator]. Regarding claims 4, 15, 20, Tominbang discloses that the external component is configured to trip a circuit breaker [Fig. 1, trip mechanism 15] of the electrical network based on detecting the arc-fault. Regarding claims 5, 12, Tominbang discloses that the undersampling scheme uses a sampling rate that is less than a minimum sampling rate defined by a Nyquist-Shannon sampling theorem for the selected certain range of frequencies of the voltage signal [Fig. 1, the anti-alias filter 20 is inherently designed specifically to prepare a signal to meet the Nyquist Shannon sampling theorem by blocking frequencies higher than half your chose sample rate]. Regarding claim 6, Tominbang discloses that computing the power includes squaring and time averaging the aliased digitized signal [col. 19 lines 57-67; col. 22 lines 52-59; the digital signal processor (DSP) uses the mean square value to determine an average power of an aliased digital signal; wherein the processor includes squaring the signal and then the squared values are summed and divided by the total number of samples to yield the mean square value or average power of the signal]. Regarding claim 7, Tominbang discloses that the time averaging is performed in millisecond time scales [col. 19 lines 57-67; col. 22 lines 52-59, the microprocessor and the DSP samples the current voltage values in millisecond time scale to monitor the rapidly fluctuating power dynamics]. Regarding claim 9, Tominbang discloses that the filter is implemented by a band pass filter that includes a certain number of capacitors and a certain number of resistors arranged between a current-voltage component, an operational amplifier, and an analog-to-digital conversion component [Fig. 1, the filter 20 is arranged between the current voltage component 1 and amplifier 7]. Regarding claims 10, 17, Tominbang discloses that the current signal is transformed to the voltage signal via the current-voltage component, the certain range of frequencies of the voltage signal are amplified via the amplifier, and the amplified certain range of frequencies of the voltage signal are converted from analog to the aliased digitized signal by the analog-to-digital conversion component, the analog-to-digital conversion component using a certain undersampling rate of the undersampling scheme, the power computed by a feature computation component [see rejection of claim 1, col 12, col. 13]. Regarding claim 11, Tominbang discloses that the certain range of frequencies is based on reference data associated with arc-faults detected in a controlled environment [Fig. 1, the filter 20 is used to prevent aliasing of sampled data and to remove noise in the signal by selecting certain range of frequencies; col. 10; col. 22 lines 41-52; col. 32 lines 66 to col. 33 lines 5]. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Tomimbang Patent No. US 8,879,218. Regarding claim 8, Tominbang does not explicitly disclose that the undersampling scheme uses an undersampling rate of at least 64 kilo samples per second and the certain range of frequencies is from 1 megahertz (MHz) to 3 MHz It would have been obvious to one having ordinary skill in the art at the time the invention was made to have an undersampling rate of at least 64 kilo samples per second and the certain range of frequencies is from 1 megahertz (MHz) to 3 MHz since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F. 2d 272, 205 USPQ 215 (CCPA 1980). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DHARTI PATEL whose telephone number is (571)272-8659. The examiner can normally be reached M - F 9 AM - 5 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu Tran can be reached at 571-270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. DHARTI PATEL Primary Examiner Art Unit 2836 /DHARTI H PATEL/Primary Examiner, Art Unit 2838
Read full office action

Prosecution Timeline

Sep 10, 2024
Application Filed
Jun 23, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
95%
With Interview (+7.7%)
2y 3m (~4m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1263 resolved cases by this examiner. Grant probability derived from career allowance rate.

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