DETAILED ACTION
The Amendment filed July 21, 2026 has been entered. Claims 1-20 are pending. Claims 1, 8 and 15 are independent.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of US Patent No. 12,119,068. Although the claims at issue are not identical, they are not patentably distinct from each other.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2021/0202008) in view of Arora et al. (US 2021/0373764).
Regarding independent claims 1, 8 and 15, Lee et al. teach a system comprising:
a memory device (FIG. 3 along with FIG. 1); and
a processing device, operatively coupled with the memory device, to perform operations comprising:
responsive to detecting a power up event of the memory device1, identifying an open block (FIG. 1: O_BLK, para. 0030-0036, the free block FR_BLK … the open block O_BLK …) of the memory device;
determining, based on at least one charge loss metric associated with a set of programmed pages of the open block or at least one charge gain metric associated with a set of erased pages of the open block whether the open block is valid for programming (e.g., para. 0042: … a charge loss, charge gain2 … in the free block … Thus, an error may occur during a process of programming new data. For this reason, the conventional controller generates the free block (along with para. 0031: the free block FR_BLK, …, may be used as the open block O_BLK)… just before performing a program operation …; and para. 0177: The controller may determine … the open block O_BLK is changed to a closed block … the open block O_BLK may be changed to the closed block C_BLK; i.e., the closed block does not valid for programming (by para. 0032: … Among closed blocks C_BLK, a memory block … because the memory block has no valid data stored …)).
Lee et al’ open block does not explicitly disclose responsive to determining that the open block is not valid for programming, abandoning the open block.
Arora et al. teach the deficiencies in e.g., FIG. 7, 736: Open Block as GBB, and accompanying disclosure, e.g., para. 0054: … the controller may mark … as a GBB (para. 0005: grown bad blocks) and remove it from the population of available open blocks.
Lee and Arora are analogous art because they both are directed to flash memory device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lee with the specified features of Arora because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Arora et al. to the teaching of Lee et al. such that a memory, as taught by Lee et al., utilizes a abandoning non valid blocks, as taught by Arora et al., for the purpose of utilizing healthy storage space, thereby improving storage device performance during memory operations.
Regarding claims 2, 9 and 16, Lee et al. and Arora et al, as combined, teach the limitations of claims 1, 8 and 15, respectively.
Lee et al. further teach the set of programmed pages comprises an oldest written page of the open block (see e.g., FIG. 1: O_BLK, i.e., one of DAT is oldest written).
Regarding claims 3, 10 and 17, Lee et al. and Arora et al, as combined, teach the limitations of claims 1, 8 and 15, respectively.
Lee et al. further teach the set of programmed pages comprises a set of sample pages, wherein each sample page of the set of sample pages is associated with a respective individual charge loss metric, and wherein the at least one charge loss metric is a function of each respective individual charge loss metric (see FIGS. 5A-5B, and accompanying disclosure, e.g., para. 0123-0129: … the program unit …).
Regarding claims 4, 11 and 18, Lee et al. and Arora et al, as combined, teach the limitations of claims 1, 8 and 15, respectively.
Lee et al. further teach determining whether the open block is valid for programming further comprises at least one of: determining whether an amount of charge loss is less than or equal to a threshold amount of charge loss; determining whether a number of cells that have a threshold voltage above a charge loss detection read level is greater than or equal to a threshold number of cells; or determining whether a position difference related to movement of a center of a valley of an erased state threshold voltage distribution is greater than or equal to a threshold position difference (see e.g., para. 0042: … the time point of a program operation … charge loss … the threshold voltage distribution of memory cell …).
Regarding claims 5 and 12, Lee et al. and Arora et al, as combined, teach the limitations of claims 1 and 15, respectively.
Lee et al. further teach the set of erased pages comprises a first erased page of the open block. (see e.g., FIG. 1, ET_BLK from O_BLK).
Regarding claims 6, 13 and 19, Lee et al. and Arora et al, as combined, teach the limitations of claims 1, 8 and 15, respectively.
Lee et al. further teach the set of erased pages comprises a set of sample pages, wherein each sample page of the set of sample pages is associated with a respective individual charge gain metric, and wherein the at least one charge gain metric is a function of each respective individual charge gain metric (see FIGS. 5A-5B, and accompanying disclosure, e.g., para. 0123-0129: … the erase target blocks …).
Regarding claims 7, 14 and 20, Lee et al. and Arora et al, as combined, teach the limitations of claims 1, 8 and 15, respectively.
Lee et al. further teach determining whether the open block is valid for programming further comprises at least one of: determining whether an amount of charge gain is less than or equal to a threshold amount of charge gain; determining whether a number of cells that have a threshold voltage below a charge gain detection read level is less than or equal to a threshold number of cells; or determining whether a position difference related to movement of a center of a valley of an erased state threshold voltage distribution is greater than or equal to a threshold position difference (see e.g., para. 0042: … the time point of a program operation … charge gain … the threshold voltage distribution of memory cell …).
Response to Arguments
Applicant’s arguments filed 06/05/2026, with respect to the rejection(s) of claims 1-20 under 35 USC 102 and 103, have been fully considered but are moot in view of the new ground(s) of rejection. See the art rejection above for more details.
Therefore, it is respectfully submitted that the examiner maintains the rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUNG IL CHO whose telephone number is (571)270-0137. The examiner can normally be reached on M-Th, 7:30AM-5PM; Every other F, 7:30AM-4PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander G Sofocleous can be reached on 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SUNG IL CHO/Primary Examiner, Art Unit 2825
1 Lee’s identifying an open block (see FIG. 1) does not explicitly disclose responsive to detecting a power up event.
However, the claimed limitation is a well-known technology for a type of memory (e.g., flash memory) for its purpose.
For support, of the above asserted facts, see for example, Kumar et al. (US 9,691,485), e.g., col. 6, lines 48-58: … during every initialization/power-up of the storage system, the storage system can scan all the open blocks to check …; Lehman et al. (US 2016/0283397), para. 0068: On power up, … the closed blocks and the open blocks, …; Ng et al. (US 9,361,991), col, 12, lines 10-28: …when the memory system powers up again the locations of open blocks …
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize non-volatile memory used as configuration flash memory in identifying blocks in response to power-up because these conventional technology are well established in the art of the memory devices
2 A charge loss with respect to a programmed memory cell, and a charge gain with respect to a erase state is an inherent characteristic of a flash memory device (see, for example, Kang et al. (US 2015/0364199), paragraph [0068]).
Prosecution Insights