DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement(s)
The Information Disclosure Statement(s) filed on September 10, 2024 and November 5, 2025 were considered by the Examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-16, 18-21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 includes “a plurality of first pillars provided in the second region and the third region, each of the first pillars having a portion crossing at least one of the first conductive layers and having a configuration different from a configuration of each of the memory pillars” and the underlined portion of this limitation is indefinite as it is unclear what configuration means in this context. For example, it is unclear if “a configuration different from a configuration of each of the memory pillars” means the materials of the first pillars, the connections made to the first pillars, the spacing or pitch of the first pillars, and/or some other property of the first pillars is different from that of the memory pillars. For the purposes of examination, this underlined portion of the limitation will be interpreted to mean “and wherein a spacing or pitch of the first pillars is different from a spacing or pitch of the memory pillars.”
Further, claim 1 includes “a plurality of memory pillars provided in the first region, each of the memory pillars having a portion crossing the first conductive layers and including a stacked film” and “a plurality of second pillars provided in the second region, each of the second pillars having a portion crossing at least one first conductive layer among the first conductive layers and including the stacked film” and it is unclear if the second instance of “stacked film” is intended to refer to the same stacked film in the memory pillars or to a different stacked film. If it refers to the same stacked film in the memory pillars, it is unclear how the same stacked film can be in two regions, i.e., it is unclear how the same stacked film can be in the first region which is where the memory pillars are provided, and also the second region which is where the second pillars are provided.
Accordingly, for the purposes of examination, the instances of “stacked film” will be interpreted to be different, i.e., the first instance of “stacked film” which is in the memory pillars will be interpreted to mean “first stacked film” and the second instance of “stacked film” which is in the second pillars will be interpreted to mean “second stacked film.” In claim 14, the instance of “stacked film” will be interpreted as referring to the “first stacked film.” In claim 15, the stacked film in the second pillars will be interpreted as referring to the “second stacked film” and the stacked film in the memory pillars will be interpreted as referring to the “first stacked film.”
Claims 2-13, 16, 18-21 are rejected due to their dependency from claim 1.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-13, 16, 18, 20-21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US10,381,434B1 (“Pachamuthu”).
First Rejection of Claim 1:
RE: Claim 1, Pachamuthu discloses A memory device (device in FIG. 19) comprising:
a substrate (8) including a first region (100 in FIG. 13B), a second region (right region of 200 in FIG. 13B, which is the right part of 200 that is vertically delineated by the rightmost edge of 165 in FIG. 18), and a third region (left region of 200 in FIG. 13B, which is the left part of 200 that is vertically delineated by the rightmost edge of 165 in FIG. 18) arranged in order in a first direction (horizontal direction hd1 in FIG. 13B);
a plurality of first conductive layers (146, 246 in FIG. 19, Col. 33, lines 33-35) provided apart from the substrate in a second direction (vertical direction in FIG. 19) crossing the first direction and arranged in the second direction;
a plurality of memory pillars (memory fill structures 58 in FIG. 19, Col. 29, lines 37-40) provided in the first region, each of the memory pillars having a portion crossing the first conductive layers and including a stacked film (combination of 54, 56 of 50 shown in FIG. 15B; Each memory opening fill structure 58 comprises a vertical semiconductor channel 60 and a memory film 50, Col. 29, lines 37-45; Each memory film 50 can comprise a layer stack including a tunneling dielectric layer 56, a charge storage layer 54, and a blocking dielectric layer 52, Col. 29, lines 55-60);
a plurality of first pillars (52 of dummy memory films 50’ of 20 extending through 246 and 146 in FIGs. 15A-15B, excluding uppermost pillars of 52 of 50’ in 20 in region 200 in FIG. 13B; Alternatively: 52 of 50’ and pedestal channel portion 11, Col. 29, lines 1-14; Each memory film 50 and each dummy memory film 50′ can include a layer stack of a blocking dielectric layer 52, a charge storage layer 54, and a tunneling dielectric layer 56, Col. 28, lines 25-40) provided in the second region and the third region, each of the first pillars having a portion crossing at least one of the first conductive layers (246 or 146) and having a configuration different from a configuration of each of the memory pillars (FIG. 13B shows 20 has configuration different from a configuration of 58 in that 20 are spaced farther apart from each other than 58; Accordingly, 52 in 20 has configuration different from a configuration of 58 in that 52 in 20 are spaced farther apart from each other than 58); and
a plurality of second pillars (combinations of 54, 56 of dummy memory films 50’ of 20 extending through 146 and 246 in FIGs. 15A, 15B, excluding uppermost pillars of 54, 56 in 20 in region 200 in FIG. 13B; see also FIGs. 10, 11, 12A-12B) provided in the second region, each of the second pillars having a portion crossing at least one first conductive layer (146 or 246) among the first conductive layers and including the stacked film (combination of 54, 56 of dummy memory 50’ which has the same thickness and same composition as 54, 56 of memory pillars 50; Each support pillar structure 20 can comprise a dummy memory film 50′ including a dummy tunneling dielectric layer having a same thickness and a same composition as the tunneling dielectric layer 56, a dummy charge storage layer having a same thickness and a same composition as the charge storage layer 54, and a dummy blocking dielectric layer having a same thickness and a same composition as the blocking dielectric layer 52, Col. 29, lines 55-60).
RE: Claim 2, Pachamuthu discloses The memory device of claim 1, wherein in the second region, at least a part of each of the second pillars overlaps with any one of the first pillars in the second direction (FIG. 12B shows upper portions of 50’ overlap lower portions of 50’ in the vertical direction; Accordingly, upper portions of second pillars formed of 54, 56 in 50’ overlap with lower portions of first pillars 52 in 50’ in FIG. 12B in the vertical direction).
RE: Claim 3, Pachamuthu discloses The memory device of claim 1, wherein each of the second pillars is apart from the first conductive layers (Pachamuthu discloses a blocking dielectric layer 52, a charge storage layer 54, a tunneling dielectric layer 56, and an optional first semiconductor channel layer 601 can be sequentially deposited in the inter-tier support openings 19, Col. 23, lines 4-11; FIG. 10 shows 52 is deposited first; Accordingly, as 52 is deposited first for each second pillar formed of 54, 56, 52 would space each second pillar formed of 54, 56 apart from conductive layers 246 in FIG. 19).
RE: Claim 4, Pachamuthu discloses The memory device of claim 1, wherein the first pillars are arranged in a lattice configuration in the second region (FIG. 13B shows 20 are arranged in a lattice configuration in the right region of 200; Accordingly, first pillars 52 in 20 are arranged in a lattice configuration in the right region of 200), the second pillars are arranged in a lattice configuration in the second region (FIG. 13B shows 20 are arranged in a lattice configuration in the right region of 200; Accordingly, second pillars formed of 54, 56 in 20 are arranged in a lattice configuration in the right region of 200), and numbers of rows and columns of the second pillars arranged in the second region are same as numbers of rows and columns of the first pillars arranged in the second region, respectively (As each first pillar 52 is in a respective 20, and each second pillar is a combination of 54, 56 in a respective 20, the number of rows and columns of the second pillars arranged in any region including the second region is the same as the number of rows and columns of the first pillars arranged in the second region in FIG. 13B).
RE: Claim 5, Pachamuthu discloses The memory device of claim 1, wherein the first pillars are arranged in a lattice configuration in the second region (FIG. 13B shows 20 are arranged in a lattice configuration in the right region of 200; Accordingly, first pillars 52 in 20 are arranged in a lattice configuration in the right region of 200), the second pillars are arranged in a lattice configuration in the second region (FIG. 13B shows 20 are arranged in a lattice configuration in the right region of 200; Accordingly, the second pillars formed of 54, 56 in 20 are arranged in a lattice configuration in the right region of 200), and a pitch of the second pillars arranged in the second region is same as a pitch of the first pillars arranged in the second region (52, 54, 56, 60 forms part of each support pillar 20, Col. 29, lines 55-60, Col. 28, lines 25-40, Col. 29, lines 1-14; Accordingly the center-to-center pitch of each first pillar 52 is the same as the center-to-center pitch of each support pillar 20 as shown in FIGs. 10, 13B, and the center-to-center pitch of each second pillar formed of 54, 56 in 20 is the same as the center-to-center pitch of each support pillar 20 as shown in FIGs. 10, 13B; Accordingly, a pitch of the second pillars formed of 54, 56 in 20 arranged in the second region is same as a pitch of the first pillars 52 arranged in the second region).
RE: Claim 6, Pachamuthu discloses The memory device of claim 1, wherein at least one second pillar among the second pillars is shorter than each of the memory pillars in the second direction (58 includes 11 and 50, Col. 29, lines 1-14, Col. 28, lines 62-66; As the second pillar is formed of a combination of 54, 56 which are part of 50’ in 20, and the memory pillars 58 are formed of 11 and 50, the memory pillars 58 extend to 10 in FIG. 15B while the second pillars 54, 56 in 20 extend to 11 and therefore the second pillars formed of 54, 56 in 20 are shorter than the memory pillars 58).
RE: Claim 7, Pachamuthu discloses The memory device of claim 1, wherein a diameter of each of the second pillars is smaller than a diameter of each of the first pillars in the second region (FIG. 15B shows a diameter of upper portions of 50’ is smaller than a diameter of lower portions of 50’; Accordingly, a diameter of upper portions of each second pillar formed of 54, 56 in 50’ is smaller than a diameter of lower portions of each first pillar 52 in 50’).
RE: Claim 8, Pachamuthu discloses The memory device of claim 7, wherein a diameter of at least one second pillar among the second pillars is smaller than a diameter of each of the memory pillars (FIG. 12B shows a diameter of an upper portion of a second pillar formed of 54, 56 in 50’ is smaller than a diameter of an upper portion of each memory pillar 58 formed of 50).
RE: Claim 9, Pachamuthu discloses The memory device of claim 1, wherein a length in the second direction of each of the memory pillars is substantially equal to a length in the second direction of each of the first pillars (58 includes 11 and 50, Col. 29, lines 1-14, Col. 28, lines 62-66; Each memory film 50 and each dummy memory film 50′ can include a layer stack of a blocking dielectric layer 52, a charge storage layer 54, and a tunneling dielectric layer 56, Col. 28, lines 25-40; FIGs. 10, 11, 12B show 52 lines the opening for each 50 which is part of a memory pillar 58, Col. 29, lines 37-45; Accordingly, a length in the vertical direction of each memory pillar 58 formed of 11 and 50 is substantially equal to a length in the vertical direction of each of the first pillars formed of 11 and 52).
RE: Claim 10, Pachamuthu discloses The memory device of claim 1, wherein each of the memory pillars includes a first portion included in a first tier (lower portion of 58 in lower tier of 146, 132 in FIG. 18) and a second portion included in a second tier (upper portion of 58 in upper tier of 246, 232 in FIG. 18) arranged in the second direction with the first tier (upper tier of 246, 232 is arranged in vertical direction with the lower tier of 146, 132 in FIG. 19), and a shape of a side surface of the first portion and a shape of a side surface of the second portion are discontinuous (FIGs. 15B, 19 show shape of side surface of lower portion of 58 and shape of side surface of upper portion of 58 are discontinuous).
RE: Claim 11, Pachamuthu discloses The memory device of claim 10, wherein each of the first pillars includes a first insulating member (52) continuously provided between the first tier and the second tier (Pachamuthu discloses a blocking dielectric layer 52, a charge storage layer 54, a tunneling dielectric layer 56, and an optional first semiconductor channel layer 601 can be sequentially deposited in the inter-tier support openings 19, Col. 23, lines 4-11; FIG. 10 shows 52 is deposited first in openings for support pillars 20 in FIG. 15B; As 50 is continuously provided between the lower tier of 146, 132 and the upper tier of 246, 232 in FIG. 15B, dielectric layer 52 is continuously provided between the lower tier of 146, 132 and the upper tier of 246, 232).
RE: Claim 12, Pachamuthu discloses The memory device of claim 10, further comprising a plurality of third pillars (uppermost support pillars 20 in 200 in FIG. 13B) arranged in the second region, each of the third pillars having a portion crossing at least one other first conductive layer (146 or 246) among the first conductive layers and including a second insulating member (52; Each support pillar structure 20 can comprise a dummy memory film 50′, Col. 29, lines 55-60; Each memory film 50 and each dummy memory film 50′ can include a layer stack of a blocking dielectric layer 52, a charge storage layer 54, and a tunneling dielectric layer 56, Col. 28, lines 25-40), wherein the second pillars are included in the second tier (second pillars of 54, 56 of 20 are included in upper tier of 246, 232 in FIG. 15A as they extend through 246, 146), and the third pillars are included in the first tier (third pillars of 20 are included in the lower tier of 146, 132 as they extend through 146, 132 in FIG. 15A).
RE: Claim 13, Pachamuthu discloses The memory device of claim 12, wherein each of the first pillars includes a third portion included in the first tier (lower portion of first pillars 52 of 20 in lower tier of 146, 132 in FIG. 15A) and a fourth portion included in the second tier (upper portion of first pillars 52 of 20 in upper tier of 246, 232 in FIG. 15A), and a shape of a side surface of the third portion and a shape of a side surface of the fourth portion are discontinuous (FIGs. 15B, 19 show a shape of side surface of lower portion of 20 and shape of side surface of upper portion of 20 are discontinuous; Accordingly, a shape of side surface of lower portion of first pillars 52 of 20 and a shape of side surface of upper portion of first pillars 52 of 20 are discontinuous).
RE: Claim 16, Pachamuthu discloses The memory device of claim 1, wherein each of the first pillars includes a first insulating member containing oxygen and silicon (dielectric layer 52 includes silicon oxide, Col. 23, lines 46-48).
RE: Claim 18, Pachamuthu discloses The memory device of claim 1, further comprising a plurality of second conductive layers (bit lines 98 in FIG. 19, Col. 35, lines 15-20) provided apart from the first conductive layers in the second direction and arranged in the first direction, each of the second conductive layers having a portion provided to extend in a third direction (horizontal direction hd2 in FIG. 17B) crossing the first direction and the second direction (As 98 are bit lines, 98 are three-dimensional and would extend in three orthogonal directions including the horizontal directions hd1 and hd2 in FIG. 13B), wherein each of the memory pillars is coupled to one second conductive layer among the second conductive layers (FIG. 19 shows each 58 is coupled to one of the bit lines 98), and any conductive layers apart from the first conductive layers in the second direction are not coupled to the second pillars (FIG. 19 shows that any conductive layers apart from the first conductive layers 146, 246 in the vertical direction are not directly coupled to 20 and therefore are not directly coupled to second pillars formed of 54, 56 of dummy memory film 50’ of 20).
RE: Claim 20, Pachamuthu discloses The memory device of claim 1, further comprising: a source layer (6 in FIG. 19, The planar conductive material layer 6 may function as a special source line, Col. 13, lines 30-35) provided apart from the plurality of first conductive layers in the second direction and connected to end portions (top or bottom end portions of 58) of the plurality of memory pillars.
RE: Claim 21, Pachamuthu discloses The memory device of claim 20, wherein end surfaces (top end surfaces of 50 of 58) of the plurality of memory pillars are aligned with end surfaces (top end surfaces of second pillars formed of 54, 56 of dummy 50’) of the plurality of second pillars (each 50 and each 50’ include 54, 56, Col. 28, lines 25-40; Accordingly, as top end surfaces of 50 and top end surfaces of 50’ are aligned in FIG. 15B, top end surfaces of 50 of 58 and top end surfaces of second pillars 54, 56 of dummy 50’ are aligned), the end surfaces of the plurality of memory pillars being distant from the source layer in the second direction (FIG. 19 shows top end surfaces of 50 of 58 are distant from 6 in the vertical direction), the end surfaces of the plurality of second pillars being distant from the source layer in the second direction (FIG. 19 shows top end surfaces of second pillars 54, 56 of 50’ are distant from 6 in the vertical direction).
Claim(s) 1, 14-15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pachamuthu.
Second Rejection of Claim 1:
RE: Claim 1, Pachamuthu discloses A memory device (device in FIG. 19) comprising:
a substrate (8) including a first region (100 in FIG. 13B), a second region (right region of 200 in FIG. 13B, which is the right part of 200 that is vertically delineated by the rightmost edge of 165 in FIG. 18), and a third region (left region of 200 in FIG. 13B which is the left part of 200 that is vertically delineated by the rightmost edge of 165 in FIG. 18) arranged in order in a first direction (horizontal direction hd1 in FIG. 13B);
a plurality of first conductive layers (146, 246 in FIG. 19, Col. 33, lines 33-35) provided apart from the substrate in a second direction (vertical direction in FIG. 19) crossing the first direction and arranged in the second direction;
a plurality of memory pillars (memory fill structures 58 in FIG. 19, Col. 29, lines 37-40) provided in the first region, each of the memory pillars having a portion crossing the first conductive layers and including a stacked film (50 shown in FIG. 15B; Each memory opening fill structure 58 comprises a vertical semiconductor channel 60 and a memory film 50, Col. 29, lines 37-45; Each memory film 50 can comprise a layer stack including a tunneling dielectric layer 56, a charge storage layer 54, and a blocking dielectric layer 52, Col. 29, lines 55-60);
a plurality of first pillars (dielectric cores 62’ which are part of 20 extending through 246 and 146 in FIGs. 15A-15B, Col. 29, lines 8-15) provided in the second region and the third region (20 is in left and right regions of 200 in FIG. 13B), each of the first pillars having a portion crossing at least one of the first conductive layers (246 or 146) and having a configuration different from a configuration of each of the memory pillars (FIG. 13B shows 20 has configuration different from a configuration of 58 in that 20 are spaced farther apart from each other than 58; Accordingly, 62’ in 20 has configuration different from a configuration of 58 in that 62’ in 20 are spaced farther apart from each other than 58); and
a plurality of second pillars (dummy memory films 50’ of 20 extending through 146 and 246 in FIGs. 15A, 15B; see also FIGs. 10, 11, 12A-12B) provided in the second region, each of the second pillars having a portion crossing at least one first conductive layer (146 or 246) among the first conductive layers and including the stacked film (Each memory film 50 and each dummy memory film 50′ can include a layer stack of a blocking dielectric layer 52, a charge storage layer 54, and a tunneling dielectric layer 56, Col. 28, lines 25-40; Each support pillar structure 20 can comprise a dummy memory film 50′ including a dummy tunneling dielectric layer having a same thickness and a same composition as the tunneling dielectric layer 56, a dummy charge storage layer having a same thickness and a same composition as the charge storage layer 54, and a dummy blocking dielectric layer having a same thickness and a same composition as the blocking dielectric layer 52, Col. 29, lines 55-60).
RE: Claim 14, Pachamuthu discloses The memory device of claim 1, wherein each of the memory pillars further includes a semiconductor layer (60 of 50; Each memory opening fill structure 58 comprises a vertical semiconductor channel 60 and a memory film 50, Col. 29, lines 37-45), and the stacked film includes a tunnel insulating film surrounding a side surface of the semiconductor layer, a charge storage layer surrounding a side surface of the tunnel insulating film, and a block insulating film surrounding a side surface of the charge storage layer (Each memory film 50 and each dummy memory film 50′ can include a layer stack of a blocking dielectric layer 52, a charge storage layer 54, and a tunneling dielectric layer 56, Col. 28, lines 25-40; FIG. 15B shows a tunnel insulating film 56 surrounding a side surface of the semiconductor layer 60, a charge storage layer 54 surrounding a side surface of the tunnel insulating film 56, and a block insulating film 52 surrounding a side surface of the charge storage layer 54).
RE: Claim 15, Pachamuthu discloses The memory device of claim 14, wherein a film thickness of the stacked film included in each of the second pillars and a film thickness of the stacked film included in each of the memory pillars are substantially same (Each memory film 50 and each dummy memory film 50′ can include a layer stack of a blocking dielectric layer 52, a charge storage layer 54, and a tunneling dielectric layer 56, Col. 28, lines 25-40; Each support pillar structure 20 can comprise a dummy memory film 50′ including a dummy tunneling dielectric layer having a same thickness and a same composition as the tunneling dielectric layer 56, a dummy charge storage layer having a same thickness and a same composition as the charge storage layer 54, and a dummy blocking dielectric layer having a same thickness and a same composition as the blocking dielectric layer 52, Col. 29, lines 55-60).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pachamuthu as applied to claim 1 (in the first rejection of claim 1), further in view of US20240074214A1 (“Okada”)
RE: Claim 19, Pachamuthu does not explicitly disclose The memory device of claim 1, further comprising a third conductive layer and a fourth conductive layer provided between the substrate and the first conductive layers and arranged to face each other in the second direction, wherein the substrate is provided with a control circuit electrically connected to the memory pillars via the third conductive layer and the fourth conductive layer, and the third conductive layer and the fourth conductive layer have tapered shapes different from each other.
In the same field of endeavor, Okada discloses a memory device (memory die MD in FIG. 8, [0011]) including:
a third conductive layer (bonding electrode PI1, [0117]) and a fourth conductive layer (bonding electrode PI2, [0117]) provided between a substrate (200) and first conductive layers (word lines 110, [0140]) and arranged to face each other in a second direction (vertical direction in FIG. 8),
wherein the substrate is provided with a control circuit (peripheral circuit PC including transistors Tr; semiconductor substrate region 200S function as parts of a plurality of transistors Tr, a plurality of capacitors, and the like constituting the peripheral circuit PC. Note that a part of the plurality of transistors Tr function as the word line switches WLSW and the select gate line switches SGSW, [0170]; As the transistors Tr are switches for the word lines and select gate lines, the transistors Tr are considered control circuitry for the word lines and select gate lines) electrically connected to the memory pillars via the third conductive layer and the fourth conductive layer (Each of these plurality of memory strings MS has one end connected to the peripheral circuit PC via a bit line BL, [0083]; The bonding electrode PI1 and the bonding electrode PI2 function as bonding electrodes to bond the chip CM and the chip CP together to electrically conduct the chip CM and the chip CP, [0118]; Accordingly, the bonding electrodes PI1 and PI2 electrically connect the transistors Tr in the peripheral circuit PC in the chip Cp to the bit lines BL which are electrically connected to the semiconductor layers 120 of the memory cells in FIG. 8, [0141]), and the third conductive layer and the fourth conductive layer have tapered shapes different from each other (FIG. 8 shows bonding electrode PI1 -is tapered in the upward vertical direction and the bonding electrode PI2 is tapered in the downward vertical direction; therefore, the bonding electrode PI1 - and the bonding electrode PI2 have tapered shapes different from each other).
Okada further discloses the width in the Y-direction of the passing wiring that transmits the voltage (what is referred to as a power line) can be configured to be large, and the width in the Y-direction of the passing wiring that transmits the control signal (what is referred to as a signal line) can be configured to be small. As a result, the signal can be surely transmitted by the passing wiring, and the stability of the operation of the peripheral circuit PC can be achieved, [0303].
It would have been obvious to one of ordinary skill in the art to provide a third conductive layer and a fourth conductive layer having different tapered shapes and to modify the substrate 8 to include a control circuit electrically connected to the memory pillars 58 via the third conductive layer and the fourth conductive layer as taught by Okada in order to control operation of the memory pillars and to achieve stability in the control circuit.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL ANGUIANO whose telephone number is (703)756-1226. The examiner can normally be reached Monday through Friday.
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/MICHAEL ANGUIANO/Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899
Prosecution Insights