Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
In response to the Communications dated September 10, 2024, claims 1-20 are active in
this application.
Specification
If there are cross-reference to related applications, please include the
respective patent numbers, if known.
Information Disclosure Statement
The information disclosure statements filed September 10, 2024 have been considered.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-5 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3, 5 and 6 of U.S. Patent No. 12112793 [‘793]. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following reason.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows.
Present Application
Patent ‘793
1. A method comprising: storing, at a buffer of a logic die that is bonded to a memory die via a wafer-on-wafer bonding process, signals indicative of input data from a global data bus of the memory die and through a bond of the logic die and the memory die; receiving, at the logic die, signals indicative of kernel data from local input/output (LIO) lines of the memory die and through the bond; performing, at the logic die, a plurality of operations utilizing the signals indicative of input data and the signals indicative of kernel data; and providing results of the plurality of operations to the buffer based on a mode of the logic die and a type of the plurality of operations, wherein the mode of the logic die is used to identify the type of the plurality of operations.
1. A method comprising: storing, at a buffer of a logic die that is bonded to a memory die via a wafer-on-wafer bonding process, signals indicative of input data from a global data bus of the memory die and through a bond of the logic die and the memory die; receiving, at the logic die, signals indicative of kernel data from local input/output (LIO) lines of the memory die and through the bond; performing, at the logic die, a plurality of operations at a plurality of vector-vector (VV) units utilizing the signals indicative of input data and the signals indicative of kernel data; and providing results of the plurality of operations to the buffer based on a mode of the logic die and a type of the plurality of operations, wherein the mode of the logic die is used to identify the type of the plurality of operations.
2. The method of claim 1, further comprising storing the signals indicative of the input data to the buffer and receiving the signals indicative of the kernel data from the LIO lines based on the type of the plurality of operations.
2. The method of claim 1, further comprising storing the signals indicative of the input data to the buffer and receiving the signals indicative of the kernel data from the LIO lines based on the type of the plurality of operations.
3. The method of claim 1, further comprising providing the results from the buffer to the memory die via the bond.
3. The method of claim 1, further comprising providing the results from the buffer to the memory die via the bond.
4. The method of claim 1, wherein the input data comprises a quantity of bits that is less than or equal to a different quantity of bits that comprises the kernel data.
5. The method of claim 1, wherein the input data comprises a quantity of bits that is less than or equal to a different quantity of bits that comprises the kernel data.
5. The method of claim 1, wherein the input data comprises a same quantity of bits as each of a number of portions of the kernel data.
6. The method of claim 1, wherein the input data comprises a same quantity of bits as each of a number of portions of the kernel data.
As can be seen from the above table, similar to claim 1 of the present application, claim 1 of patent ‘793 recites “A method comprising: storing, at a buffer of a logic die that is bonded to a memory die via a wafer-on-wafer bonding process, signals indicative of input data from a global data bus of the memory die and through a bond of the logic die and the memory die; receiving, at the logic die, signals indicative of kernel data from local input/output (LIO) lines of the memory die and through the bond; performing, at the logic die, a plurality of operations utilizing the signals indicative of input data and the signals indicative of kernel data; and providing results of the plurality of operations to the buffer based on a mode of the logic die and a type of the plurality of operations, wherein the mode of the logic die is used to identify the type of the plurality of operations." Unlike claim 1 of the present application, claim 1 recites that process included “a plurality of vector-vector (VV) units “. However, since the claim of the patent is more limited, it would encompass all limitations of the claim of the present application. Therefore, the patent protections have been granted to the earlier filed patent application.
For similar reasons, claims 2-5 are rejected over claims 1-3, 5 and 6 of patent ‘793.
Claims 6-16 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 7-19 of U.S. Patent No. 12112793 [‘793]. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following reason.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows.
Present Application
Patent ‘793
6. An apparatus, comprising: a memory die; a logic die bonded to the memory die via a wafer-to-wafer bonding process; wherein the logic die comprises a plurality of units configured to: receive signals indicative of kernel data from a global data bus (GBUS) of the memory die and through a bond of the logic die and the memory die; receive signals indicative of input data from local input/output (LIO) lines of the memory die and through the bond; perform a plurality of operations using the signals indicative of kernel data and the signals indicative of input data; and provide a plurality of results of the plurality of operations to the LIO lines of the memory die based on a mode of the logic die utilizing a plurality of multiplexors (MUXs).
7. An apparatus, comprising: a memory die; a logic die bonded to the memory die via a wafer-to-wafer bonding process; wherein the logic die comprises a plurality of vector-vector (VV) units configured to: receive signals indicative of kernel data from a global data bus (GBUS) of the memory die and through a bond of the logic die and the memory die; receive signals indicative of input data from local input/output (LIO) lines of the memory die and through the bond; perform a plurality of operations using the signals indicative of kernel data and the signals indicative of input data; and provide a plurality of results of the plurality of operations to the LIO lines of the memory die based on a mode of the logic die utilizing a plurality of multiplexors (MUXs).
7. The apparatus of claim 6, wherein the logic die is further configured to provide a result, from the plurality of results, of a unit, from the plurality of units, via a MUX, from the plurality of MUXs, coupled to the unit.
8. The apparatus of claim 7, wherein the logic die is further configured to provide a result, from the plurality of results, of a VV unit, from the plurality of VV units, via a MUX, from the plurality of MUXs, coupled to the VV unit.
8. The apparatus of claim 6, wherein each unit from the plurality of units is coupled to a different MUX from the plurality of MUXs and is configured to provide an output to the different MUX.
9. The apparatus of claim 7, wherein each VV unit from the plurality of VV units is coupled to a different MUX from the plurality of MUXs and is configured to provide an output to the different MUX.
9. The apparatus of claim 6, wherein the logic die is configured to provide the signals indicative of the input data to each of the plurality of units based on the mode of the logic die utilizing a different plurality of MUXs.
11. The apparatus of claim 7, wherein the logic die is configured to provide the signals indicative of the input data to each of the plurality of VV units based on the mode of the logic die utilizing a different plurality of MUXs.
10. The apparatus of claim 9, wherein each of the different plurality of MUXs is configured to provide a different portion of the input data to each of the plurality of units.
12. The apparatus of claim 11, wherein each of the different plurality of MUXs is configured to provide a different portion of the input data to each of the plurality of VV units.
11. The apparatus of claim 9, wherein a quantity of the different plurality of MUXs is less than a quantity of the plurality of MUXs.
13. The apparatus of claim 11, wherein a quantity of the different plurality of MUXs is less than a quantity of the plurality of MUXs.
12. The apparatus of claim 9, wherein a quantity of the different plurality of MUXs is less than a quantity of the plurality of units.
14. The apparatus of claim 11, wherein a quantity of the different plurality of MUXs is less than a quantity of the VV units.
13. The apparatus of claim 6, wherein a quantity of the plurality of units is equal to a quantity of the plurality of MUXs.
15. The apparatus of claim 7, wherein a quantity of the VV units is equal to a quantity of the plurality of MUXs.
14. The apparatus of claim 6, wherein the plurality of units is configured to provide the plurality of results of the plurality of operation to the LIO lines via the bond.
16. The apparatus of claim 7, wherein the plurality of VV units is configured to provide the plurality of results of the plurality of operation to the LIO lines via the bond.
15. The apparatus of claim 6, wherein the logic die is configured to: receive the signals indicative of the kernel data and the signals indicative of the input data via a plurality of lines generated via the wafer-on-wafer bonding process that couple the LIO lines and the GBUS to through silicon vias (TSVs); and wherein the plurality of units is further configured to receive the signals indicative of the kernel data and the signals indicative of the input data from the TSVs.
17. The apparatus of claim 7, wherein the logic die is configured to receive the signals indicative of the kernel data and the signals indicative of the input data via a plurality of lines generated via the wafer-on-wafer bonding process that couple the LIO lines and the GBUS to through silicon vias (TSVs).
18. The apparatus of claim 17, wherein the plurality of VV units is further configured to receive the signals indicative of the kernel data and the signals indicative of the input data from the TSVs.
16. The apparatus of claim 6, wherein each of the plurality of units are further configured to receive the signals indicative of the input data via from a different section of a bank of the memory die via different LIO lines coupled to the different section.
19. The apparatus of claim 7, wherein each of the plurality of VV units are further configured to receive the signals indicative of the input data via from a different section of a bank of the memory die via different LIO lines coupled to the different section.
As can be seen from the above table, similar to claim 6 of the present application, claim 7 of patent ‘793 recites “An apparatus, comprising: a memory die; a logic die bonded to the memory die via a wafer-to-wafer bonding process; wherein the logic die comprises a plurality of units configured to: receive signals indicative of kernel data from a global data bus (GBUS) of the memory die and through a bond of the logic die and the memory die; receive signals indicative of input data from local input/output (LIO) lines of the memory die and through the bond; perform a plurality of operations using the signals indicative of kernel data and the signals indicative of input data; and provide a plurality of results of the plurality of operations to the LIO lines of the memory die based on a mode of the logic die utilizing a plurality of multiplexors (MUXs)." Unlike claim 6 of the present application, claim 7 recites that process included “a plurality of vector-vector (VV) units “. However, since the claim of the patent is more limited, it would encompass all limitations of the claim of the present application. Therefore, the patent protections have been granted to the earlier filed patent application.
For similar reasons, claims 7-16 are rejected over claims 7-19 of patent ‘793.
Claims 17-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 20-25 of U.S. Patent No. 12112793 [‘793]. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following reason.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows.
Present Application
Patent ‘793
17. An apparatus, comprising: a memory die; a logic die bonded to the memory die via a wafer-to-wafer bonding process; wherein the logic die comprises a plurality of units configured to: receive signals, at a buffer, indicative of first data from a global data bus (GBUS) of the memory die and through bond of the logic die and the memory die; receive signals, at the plurality of units, indicative of second data from local input/output (LIO) lines of the memory die and through the bond; perform a first plurality of operations using the signals indicative of the first data and the signals indicative of the second data to generate a plurality of outputs; store the plurality of outputs to the buffer based on the logic die being in a first mode; and provide the plurality of outputs to the memory die via the LIO lines based on the logic die being in a second mode.
20. An apparatus, comprising: a memory die; a logic die bonded to the memory die via a wafer-to-wafer bonding process; wherein the logic die comprises a plurality of vector-vector (VV) units configured to: receive signals, at a buffer, indicative of first data from a global data bus (GBUS) of the memory die and through bond of the logic die and the memory die; receive signals, at the plurality of VV units, indicative of second data from local input/output (LIO) lines of the memory die and through the bond; perform a first plurality of operations using the signals indicative of the first data and the signals indicative of the second data to generate a plurality of outputs; store the plurality of outputs to the buffer based on the logic die being in a first mode; and provide the plurality of outputs to the memory die via the LIO lines based on the logic die being in a second mode.
18. The apparatus of claim 17, wherein the plurality of units is further configured to: provide a portion of the plurality of outputs to a portion of the plurality of units based on the logic die being in a third mode; and provide the plurality of outputs to the buffer based on the logic die being in the third mode.
21. The apparatus of claim 20, wherein the VV units is further configured to: provide a portion of the plurality of outputs to a portion of the VV units based on the logic die being in a third mode; and provide the plurality of outputs to the buffer based on the logic die being in the third mode.
19. The apparatus of claim 17, wherein the plurality of units is further configured to: provide the portion of the plurality of outputs to the portion of the plurality of units utilizing a first plurality of multiplexors (MUXs) configured using the third mode; and provide the plurality of outputs to the buffer utilizing a second plurality of MUXs configured using the third mode.
22. The apparatus of claim 20, wherein the VV units are further configured to provide the portion of the plurality of outputs to the portion of the VV units utilizing a first plurality of multiplexors (MUXs) configured using the third mode.
23. The apparatus of claim 22, wherein the VV units are further configured to provide the plurality of outputs to the buffer utilizing a second plurality of MUXs configured using the third mode.
20. The apparatus of claim 19, wherein the plurality of units is configured to: store the plurality of outputs to the buffer utilizing the second plurality of MUXs configured utilizing the first mode; and provide the plurality of outputs to the memory die utilizing the second plurality of MUXs configured utilizing the second mode.
24. The apparatus of claim 23, wherein the VV units are configured to store the plurality of outputs to the buffer utilizing the second plurality of MUXs configured utilizing the first mode.
25. The apparatus of claim 23, wherein the VV units are configured to provide the plurality of outputs to the memory die utilizing the second plurality of MUXs configured utilizing the second mode.
As can be seen from the above table, similar to claim 17 of the present application, claim 20 of patent ‘793 recites “An apparatus, comprising: a memory die; a logic die bonded to the memory die via a wafer-to-wafer bonding process; wherein the logic die comprises a plurality of units configured to: receive signals, at a buffer, indicative of first data from a global data bus (GBUS) of the memory die and through bond of the logic die and the memory die; receive signals, at the plurality of units, indicative of second data from local input/output (LIO) lines of the memory die and through the bond; perform a first plurality of operations using the signals indicative of the first data and the signals indicative of the second data to generate a plurality of outputs; store the plurality of outputs to the buffer based on the logic die being in a first mode; and provide the plurality of outputs to the memory die via the LIO lines based on the logic die being in a second mode." Unlike claim 17 of the present application, claim 20 recites that process included “a plurality of vector-vector (VV) units “. However, since the claim of the patent is more limited, it would encompass all limitations of the claim of the present application. Therefore, the patent protections have been granted to the earlier filed patent application.
For similar reasons, claims 18-20 are rejected over claims 20-25 of patent ‘793.
Claim Rejections- 35 U.S.C. § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kumar et al. [WO 2020242781 A1].
With respect to claim 1, Kumar et al. disclose a method comprising: storing, at a buffer of a logic die that is bonded to a memory die via a wafer-on-wafer bonding [“The two dies are wafer-to-wafer bonded or coupled via micro-bumps.” – Abstract] process [“ The second die can be an inference die that applies fixed weights for a trained model to an input data to generate an output. In some embodiments, the second die includes processing cores (or processing entities (PEs)) that have matrix multipliers, adders, buffers, etc.” – par. 0036 (it is noted that an "inference die" with matrix multipliers and adders is a specialized type of logic die, making the "second die" in context of Kumar et al., a "logic die" in context the claimed recitation. Additionally, the inclusion of buffers within the die architecture specifically enables the storing of input data or weights necessary for the inference process. Further, the compute die 402 and memory die 401 are bonded via micro bumps 403 – see fig. 4a], signals indicative of input data ["memory of the first die may store input data" - par. 0036 (establishes that the memory die holds the input data, which must be signaled to the logic die for processing. ) from a global data bus of the memory die ["DRAM below the compute die... (or other memories)" + "...second die includes processing cores... [with] buffers" - par. 0036 (To move large amounts of data (input/weights) to PEs, it must traverse the memory die's internal bus structure before exiting the die. ) and through a bond ["...computational logic of the second die is coupled to the memory of the first die" - par. 0036 (3D stacking implies vertical coupling via bonding (e.g., TSVs, micro-bumps). "Coupled" is the functional requirement for a bond. ) of the logic die and the memory die ["DRAM below the compute die" / "second die [inference die]... [over] the first die" – par. 0036 (Confirms the physical stacking of a logic die (second) on top of a memory die (first).); receiving, at the logic die, signals indicative of kernel data from local input/output (LIO) lines of the memory die and through the bond ["...supplemented with other fast access memories... The memory of the first die may store... weight factors [kernel data]." – par. 0036 (Kernel data" (weights) is identified as being stored in the first die in A. High-speed, low-latency access (implied by "fast access memories" in A) requires Local I/O (LIO) routing.); performing, at the logic die, a plurality of operations utilizing the signals indicative of input data and the signals indicative of kernel data ("The second die can be an inference die that applies fixed weights for a trained model to an input data... includes processing cores... that have matrix multipliers, adders, buffers, etc." – par. 0036 (explicitly states the second die (logic) uses weight factors (kernels) and input data to perform operations (matrix multiplication/addition for inference).); and providing results of the plurality of operations to the buffer based on a mode of the logic die and a type of the plurality of operations, wherein the mode of the logic die is used to identify the type of the plurality of operations ["In some embodiments, the second die includes processing cores... that have matrix multipliers, adders, buffers, etc." – par. 0036 (describes the hardware (buffers, PEs) necessary to store and process the results, which in a flexible, configurable inference die (as mentioned) requires a "mode" or control signal to define how the operations are done.).
With respect to claim 2, Kumar et al. disclose storing the signals indicative of the input data to the buffer ["...memory of the first die may store input data..." AND "...second die includes... buffers" – par. 0036 (establishes that input data lives in the first die, and the second die has buffers for processing, implying that input data is loaded into these buffers.) and receiving the signals indicative of the kernel data from the LIO lines ["...computational logic of the second die is coupled to the memory of the first die" – par. 0036 (While "LIO" isn't explicitly mentioned, the coupling (via TSVs/Vertical links) enables moving weight factors (kernel data) from memory to compute.) based on the type of the plurality of operations ["...second die can be an inference die... second die includes processing cores... that have matrix multipliers, adders..." – par. 0036 (An inference die performing matrix multiplication inherently adapts its data fetching based on the operation type).
With respect to claim 3, Kumar et al. disclose providing the results from the buffer to the memory die ["...DRAM below the compute die...", "...memory of the first die...", "...coupled to..."… "...second die includes processing cores... that have... buffers..." – par. 0036 (Kumar et al. establishes a 3D-stacked architecture where a "memory die" (first die) is positioned below a "compute die" (second die), and they are "coupled" (connected). Additionally, Kumar et al. establishes that the computational logic (second die) processes data and utilizes buffers for data management.] via the bond ["...coupled to the memory of the first die." – par. 0036 ("Coupled" in a 3D stacking context implies physical bonding (microbumps, hybrid bonding, or through-silicon vias/TSVs) to connect the logic/buffer on the top die to the memory on the bottom die. Also, see fig. 4a).
Conclusion
For applicant’s benefit portions of the cited reference(s) have been cited to aid in
the review of the rejection(s). While every attempt has been made to be thorough and consistent within the rejection it is noted that the PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS. See MPEP 2141.02 VI.
When responding to the Office action, Applicants are advised to provide
the Examiner with line and page numbers of the application and/or references cited to assist the Examiner in the prosecution of this case.
Any inquiry concerning this communication or earlier communications
from the Examiner should be directed to Michael T. Tran whose telephone number is (571) 272-1795. Interview agendas may be emailed to Michael.tran@uspto.gov. The Examiner can normally be reached on Monday-Thursday from 6:00AM-4:30 P.M.
Any inquiry of a general nature or relating to the status of this application.
should be directed to the Group receptionist whose telephone number is (571) 272-1650.
/MICHAEL T TRAN/Primary Examiner, Art Unit 2827 February 24, 2026