DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement(s)
The Information Disclosure Statement(s) filed on October 17, 2024 were considered by the Examiner.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference characters "197" and "198" have both been used to designate the “source/drain contact” in FIGs. 26-27, 30, 31, 34 which show the same contact directly on source/drain region 132 but labeled with different reference characters. As “198” does not appear to be in the instant specification, it is believed “198” is a typographical error of “197.”
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 5-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over US20240363491A1 (“Yun”) in view of US20260026091A1 (“Kim”).
RE: Claim 1, Yun discloses A microelectronic structure (1000 in FIG. 10) comprising:
a first nanosheet FET (second transistor including the second source/drain region 112 b and a third source/drain region 112 c, [0023]; each of the first, second, and third transistors may be a gate-all-around (GAA) transistor including a single channel region or a fin-shaped field-effect transistor (FinFET), [0022]; each of the first, second, and third channel regions 106 a, 106 b, and 106 c may be a nanosheet, [0024]) that includes a first source/drain (112c);
a second nanosheet FET (first transistor including first and second source/ drain regions 112 a and 112 b, [0023]) located adjacent to the first nanosheet FET;
a first backside contact (combination of 122 and 1024, [0034], [0057]; substrate 102 is also referred to as a backside insulator, [0017]; Accordingly, 122, 1024 are in a backside region and therefore in combination considered a first backside contact) connected to the first source/drain (112c), wherein the first backside contact extends through a backside region of the second nanosheet FET (FIG. 10 shows 1024 extending through a backside region of 112b which is part of the second nanosheet FET).
Yun does not explicitly disclose:
the first nanosheet FET includes a second source/drain;
a second backside contact connected to the second source/drain, wherein the first backside contact and the second backside contact are located on the same level.
In the same field of endeavor, Kim discloses in FIG. 2C:
a first FET (100A; 100A is a gate-all-around type field effect transistor, [0034]; Gate-All-Around field effect transistors include nanosheets surrounded by gates, [0003]; 100A is a pFET or nFET, [0038]) includes a first source/drain and a second source/drain (Annotated FIG. 2C shows first left source/drain 150 and second right source/drain 150 separated by separation pattern 320 which is dielectric, [0056]; the second separation pattern 320 may have a constant width in the first x-direction and/or the y-second direction, [0044], [0023]-[0024]; FIG. 1 shows top view where separation pattern 320 completely separates portions of source/drains 150);
a first backside contact (left 270A in Annotated FIG. 2C below; 270A is a backside contact plug, [0036]) connected to the first source/drain (left 150 in Annotated FIG. 2C below);
a second backside contact (right 270A in Annotated FIG. 2C below) connected to the second source/drain (right 150 in Annotated FIG. 2C below), wherein the first backside contact and the second backside contact are located on the same level (Annotated FIG. 2C below shows the first backside contact and the second backside contact are located on the same level).
Kim discloses by forming the first and second separation patterns 310 and 320 including a low dielectric constant material during the backside process for forming the backside contact structure 270, the parasitic voltage problem within the semiconductor device may be improved (e.g., reduced), and accordingly, a semiconductor device with improved reliability and electrical characteristics may be provided, [0046].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a second source/drain, and
a second backside contact connected to the second source/drain as taught by Kim in order to improve reliability and improve a parasitic voltage problem as further taught by Kim.
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RE: Claim 5, Yun in view of Kim discloses The microelectronic structure of claim 1, wherein the second nanosheet FET includes a third source/drain (Yun FIG. 10: 112b, [0023]).
RE: Claim 6, Yun in view of Kim discloses The microelectronic structure of claim 5, wherein the first backside contact extends through a backside region of the third source/drain (Yun FIG. 10 shows 1024 extends through a backside region of the third source/drain 112b).
RE: Claim 7, Yun in view of Kim discloses The microelectronic structure of claim 6, wherein the first backside contact bypasses the third source/drain (Yun FIG. 10 shows 1024 bypasses the third source/drain 112b).
Claim(s) 2-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yun in view of Kim as applied to claim 1, further in view of US20230207553A1 (“Xie”).
RE: Claim 2, Yun in view of Kim discloses The microelectronic structure of claim 1, further comprising:
a second metal line (In Yun FIG. 10: power rail 120; 120 includes metal, [0043]) located adjacent to the second nanosheet FET (Yun FIG. 10 shows 120 adjacent to each of the first and second FETs that include 112a, 112b, 112c, [0023]; the word “adjacent” is further discussed below).
Yun in view of Kim does not explicitly disclose:
a first metal line located adjacent to the first nanosheet FET.
In the same field of endeavor, Xie discloses in FIG. 1A:
a first metal line (194, [0049]) located adjacent to a first nanosheet FET (120-1 or 120-2, [0044]);
a second metal line (196, [0048]; power rails can be formed using metallic material, [0099]) located adjacent to a second nanosheet FET (120-3 or 120-4, [0044]).
Further, the word “adjacent” is not defined in the instant specification. The word “adjacent” is defined as “not distant : nearby,” see definition 1b by Merriam-Webster’s dictionary. Accordingly, in the integrated circuit device 100 in FIG. 1A of Xie, each of the power rails 194, 196 is nearby and therefore adjacent to each of the FETs 120-1, 120-2, 120-3, 120-4.
FIG. 1A shows source/drain contacts 181, 182 are connected to power rails 194, 196, respectively.
Xie further discloses The backside power distribution network 198 comprises one or more levels wiring that are configured to distribute positive power supply voltage (e.g., VDD) and negative power supply voltage (e.g., VSS, ground (GND)=0V) to the backside power rails 194 and 196, [0050].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a first metal line as taught by Xie in order to distribute power to the second backside contact. As modified, Xie’s first metal power rail and Yun’s power rail 120 would be adjacent to Yun’s first and second FETs that include 112a, 112b, 112c, [0023].
RE: Claim 3, Yun in view of Kim, Xie discloses The microelectronic structure of claim 2, wherein the second backside contact is connected to the first metal line (As modified, Yun’s first backside contact 122, 1024 is connected to Yun’s second metal line 120, and Kim’s second backside contact is connected to Xie’s first metal line).
RE: Claim 4, Yun in view of Kim, Xie discloses The microelectronic structure of claim 3, wherein the first backside contact is connected to the second metal line (As modified, Yun’s first backside contact 122, 1024 is connected to Yun’s second metal line 120).
Claim(s) 8 and 12-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yun in view of Kim.
RE: Claim 8, Yun discloses A microelectronic structure (1000 in FIG. 10) comprising:
a first nanosheet FET (second transistor including the second source/drain region 112 b and a third source/drain region 112 c, [0023]; each of the first, second, and third transistors may be a gate-all-around (GAA) transistor including a single channel region or a fin-shaped field-effect transistor (FinFET), [0022]; each of the first, second, and third channel regions 106 a, 106 b, and 106 c may be a nanosheet, [0024]) that includes a first source/drain (112c);
a second nanosheet FET (first transistor including first and second source/ drain regions 112 a and 112 b, [0023]) located adjacent to the first nanosheet FET;
a first backside contact (combination of 122 and 1024, [0034], [0057]; substrate 102 is also referred to as a backside insulator, [0017]; Accordingly, 122, 1024 are in a backside region and therefore in combination considered a first backside contact) connected to the first source/drain, wherein the first backside contact extends through a backside region of the second nanosheet FET (FIG. 10 shows 1024 extending through a backside region of 112b which is part of the second nanosheet FET).
Yun does not explicitly disclose:
the first nanosheet FET includes a second source/drain;
a second backside contact connected to the second source/drain, wherein the first backside contact and the second backside contact are located on the same level; and
a dielectric pillar located between the first backside contact and the second backside contact.
In the same field of endeavor, Kim discloses in FIG. 2C:
a first FET (100A; 100A is a gate-all-around type field effect transistor, [0034]; Gate-All-Around field effect transistors include nanosheets surrounded by gates, [0003]; 100A is a pFET or nFET, [0038]) includes a first source/drain and a second source/drain (Annotated FIG. 2C shows first left source/drain 150 and second right source/drain 150 separated by separation pattern 320 which is dielectric, [0056]; the second separation pattern 320 may have a constant width in the first x-direction and/or the y-second direction, [0044], [0023]-[0024]; FIG. 1 shows top view where separation pattern 320 completely separates portions of source/drains 150);
a first backside contact (left 270A in Annotated FIG. 2C below; 270A is a backside contact plug, [0036]) connected to the first source/drain (left 150 in Annotated FIG. 2C below);
a second backside contact (right 270A in Annotated FIG. 2C below) connected to the second source/drain (right 150 in Annotated FIG. 2C below), wherein the first backside contact and the second backside contact are located on the same level (Annotated FIG. 2C below shows the first backside contact and the second backside contact are located on the same level);
a dielectric pillar (320, 320 includes a low dielectric constant material, [0046]; the second separation pattern 320 may include a low-κ dielectric material instead of the air gap AG2, [0056]; FIG. 3C shows separation pattern 320a composed of 322a, 321a which are dielectric, [0100]) located between the first backside contact and the second backside contact.
Further, Kim discloses that silicon oxide has a dielectric constant, [0026], and therefore silicon oxide is a dielectric material.
Kim discloses by forming the first and second separation patterns 310 and 320 including a low dielectric constant material during the backside process for forming the backside contact structure 270, the parasitic voltage problem within the semiconductor device may be improved (e.g., reduced), and accordingly, a semiconductor device with improved reliability and electrical characteristics may be provided, [0046].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a second source/drain,
a second backside contact connected to the second source/drain, and a dielectric pillar as taught by Kim in order to improve reliability and improve a parasitic voltage problem as further taught by Kim.
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RE: Claim 12, Yun in view of Kim discloses The microelectronic structure of claim 8, wherein the second nanosheet FET includes a third source/drain (Yun FIG. 10: 112b, [0023]).
RE: Claim 13, Yun in view of Kim discloses The microelectronic structure of claim 12, wherein the first backside contact extends through a backside region of the third source/drain (Yun FIG. 10 shows 1024 extends through a backside region of the third source/drain 112b).
RE: Claim 14, Yun in view of Kim discloses The microelectronic structure of claim 13, wherein the first backside contact bypasses the third source/drain (Yun FIG. 10 shows 1024 bypasses the third source/drain 112b).
RE: Claim 15, Yun in view of Kim discloses The microelectronic structure of claim 8,
wherein the first backside contact is in direct contact with a first side of the dielectric pillar (Annotated FIG. 2C of Kim above shows the first left backside contact 270A is in direct contact with a first left side of the dielectric pillar 320; Accordingly as modified, Yun’s first backside contact 122, 1024 would be in direct contact with a first side of Kim’s dielectric pillar),
wherein the second backside contact is in direct contact with a second side of the dielectric pillar (Annotated FIG. 2C of Kim above shows the second right backside contact 270A is in direct contact with a second right side of the dielectric pillar 320; Accordingly as modified, Kim’s second backside contact would be in direct contact with a second side of Kim’s dielectric pillar),
wherein the first side of the dielectric pillar and the second side of the dielectric pillar are different sides (Annotated FIG. 2C of Kim above shows the first left side of 320 and the second right side of 320 are different sides of 320; Accordingly, as modified the first and second sides of Kim’s dielectric pillar are different sides).
Claim(s) 9-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yun in view of Kim as applied to claim 8, further in view of Xie.
Re: Claim 9, Yun in view of Kim discloses The microelectronic structure of claim 8, further comprising:
a second metal line (In Yun FIG. 10: power rail 120; 120 includes metal, [0043]) located adjacent to the second nanosheet FET.
Yun in view of Kim does not explicitly disclose:
a first metal line located adjacent to the first nanosheet FET.
In the same field of endeavor, Xie discloses in FIG. 1A:
a first metal line (194, [0049]) located adjacent to a first nanosheet FET (120-1 or 120-2, [0044]);
a second metal line (196, [0048]; power rails can be formed using metallic material, [0099]) located adjacent to a second nanosheet FET (120-3 or 120-4, [0044]).
Further, the word “adjacent” is not defined in the instant specification. The word “adjacent” is defined as “not distant : nearby,” see definition 1b by Merriam-Webster’s dictionary. Accordingly, in the integrated circuit device 100 in FIG. 1A of Xie, each of the power rails 194, 196 is nearby and therefore adjacent to each of the FETs 120-1, 120-2, 120-3, 120-4.
FIG. 1A shows source/drain contacts 181, 182 are connected to power rails 194, 196, respectively.
Xie further discloses The backside power distribution network 198 comprises one or more levels wiring that are configured to distribute positive power supply voltage (e.g., VDD) and negative power supply voltage (e.g., VSS, ground (GND)=0V) to the backside power rails 194 and 196, [0050].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a first metal line as taught by Xie in order to distribute power to the second backside contact. As modified, Xie’s first metal power rail and Yun’s power rail 120 would be adjacent to Yun’s first and second FETs that include 112a, 112b, 112c, [0023].
RE: Claim 10, Yun in view of Kim, Xie discloses The microelectronic structure of claim 9, wherein the second backside contact is connected to the first metal line (As modified, Yun’s first backside contact 122, 1024 is connected to Yun’s second metal line 120, and Kim’s second backside contact is connected to Xie’s first metal line).
RE: Claim 11, Yun in view of Kim, Xie discloses The microelectronic structure of claim 10, wherein the first backside contact is connected to the second metal line (As modified, Yun’s first backside contact 122, 1024 is connected to Yun’s second metal line 120).
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yun in view of Kim.
RE: Claim 16, Yun discloses A microelectronic structure (1000 in FIG. 10) comprising:
a first nanosheet FET (second transistor including the second source/drain region 112 b and a third source/drain region 112 c, [0023]; each of the first, second, and third transistors may be a gate-all-around (GAA) transistor including a single channel region or a fin-shaped field-effect transistor (FinFET), [0022]; each of the first, second, and third channel regions 106 a, 106 b, and 106 c may be a nanosheet, [0024]) that includes a first source/drain (112c);
a second nanosheet FET (first transistor including first and second source/ drain regions 112 a and 112 b, [0023]) located adjacent to the first nanosheet FET includes a third source/drain (112b);
a dielectric cap (104 or 102; 104 may be insulating silicon oxide, [0019]; 102 may be insulating silicon oxide, [0018]; As discussed below, silicon oxide is a dielectric material) is located on a backside of the third source/drain (substrate 102 is also referred to as a backside insulator, [0017]; Accordingly, 102, 104 are located on a backside of 112b in FIG. 10);
a first backside contact (combination of 122 and 1024, [0034], [0057]; substrate 102 is also referred to as a backside insulator, [0017]; Accordingly, 122, 1024 are in a backside region and therefore in combination considered a first backside contact) connected to the first source/drain (112c), wherein the first backside contact extends through a backside region of the second nanosheet FET (FIG. 10 shows 1024 extending through a backside region of 112b which is part of the second nanosheet FET).
Yun does not explicitly disclose:
the first nanosheet FET includes a second source/drain;
a second backside contact connected to the second source/drain, wherein the first backside contact and the second backside contact are located on the same level; and
a dielectric pillar located between the first backside contact and the second backside contact.
In the same field of endeavor, Kim discloses in FIG. 2C:
a first FET (100A; 100A is a gate-all-around type field effect transistor, [0034]; Gate-All-Around field effect transistors include nanosheets surrounded by gates, [0003]; 100A is a pFET or nFET, [0038]) includes a first source/drain and a second source/drain (Annotated FIG. 2C shows first left source/drain 150 and second right source/drain 150 separated by separation pattern 320 which is dielectric, [0056]; the second separation pattern 320 may have a constant width in the first x-direction and/or the y-second direction, [0044], [0023]-[0024]; FIG. 1 shows top view where separation pattern 320 completely separates portions of source/drains 150);
a first backside contact (left 270A in Annotated FIG. 2C below; 270A is a backside contact plug, [0036]) connected to the first source/drain (left 150 in Annotated FIG. 2C below);
a second backside contact (right 270A in Annotated FIG. 2C below) connected to the second source/drain (right 150 in Annotated FIG. 2C below), wherein the first backside contact and the second backside contact are located on the same level (Annotated FIG. 2C below shows the first backside contact and the second backside contact are located on the same level);
a dielectric pillar (320, 320 includes a low dielectric constant material, [0046]; the second separation pattern 320 may include a low-κ dielectric material instead of the air gap AG2, [0056]; FIG. 3C shows separation pattern 320a composed of 322a, 321a which are dielectric, [0100]) located between the first backside contact and the second backside contact.
Further, Kim discloses that silicon oxide has a dielectric constant, [0026], and therefore silicon oxide is a dielectric material.
Kim discloses by forming the first and second separation patterns 310 and 320 including a low dielectric constant material during the backside process for forming the backside contact structure 270, the parasitic voltage problem within the semiconductor device may be improved (e.g., reduced), and accordingly, a semiconductor device with improved reliability and electrical characteristics may be provided, [0046].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a second source/drain,
a second backside contact connected to the second source/drain, and a dielectric pillar as taught by Kim in order to improve reliability and improve a parasitic voltage problem as further taught by Kim.
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Claim(s) 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yun in view of Kim as applied to claim 16, further in view of Xie.
RE: Claim 17, Yun in view of Kim discloses The microelectronic structure of claim 16, further comprising:
a second metal line (In Yun FIG. 10: power rail 120; 120 includes metal, [0043]) located adjacent to the second nanosheet FET.
Yun in view of Kim does not explicitly disclose:
a first metal line located adjacent to the first nanosheet FET.
In the same field of endeavor, Xie discloses in FIG. 1A:
a first metal line (194, [0049]) located adjacent to a first nanosheet FET (120-1 or 120-2, [0044]);
a second metal line (196, [0048]; power rails can be formed using metallic material, [0099]) located adjacent to a second nanosheet FET (120-3 or 120-4, [0044]).
Further, the word “adjacent” is not defined in the instant specification. The word “adjacent” is defined as “not distant : nearby,” see definition 1b by Merriam-Webster’s dictionary. Accordingly, in the integrated circuit device 100 in FIG. 1A of Xie, each of the power rails 194, 196 is nearby and therefore adjacent to each of the FETs 120-1, 120-2, 120-3, 120-4.
FIG. 1A shows source/drain contacts 181, 182 are connected to power rails 194, 196, respectively.
Xie further discloses The backside power distribution network 198 comprises one or more levels wiring that are configured to distribute positive power supply voltage (e.g., VDD) and negative power supply voltage (e.g., VSS, ground (GND)=0V) to the backside power rails 194 and 196, [0050].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a first metal line as taught by Xie in order to distribute power to the second backside contact. As modified, Xie’s first metal power rail and Yun’s power rail 120 would be adjacent to Yun’s first and second FETs that include 112a, 112b, 112c, [0023].
RE: Claim 18, Yun in view of Kim, Xie discloses The microelectronic structure of claim 17, wherein the second backside contact is connected to the first metal line, and wherein the first backside contact is connected to the second metal line (As modified, Yun’s first backside contact 122, 1024 is connected to Yun’s second metal line 120, and Kim’s second backside contact is connected to Xie’s first metal line).
RE: Claim 19, Yun in view of Kim, Xie discloses The microelectronic structure of claim 18, wherein the first backside contact extends through a backside region of the third source/drain (Yun FIG. 10 shows 1024 extends through a backside region of the third source/drain 112b).
RE: Claim 20, Yun in view of Kim, Xie discloses The microelectronic structure of claim 19, wherein the first backside contact contacts the dielectric cap to bypasses the third source/drain (Yun FIG. 10 shows 1024 bypasses the third source/drain 112b).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL ANGUIANO whose telephone number is (703)756-1226. The examiner can normally be reached Monday through Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at (408) 918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MICHAEL ANGUIANO/Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899
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