DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d).
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/10/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 10-11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 10 recites “a fifth word line” in line 2. However, the claims does have a fourth word line, which confuses the reader whether the fourth word line exist.
Claim 10 recites “a sixth word line” in line 2. However, the claims does have a fifth word line and a fourth word line, which confuses the reader whether the fourth word line and fifth word line exist.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3-4, 7-11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsai et al. (US 2012/0081962 A1).
Regarding claim 1, Tsai teaches a semiconductor memory device, comprising:
first memory string including a first selection transistor (Fig. 4, 112), a first memory cell (100), a second memory cell (113), a third memory cell (memory cell coupled to WL(N-2)), and a second selection transistor (111) in which current paths are coupled in series;
a bit line coupled to the first selection transistor (BL-1);
a source line coupled to the second selection transistor (CS Line);
a first select gate line coupled to a gate of the first selection transistor (SSL);
a second select gate line coupled to a gate of the second selection transistor (GSL);
a first word line coupled to a gate of the first memory cell (word line WL(i));
a second word line coupled to a gate of the second memory cell (WL(i+1));
a third word line coupled to a gate of the third memory cell (WL(N-2)); and
a control circuit configured to execute a write operation including a program operation and a program verify operation, wherein in a case where data is written to the first memory cell in the program operation of the first memory cell (Program operation, Fig. 5), the control circuit is configured to:
apply a first voltage to the bit line BL (Fig. 5, BL1 receives VBL1 which is 4V);
apply a second voltage lower than the first voltage to the source line (common source line receives GND);
apply a third voltage higher than the first voltage to the first select gate line (SSL receives 10V);
apply a fourth voltage higher than the first voltage to the second select gate line (GSL receives 10V);
apply a program voltage to the first word line (Vpgm equals to 14V is applied to the selected WL(i));
apply a fifth voltage to the second word line (Vswl is applied to (WL(i+1)) which can be -4V, see ¶0053);
and apply a sixth voltage higher than the fifth voltage and lower than the program voltage to the third word line (all other unselected word lines will receive Vpass, which is 10V).
Regarding claim 3, Tsai teaches the semiconductor memory device according to claim 1, wherein the control circuit is further configured to apply the second voltage to the bit line BL in a case where data is not written to the first memory cell in the program operation of the first memory cell (unselected bit line receives GND voltage).
Regarding claim 4, Tsai teaches the semiconductor memory device according to claim 1, wherein the first selection transistor in which the third voltage is applied to the first select gate line, the second selection transistor in which the fourth voltage is applied to the second select gate line, the first memory cell in which the program voltage is applied to the first word line, and the third memory cell in which the sixth voltage is applied to the third word line are turned on (first selection transistor, second selection transistor, first memory cell and third memory cells all receive a positive voltage to turn them on, see Fig. 5).
Regarding claim 7, Tsai further teaches the semiconductor memory device according to claim 1, wherein the first voltage is higher than the second voltage by 1 V or more (Fig. 5, voltage applied to bit line is 4V which is higher than the second voltage, which is at GND level).
Regarding claim 8, Tsai further teaches the semiconductor memory device according to claim 1, wherein the fifth voltage is equal to or lower than a threshold voltage of the second memory cell (Fig. 5, SWL starts at -4V, which is lower than a threshold voltage of the second memory cell).
Regarding claim 9, Tsai further teaches the semiconductor memory device according to claim 1, wherein in the program operation of the first memory cell, the first voltage is applied to the drain of the second memory cell, the second voltage is applied to a source of the second memory cell, and hot carriers are generated based on a voltage difference between the first voltage and the second voltage (¶0010).
Regarding claim 10, Tsai further teaches the semiconductor memory device according to claim 1, further comprising a fifth word line, wherein the first memory string further includes an eighth memory cell provided between the first memory cell and the second memory cell and having a gate coupled with the fifth word line, and the control circuit is further configured to apply the fifth voltage to the fifth word line in the program operation of the first memory cell (Fig. 4 and Fig. 5).
Regarding claim 11, Tsai further teaches the semiconductor memory device according to claim 1, further comprising a sixth word line, wherein the first memory string further includes a ninth memory cell provided between the first memory cell and the second memory cell and having a gate coupled with the sixth word line, and the control circuit is further configured to apply a seventh voltage higher than the first voltage and lower than the sixth voltage to the sixth word line in the program operation of the first memory cell (Fig. 4 and Fig. 5).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai as applied to claim 1 above, and further in view of Wan et al. (US 2006/0279990A1).
Regarding claim 2, Tsai did not explicitly teach wherein the control circuit is further configured to; execute the write operation of the second memory cell after the write operation of the first memory cell; and execute the write operation of the third memory cell after the write operation of the second memory cell. Wan teaches data will be programmed into the first word line, then the second word line, then the third word line and so on until it reaches the last word line (¶0068). It is well-known in the art to any person with the ordinary skills in the art at the time of filing the invention that data will be programmed into the first word line, then the second word line, then the third word line and so on until it reaches the last word line. This way is the most common way to write data into a memory array.
Claim(s) 5 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai as applied to claim 1 above, and further in view of Nam et al. (US 2016/0064083 A1).
Regarding claim 5, Tsai further teaches the semiconductor memory device according to claim 1, further comprising: a second memory string including a third selection transistor, a fourth memory cell, a fifth memory cell, a sixth memory cell, and a fourth selection transistor in which current paths are coupled in series; and a third select gate line coupled to a gate of the third selection transistor, wherein the third selection transistor is coupled to the bit line, the fourth selection transistor is coupled to the source line, a gate of the fourth selection transistor is coupled to the first word line, a gate of the fifth memory cell is coupled to the second word line, a gate of the sixth memory cell is coupled to the third word line (Tsai teaches the claimed feature for an unselected memory cell string in Fig. 4 and Fig. 5).
Tsai is silent in teaching the unselected memory cell to have the control circuit is further configured to apply the second voltage (ground voltage) to the third select gate line in the program operation of the first memory cell.
Nam teaches control circuit is further configured to apply the second voltage (ground voltage) to the third select gate line in the program operation of the first memory cell (¶0073 and ¶0116).
Thus, it would have been obvious to a person with the ordinary skill in the art before the effective filling date of the claimed invention to unselect the memory cells string in order to prevent programming data into the wrong memory cells string.
Regarding claim 6, Nam further teaches the semiconductor memory device according to claim 5, wherein the third selection transistor in which the second voltage is applied to the third select gate line is turned off (Ground voltage applied to the selection transistor causes the NMOS to turn off).
Claim(s) 12-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai, and further in view of Kato et al. (US 2017/0076813 A1).
Regarding claim 12, Tsai teaches a semiconductor memory device, comprising:
first memory string including a first selection transistor (Fig. 4, 112), a first memory cell (100), a second memory cell (113), a third memory cell (memory cell coupled to WL(N-2)), and a second selection transistor (111) in which current paths are coupled in series;
a bit line coupled to the first selection transistor (BL-1);
a source line coupled to the second selection transistor (CS Line);
a first select gate line coupled to a gate of the first selection transistor (SSL);
a second select gate line coupled to a gate of the second selection transistor (GSL);
a first word line coupled to a gate of the first memory cell (word line WL(i));
a second word line coupled to a gate of the second memory cell (WL(i+1));
a third word line coupled to a gate of the third memory cell (WL(N-2)); and
a control circuit configured to execute a write operation including a program operation and a program verify operation, wherein in a case where data is written to the first memory cell in the program operation of the first memory cell (Program operation, Fig. 5), the control circuit is configured to:
apply a first voltage to the bit line BL (Fig. 5, BL1 receives VBL1 which is 4V);
apply a second voltage lower than the first voltage to the source line (common source line receives GND);
apply a fourth voltage higher than the first voltage to the second select gate line (GSL receives 10V);
apply a program voltage to the first word line (Vpgm equals to 14V is applied to the selected WL(i));
apply a fifth voltage to the second word line (Vswl is applied to (WL(i+1)) which can be -4V, see ¶0053);
and apply a sixth voltage higher than the fifth voltage and lower than the program voltage to the third word line (all other unselected word lines will receive Vpass, which is 10V).
Tsai does not explicitly teach applying a third voltage higher than the second voltage and lower than the first voltage to the first select gate line.
Kato teaches applying a third voltage higher than the second voltage and lower than the first voltage to the first select gate line.
Thus, it would have been obvious to a person with the ordinary skill in the art before the effective filling date of the claimed invention to use Kato programming voltages in order to use lower programming voltages which will result in operating the memory device in lower voltage range environment and the voltage generators do not need to generate a very high voltages.
Regarding claim 13, Tsai further teaches the semiconductor memory device according to claim 12, wherein the first selection transistor in which the third voltage is applied to the first select gate line and the second memory cell in which the fifth voltage is applied to the second word line are turned off, and the second selection transistor in which the fourth voltage is applied to the second select gate line, the first memory cell in which the program voltage is applied to the first word line, and the third memory cell in which the sixth voltage is applied to the third word line are turned on (Fig. 4 and Fig. 5).
Regarding claim 14, Tsai further teaches the semiconductor memory device according to claim 12, wherein the control circuit is further configured to apply the second voltage to the bit line BL in a case where data is not written to the first memory cell in the program operation of the first memory cell (Fig. 5, unselected BL receive GND).
Regarding claim 15, Tsai further teaches the semiconductor memory device according to claim 14, wherein the first selection transistor in which the first voltage is applied to the current path and in which the third voltage is applied to the first select gate line is turned off (Fig. 5, the current path for the unselected BL is turned off).
Regarding claim 16, Tsai further teaches the semiconductor memory device according to claim 12, wherein the control circuit is further configured to apply a seventh voltage higher than the fifth voltage and lower than the sixth voltage after applying the fifth voltage to the second word line in the program operation of the first memory cell (V-SW can be set to sweep across an operative range. V-SW dynamically changes).
Regarding claim 17, Tsai further teaches the semiconductor memory device according to claim 12, further comprising: a second memory string including a third selection transistor, a fourth memory cell, a fifth memory cell, a sixth memory cell, and a fourth selection transistor in which current paths are coupled in series; and a third select gate line coupled to a gate of the third selection transistor, wherein the third selection transistor is coupled to the bit line, the fourth selection transistor is coupled to the source line, a gate of the fourth selection transistor is coupled to the second select gate line, a gate of the fourth memory cell is coupled to the first word line, a gate of the fifth memory cell is coupled to the second word line, a gate of the sixth memory cell is coupled to the third word line, and the control circuit is further configured to apply an eighth voltage higher than the first voltage to the third select gate line in the program operation of the first memory cell (Fig. 4 and Fig. 5).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAMDAN N ALROBAIE whose telephone number is (571)270-7099. The examiner can normally be reached Monday to Thursday (8AM till 6PM).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached at (571) 272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Khamdan N. Alrobaie/ Primary Examiner, Art Unit 2824