Prosecution Insights
Last updated: October 02, 2026
Application No. 18/829,980

SEMICONDUCTOR DEVICE

Non-Final OA §103
Filed
Sep 10, 2024
Priority
Mar 17, 2022 — JP 2022-043176 +1 more
Examiner
JAHAN, BILKIS
Art Unit
Tech Center
Assignee
Rohm Co., Ltd.
OA Round
1 (Non-Final)
89%
Grant Probability
Favorable
1-2
OA Rounds
3m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allowance Rate
821 granted / 926 resolved
+28.7% vs TC avg
Moderate +10% lift
Without
With
+10.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
26 currently pending
Career history
959
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
54.6%
+14.6% vs TC avg
§102
23.7%
-16.3% vs TC avg
§112
13.5%
-26.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 926 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Attorney Docket Number: 10921.1308USW1 Filling Date: 09/10/2024 Priority Date: 03/17/22 Inventor: ONO Examiner: Bilkis Jahan DETAILED ACTION In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-4 and 12-17 are rejected under 35 U.S.C. 103 as being unpatentable over Nozaki et al (US 2007/0262409 A1). Regarding claim 1, Nozaki discloses a semiconductor device (Fig. 4) comprising: a semiconductor element 17 (Para. 93) including a plurality of electrodes 18 (Para. 93); a first lead including a first pad portion (see annotated figure), and a first terminal portion (see annotated figure) continuous to the first pad portion on a first side in a first direction (Fig. 4, X-direction); a second lead including a second pad portion located adjacent to the first pad portion in a second direction (see annotated figure, Y-direction) perpendicular to the first direction, and a second terminal portion located adjacent to the first terminal portion in the second direction (see annotated figure) and continuous to the second pad portion (see annotated figure); and a sealing resin 22 (Para. 94) covering a portion of each of the first lead 5 (Para. 93) and the second lead 5 and the semiconductor element 17, wherein a portion of each of the first terminal portion and the second terminal portion is exposed to an outside from the sealing resin 22, as viewed in a third direction perpendicular to the first direction and the second direction (Fig. 4), a length of a straight line connecting a center of the first pad portion and a center of the second pad is defined as a first section length portion (see annotated figure, Length L2), as viewed in the third direction, a length of a straight line connecting a center of the first terminal portion and a center of the second terminal portion is defined as a second section length portion (see annotated figure, Length L1), and the second section length is different from the first section length (see L1 and L2). Nozaki does not explicitly disclose in the embodiment of figure 4 that a plurality of wires each electrically bonded to one of the plurality of electrodes and to one of the first pad portion and the second pad portion. However, Nozaki discloses in fig. 5 that a plurality of wires 21 (Para. 93) each electrically bonded to one of the plurality of electrodes 19, 18 (Para. 93) and to one of the first pad portion and the second pad portion 16. Nozaki teaches the above modification is used to connect the electrode with the pad by the wire (Fig. 5). It would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to combine Nozaki figure 4 with Nozaki figure 5 wire as suggested above to connect the electrode with the pad by the wire (Fig. 5). PNG media_image1.png 734 1005 media_image1.png Greyscale Regarding claim 2, Nozaki discloses the semiconductor device according to claim 1, wherein a dimension of the first terminal portion (see annotated portion) in the second direction (Y-direction) is smaller than a dimension of the first pad portion (see annotated portion) in the second direction, and a dimension of the second terminal portion (see annotated portion) in the second direction is smaller than a dimension of the second pad portion (see annotated portion) in the second direction. Regarding claim 3, Nozaki discloses the semiconductor device according to claim 2, wherein the dimension of the second pad portion 20 (left top most one in Fig. 4) in the second direction is a same as the dimension of the first pad portion 20 (left bottom most one) in the second direction. Regarding claim 4, Nozaki discloses the semiconductor device according to claim 2, wherein the second section length L1 is shorter than the first section length L2 (see annotated figure). Regarding claim 12, Nozaki discloses the semiconductor device according to claim 2, wherein the second section length (length between two leads 5, top and bottom) is longer than the first section length (consider top two pads 20). Regarding claim 13, Nozaki discloses the semiconductor device according to claim 1, further comprising a die pad on which the semiconductor element is mounted, wherein the die pad 18, 19 is located opposite from the first terminal portion with respect to the first pad portion in the first direction (see annotated figure). Regarding claim 14, Nozaki discloses the semiconductor device according to claim 13, wherein the die pad 18, 19 includes a reverse surface facing away from a side facing the semiconductor element 17 in the third direction, and the reverse surface is exposed from the sealing resin 22 (same as instant application). Regarding claim 15, Nozaki discloses the semiconductor device according to claim 14, wherein the die pad 2 (Fig. 6, Para. 65) includes a pad portion on which the semiconductor element 17 is mounted, and two suspending portions located opposite from each other with respect to the pad portion 2 in the second direction and continuous to the pad portion, and as viewed in the first direction, the two suspending portions are bent toward the semiconductor element with respect to the pad portion in the third direction (Figures 4, 6). Regarding claim 16, Nozaki discloses the semiconductor device according to claim 1, wherein the first terminal portion (see annotated figure) is formed with a recess recessed in the third direction, and a portion of the sealing resin 22 is accommodated in the recess (Fig. 6B). Regarding claim 17, Nozaki discloses the semiconductor device according to claim 1, wherein as viewed in the third direction, the portion of each of the first terminal portion and the second terminal portion that is exposed to the outside from the sealing resin 22 extends in the first direction (see annotated figure). Allowable Subject Matter Claims 5-10 and 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to BILKIS JAHAN whose telephone number is (571)270-5022. The examiner can normally be reached Monday-Friday, 8:00 am-5 Pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon T Fletcher can be reached at (571)272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. BILKIS . JAHAN Primary Examiner Art Unit 2817 /BILKIS JAHAN/Primary Examiner, Art Unit 2817
Read full office action

Prosecution Timeline

Sep 10, 2024
Application Filed
Sep 15, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12751259
EMBEDDING METHOD AND PROCESSING SYSTEM
3y 0m to grant Granted Sep 29, 2026
Patent 12751276
INTERCONNECT STRUCTURE WITH INTRA-LEVEL METAL LINE CONNECTORS
2y 6m to grant Granted Sep 29, 2026
Patent 12745679
Package-On-Package Assembly Containing A Decoupling Capacitor
2y 11m to grant Granted Sep 22, 2026
Patent 12740143
RECONFIGURABLE COMPLEMENTARY METAL OXIDE SEMICONDUCTOR DEVICE AND METHOD
3y 0m to grant Granted Sep 15, 2026
Patent 12740062
NONVOLATILE MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME
2y 6m to grant Granted Sep 15, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
89%
Grant Probability
99%
With Interview (+10.2%)
2y 4m (~3m remaining)
Median Time to Grant
Low
PTA Risk
Based on 926 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month