DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement(s)
The Information Disclosure Statement(s) filed on September 10, 2024 was considered by the Examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 11 includes “a first hard mask pattern having a second hole pattern,” “removing the first hard mask pattern to form a first spacer pattern,” and “removing the second spacer layer covering the upper surface of the first spacer pattern to open the second hole pattern again” and this is indefinite as it is unclear how the second hole pattern is present without the first hard mask pattern (since the first hard mask pattern has the second hole pattern, and the first hard mask pattern was removed). It is further unclear as the claim does not state when the second hole pattern was opened initially, and therefore how can second hole pattern be opened “again.” For the purposes of examination, “removing the second spacer layer covering the upper surface of the first spacer pattern to open the second hole pattern again” will be interpreted to mean “removing the second spacer layer covering the upper surface of the first spacer pattern to open or expose an opening in the first spacer pattern.”
Similarly, claim 16 includes “a second hard mask pattern having a fifth hole pattern,” “removing the second hard mask pattern to form a third spacer pattern,” and “the fourth spacer layer covering the upper surface of the third spacer pattern is removed to open the fifth hole pattern again” and this is indefinite as it is unclear how the fifth hole pattern is present without the second hard mask pattern (since the second hard mask pattern has the fifth hole pattern, and the second hard mask pattern was removed). It is further unclear as the claim does not state when the fifth hole pattern was opened initially, and therefore how can fifth hole pattern be opened “again.” For the purposes of examination, “the fourth spacer layer covering the upper surface of the third spacer pattern is removed to open the fifth hole pattern again” will be interpreted to mean “the fourth spacer layer covering the upper surface of the third spacer pattern is removed to open or expose an opening in the third spacer pattern.”
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over US20230005750A1 (“Wan”), in view of US20230328995A1 (“Lin”), further in view of US20040214113 A1 (“Goldstein”), further in view of US6071812A (“Hsu”).
RE: Claim 1, Wan discloses A method for manufacturing a semiconductor device (method for manufacturing semiconductor structure in FIGs. 3-22, [0030]), the method comprising:
forming first and second mask layers (120, 11, respectively in FIG. 3, [0042]) above a layer to be processed (10) in order of the second mask layer (11) and the first mask layer (120) from a side of the layer to be processed (top side of 10);
forming a resist mask pattern (123; 123 is a photoresist layer [0040]) having a first hole pattern above the first mask layer (FIG. 3 shows 123 having a first hole pattern above the first mask layer 120);
transferring the first hole pattern to the first mask layer to form a first mask pattern (12 in FIG. 5, [0042]) having a second hole pattern (FIG. 5 shows the first hole pattern was transferred to the first mask layer 120 to form a first mask pattern 12 having a second hole pattern 191; Wan teaches 12 is constituted by the remaining initial second mask layer 120, [0042]);
forming a first spacer layer (131 in FIG. 6) on a side wall of the second hole pattern and removing the first mask pattern to form a first spacer pattern (13 or 192 in 13 in FIG. 7) being cylindrical and arranged at a position of the second hole pattern (FIG. 7 shows the first mask pattern 12 was removed to form a first spacer pattern 13 arranged at a position of the second hole pattern; FIGs. 7-8 show 13, 192 is cylindrical);
forming a second spacer layer (161 in FIG. 17) at least covering an upper surface of the second mask layer (11) outside the first spacer pattern, and
partially removing the second spacer layer overlapping a first region (region in FIG. 16 consisting of minimum distance connecting center points of 13 or 192) consisting of a minimum distance connecting center points of the first spacer pattern to form a second spacer pattern (16 in FIG. 18) having a third hole pattern (195), to form a fourth hole pattern (192, 195) including the first spacer pattern and the third hole pattern included in the second spacer pattern (FIGs. 16-18 show partially removing second spacer layer 161 overlapping a first region consisting of a minimum distance connecting center points of the first spacer pattern 13, 192 to form a second spacer pattern 16 having a third hole pattern 195, to form a fourth hole pattern 192, 195 including the first spacer pattern 192 and the third hole pattern 195 included in the second spacer pattern);
transferring the fourth hole pattern to the second mask layer to form a second mask pattern having a fifth hole pattern (FIG. 20 shows the fourth hole pattern 192, 195 was transferred to the second mask layer 11 to form a second mask pattern having a fifth hole pattern).
Wan does not explicitly disclose:
the first hole pattern of the resist mask pattern was formed using lithography;
the first and second mask layers are first and second hard mask layers;
forming a third spacer layer on a side wall of the fifth hole pattern, and removing the second hard mask pattern to form a third spacer pattern being cylindrical and arranged at a position of the fifth hole pattern;
forming a fourth spacer layer at least covering an upper surface of the layer to be processed outside the third spacer pattern, and
partially removing the fourth spacer layer overlapping a second region consisting of a minimum distance connecting center points of the third spacer pattern to form a fourth spacer pattern having a sixth hole pattern, to form a seventh hole pattern including the third spacer pattern and the sixth hole pattern included in the fourth spacer pattern; and transferring the seventh hole pattern to the layer to be processed.
In the same field of endeavor, Lin discloses:
A photoresist layer is then formed on the hard mask by a suitable fabrication process, for example, but not limited to, spin-on coating. The photoresist layer is then patterned by a suitable photolithography process to form a pattern of holes arranged in position corresponding to the pairs of the bottom via openings 121 to be formed, [0013].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use photolithography to form the first hole pattern of the resist mask pattern 123 as this would have been obvious to try since Wan discloses 123 is a photoresist, [0040], and photolithography is one suitable solution for forming a pattern of holes in a photoresist identified by Lin and this would have had a reasonable expectation of success, see MPEP 2143.
In the same field of endeavor, Goldstein teaches:
Because reflections occur at interfaces when there is an index of refraction mismatch between the materials on each side of the interface, in Deep UV (DUV) lithography reflections from the top and bottom resist interfaces may be so strong that prominent standing waves may be created in the resist. Photons may be absorbed in a first pass as the light enters the photoresist and in a second pass as photons are reflected from the substrate surface. To improve resolution and critical dimension (CD) control, standing waves may be minimized in DUV lithography by the use of anti-reflective hardmasks (bottom ARCS) to control the reflectivity at the interface, [0014].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the first and second mask layers 120, 11 to be hard mask layers as taught by Goldstein in order to improve resolution and critical dimension control as further taught by Goldstein.
In the same field of endeavor, Hsu discloses:
The method of the invention can repeated any number of times to create a contact hole comprised of any number of different width openings (each successive opening having a smaller width than the previous opening) that are formed using any number of spacers. The basic process of the invention--1 spacer formation (*E.g., FIGS. 3 & 4), 2 etch narrower opening (e.g., FIG. 5), and 3 spacer formation (FIGS. 3 & 4) . . . .--can be repeated any number of times to create the desired contact hole having a desired aspect ratio, Col. 2, lines 9-20.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to repeat the process of FIGs. 3-20 of Wan as taught by Hsu in order to create a hole pattern having a desired aspect ratio.
Wan as modified by Lin, Goldstein, Hsu would disclose:
forming a third spacer layer (another 131 from Wan FIG. 6) on a side wall of the fifth hole pattern (As modified, the another 131 would be formed on a side wall of the fifth hole pattern of the second mask 11 in FIG. 20 Wan), and removing the second hard mask pattern to form a third spacer pattern (another 13 or 192 in 13 from Wan FIG. 7) being cylindrical and arranged at a position of the fifth hole pattern (Wan FIG. 7 shows the first mask pattern 12 was removed to form a first spacer pattern 13 arranged at a position of the second hole pattern; FIGs. 7-8 show 13, 192 is cylindrical; Accordingly, when repeated, the process would include removing the second hard mask pattern 11 to form a third spacer pattern 13 or 192 being cylindrical and arranged at a position of the fifth hole pattern of 11);
forming a fourth spacer layer (another 161 from Wan FIG. 17) at least covering an upper surface of the layer to be processed outside the third spacer pattern (Another 161 would at least cover an upper surface of 10 outside the third spacer pattern 13 or 192 as shown in Wan FIG. 17), and
partially removing the fourth spacer layer overlapping a second region (second region in FIG .16 consisting of minimum distance connecting center points of 13 or 192 on the layer to be processed 10) consisting of a minimum distance connecting center points of the third spacer pattern to form a fourth spacer pattern (another 16 from Wan FIG. 18) having a sixth hole pattern (another 195), to form a seventh hole pattern (another 192, 195 as shown in FIG. 18) including the third spacer pattern and the sixth hole pattern included in the fourth spacer pattern (As modified, the process would include partially removing the fourth spacer layer 161 overlapping a second region consisting of a minimum distance connecting center points of the third spacer pattern 13, 192 to form a fourth spacer pattern 16 having a sixth hole pattern 195, to form a seventh hole pattern 192, 195 including the third spacer pattern 192 and the sixth hole pattern 195 included in the fourth spacer pattern); and
transferring the seventh hole pattern to the layer to be processed (Wan teaches With reference to FIG. 21, the isolation layer 10 is etched with the patterned third lower mask layer 111 as a mask to form the capacitor holes 196, [0073]; Accordingly, as modified, the process would include transferring the seventh hole pattern 192, 195 to the layer to be processed 10).
Claim(s) 2-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wan in view of Lin, further in view of Goldstein, further in view of Hsu as applied to claim 1, further in view of US20160314987A1 (“Shim”).
RE: Claim 2, Wan in view of Lin, Goldstein, Hsu does not explicitly disclose The method for manufacturing a semiconductor device according to claim 1, wherein
the first hole pattern is formed to be a hexagonal close-packed arrangement in which each of the patterns is arranged at each of vertexes of a regular hexagon and a center point of the regular hexagon when viewed from a stacking direction of the first and second hard mask layers.
However, in the same field of endeavor, Shim discloses:
The plurality of first guide-forming holes may be arranged in a regular form. For example, the first guide-forming holes H1 may be arranged in a hexagonal array or a matrix array, [0063].
In FIG. 2A, Shim discloses:
a first hole pattern (H1) is formed to be a hexagonal close-packed arrangement in which each of the patterns is arranged at each of vertexes of a regular hexagon (vertexes of regular hexagon formed by outer holes H1 in FIG. 2A) and a center point of the regular hexagon (center hole H1) when viewed from a stacking direction of first and second mask layers (vertical stacking direction in FIG. 2B of first and second mask layers 106, 108, [0045]).
In FIG. 2B, Shim shows the hole pattern H1 is formed in each of the anti-reflection layer 110P, second mask pattern 108P, and first mask pattern 106P, [0062].
In FIG. 7A, Shim shows another hole pattern for 202A in a region consisting of a minimum distance connecting center points of the spacer pattern/openings for PG1 in 202B.
Shim further teaches inventive concepts provide a method of forming fine patterns, which is capable of easily forming a plurality of patterns repeatedly with a fine pitch when forming patterns necessary for manufacturing a highly integrated semiconductor device exceeding a resolution limit of a photolithography process, [0004].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the first hole pattern in the resist mask pattern 123, the fourth hole pattern 192, 195, and the seventh hole pattern 192, 195 as hexagonal close-packed arrangements as taught by Shim in order to form a plurality of patterns with a fine pitch exceeding a resolution limit of photolithography as further taught by Shim.
RE: Claim 3, Wan in view of Lin, Goldstein, Hsu, Shim discloses The method for manufacturing a semiconductor device according to claim 2, wherein
the first region has a shape of a substantially equilateral triangle when viewed from the stacking direction (Wan teaches 192 may be arranged in hexagonal mode, [0048]; As modified, the fourth hole pattern 192, 195 is in a hexagonal close-packed arrangement; Accordingly, the first region connecting center points of the first spacer pattern 13 or 192 in Wan FIGs. 16-18 would correspond to a region connecting three center points of the spacer pattern/openings for PG1 in 202B in Shim FIG. 7A which has a shape of a substantially equilateral triangle when viewed in a vertical stacking direction of Shim FIG. 7B), and
the third hole pattern is substantially formed at a center point of the first region (Wan FIG. 19 shows the third hole pattern 195 formed near a center point of the first region connecting three points of 13, 192; As modified by Shim, the third hole pattern 195 in Wan would correspond to the hole pattern for 202A in Shim FIG. 7A which is formed at a center point of the first region connecting three center points of holes for PG1).
RE: Claim 4, Wan in view of Lin, Goldstein, Hsu, Shim discloses The method for manufacturing a semiconductor device according to claim 2, wherein the fourth hole pattern substantially has the hexagonal close-packed arrangement when viewed from the stacking direction (As modified, the fourth hole pattern would have the hole pattern for PG1, 202A in 202B Shim FIG. 7A which substantially has the hexagonal close-packed arrangement when viewed in the vertical stacking direction of Shim FIG. 7B).
RE: Claim 5, Wan in view of Lin, Goldstein, Hsu, Shim discloses The method for manufacturing a semiconductor device according to claim 4, wherein the fourth hole pattern has a pitch that is substantially 1/√3 times a pitch of the first hole pattern (Shim teaches the first pillar-shaped guides PG1 may be arranged in a hexagonal array having a first pitch P1 that is about 1.73 times greater than a bulk cycle L0 of a block copolymer layer 202, [0071]; As modified by Shim, the first hole pattern would have a pitch corresponding to P1 in Shim FIG. 7A, and the fourth hole pattern would have a pitch corresponding to L0 in Shim FIG. 7A, therefore the fourth hole pattern would have a pitch of 1/1.73 times the pitch of the first hole pattern, which is substantially 1/√3 times the pitch of the first hole pattern).
RE: Claim 6, Wan in view of Lin, Goldstein, Hsu, Shim discloses The method for manufacturing a semiconductor device according to claim 4,
wherein the second region has a shape of a substantially equilateral triangle when viewed from the stacking direction (As modified, the second region is formed by repeating the method of Wan; Accordingly, as the first region has a shape of a substantially equilateral triangle when viewed from the stacking direction, the second region connecting three center points of a second spacer pattern 13 or 192 in Wan FIGs. 16-18 would correspond to the region connecting three center points of the spacer pattern/ openings for PG1 in 202B in Shim FIG. 7A which has a shape of a substantially equilateral triangle when viewed in a vertical stacking direction of Shim FIG. 7B), and
the sixth hole pattern is substantially formed at a center point of the second region (As modified by Shim, the sixth hole pattern 195 in Wan would correspond to the hole pattern for 202A in Shim FIG. 7A which is formed at a center point of a region connecting three center points of holes for PG1, therefore the sixth hole pattern would be formed at a center point of the second region connecting center points of a second spacer pattern 13 or 192).
RE: Claim 7, Wan in view of Lin, Goldstein, Hsu, Shim discloses The method for manufacturing a semiconductor device according to claim 2, the seventh hole pattern substantially has the hexagonal close-packed arrangement when viewed from the stacking direction (As modified by Shim, the seventh hole pattern has the hexagonal close-packed arrangement when viewed from the stacking direction).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wan in view of Lin, further in view of Goldstein, further in view of Hsu, further in view of Shim as applied to claim 7, further in view of US20150243525 A1 (“Park”).
RE: Claim 8, Wan in view of Lin, Goldstein, Hsu, Shim does not explicitly disclose The method for manufacturing a semiconductor device according to claim 7, the seventh hole pattern has a pitch that is substantially 1/3 times a pitch of the first hole pattern.
However, in the same field of endeavor, Park discloses a method of forming a fine pattern, which may relatively easily implement a fine-pitch pattern that is necessary to manufacture a highly-integrated semiconductor device that transcends a resolution limit in a photolithography process, [0004].
Park discloses the plurality of guide patterns GP_6 are repetitively formed at a fourth guide pitch Pg_4, [0154];
Park further discloses the first block 650 a and the second block 650 b of the fine pattern layer 650 are repetitively disposed at a fourth block pitch Pb_4, [0154].
Park further discloses The first block 350 a and the second block 350 b of the fine pattern layer 350 are disposed in a contact hole pattern, [0120].
Park further discloses According to Equation 8, when n=2, the fourth guide pitch Pg_4 is about three times the fourth block pitch Pb_4, [0155], see FIGs. 6D.
Accordingly, the later pitch Pb_4 is 1/3 times the earlier pitch Pg_4.
Park further discloses in order to implement a fine-pitch pattern to manufacture a highly-integrated semiconductor device that transcends a resolution limit in a photolithography process, a pattern density is increased by adjusting a pattern pitch, [0045].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the seventh hole pattern to have a pitch that is 1/3 times the pitch of the first hole pattern as taught by Park in order to implement a fine pitch pattern with increased pattern density as further taught by Park.
Claim(s) 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wan in view of Lin, further in view of Goldstein, further in view of Hsu as applied to claim 1, further in view of US20110294297A1 (“Sukekawa”).
RE: Claim 9, Wan in view of Lin, Goldstein, Hsu discloses The method for manufacturing a semiconductor device according to claim 1, wherein
the second spacer pattern is formed by removing the second spacer layer overlapping with the first region, and removing the second spacer layer covering the upper surface of the first spacer pattern (Wan FIG. 18 shows the second spacer pattern 16 is formed by removing the second spacer layer 161 overlapping with the first region connecting centers points of 13 or 192 in FIG. 17, and removing the second spacer layer 161 covering the upper surface of the first spacer pattern 13 or 192 in FIG. 13).
Wan in view of Lin, Goldstein, Hsu does not explicitly disclose:
the second spacer layer is formed, while covering the upper surface of the second hard mask layer, to cover an upper surface of the first spacer pattern so as to form a first air gap in a cylinder of the first spacer pattern.
However, FIG. 17 Wan shows that a void/air gap is formed in a cylinder of the first spacer pattern 13 while the second spacer layer 161 covers an upper surface of the second mask layer 11, where the void/air gap is defined by 161 within the cylinder of the first spacer pattern 13.
Alternatively, in the same field of endeavor, Sukekawa discloses in FIGs. 4A-7B:
a spacer layer (11 in FIG. 5B, [0026]) is formed, while covering an upper surface of a mask layer (4 labeled in FIG. 1B, [0025]), to cover an upper surface of a spacer pattern (3 labeled in FIG. 1B, [0025]) so as to form an air gap (void 11b, [0026]) in a cylinder of the spacer pattern (3 would form a cylinder as 10 forms cylinders in FIGs. 3A-3B, and since 10 is used as a mask to dry etch layers 3 and 4, [0025], layers 3 and 4 would form cylinders after dry etching 3 and 4 using 10 as a mask).
Sukekawa further teaches The present invention provides a technique of forming densely-packed contact-hole patterns in a semiconductor device, and more particularly, a method of manufacturing a semiconductor device, in which a high-precision hole pattern is formed by a self-align double patterning technique, [0006].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the second spacer layer so that a void/air gap is formed in a cylinder of the first spacer pattern as taught by Sukekawa in order to form a densely packed contact hole pattern in which high precision hole pattern is formed as further taught by Sukekawa.
RE: Claim 10, Wan in view of Lin, Goldstein, Hsu discloses The method for manufacturing a semiconductor device according to claim 1, wherein
the fourth spacer pattern is formed by removing the fourth spacer layer overlapping the second region, and removing the fourth spacer layer covering the upper surface of the third spacer pattern (As modified, the method of Wan is repeated; Accordingly as modified, the fourth spacer pattern 16 would be formed by removing the fourth spacer layer 161 overlapping the second region connecting center points of 13 or 192, and removing the fourth spacer layer 161 covering the upper surface of the third spacer pattern 13 or 192).
Wan in view of Lin, Goldstein, Hsu does not explicitly disclose:
the fourth spacer layer is formed, while covering the upper surface of the layer to be processed, to cover an upper surface of the third spacer pattern so as to form a second air gap in a cylinder of the third spacer pattern.
However, as modified, the method of Wan is repeated to form the fourth spacer layer. FIG. 17 Wan shows that a void/air gap would be formed in a cylinder of the third spacer pattern 13 while the fourth spacer layer 161 covers an upper surface of the layer to be processed 10, where the void/air gap would be defined by 161 within the cylinder of the third spacer pattern 13.
Alternatively, in the same field of endeavor, Sukekawa discloses in FIGs. 4A-7B:
a spacer layer (11 in FIG. 5B, [0026]) is formed, while covering an upper surface of a mask layer (4 labeled in FIG. 1B, [0025]), to cover an upper surface of a spacer pattern (3 labeled in FIG. 1B, [0025]) so as to form an air gap (void 11b, [0026]) in a cylinder of the spacer pattern (3 would form a cylinder as 10 forms cylinders in FIGs. 3A-3B, and since 10 is used as a mask to dry etch layers 3 and 4, [0025], layers 3 and 4 would form cylinders after dry etching 3 and 4 using 10 as a mask).
Sukekawa further teaches The present invention provides a technique of forming densely-packed contact-hole patterns in a semiconductor device, and more particularly, a method of manufacturing a semiconductor device, in which a high-precision hole pattern is formed by a self-align double patterning technique, [0006].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the fourth spacer layer so that a void/air gap is formed in a cylinder of the third spacer pattern as taught by Sukekawa in order to form a densely packed contact hole pattern in which high precision hole pattern is formed as further taught by Sukekawa.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wan in view of Lin, further in view of Goldstein, further in view of Sukekawa.
RE: Claim 11, Wan discloses A method for manufacturing a semiconductor device (method for manufacturing semiconductor structure in FIGs. 3-22, [0030]), the method comprising:
forming a first mask layer (120 in FIG. 3, [0042]) above a layer to be processed (10);
forming a resist mask pattern (123; 123 is a photoresist layer [0040]) having a first hole pattern formed above the first mask layer (FIG. 3 shows 123 having a first hole pattern above the first mask layer 120);
transferring the first hole pattern to the first mask layer to form a first mask pattern (12 in FIG. 5, [0042]) having a second hole pattern (FIG. 5 shows the first hole pattern was transferred to the first mask layer 120 to form a first mask pattern 12 having a second hole pattern 191; Wan teaches 12 is constituted by the remaining initial second mask layer 120, [0042]);
forming a first spacer layer (131 in FIG. 6) on a side wall of the second hole pattern and removing the first mask pattern to form a first spacer pattern (13 or 192 in 13 in FIG. 7) being cylindrical and arranged at a position of the second hole pattern (FIG. 7 shows the first mask pattern 12 was removed to form a first spacer pattern 13 arranged at a position of the second hole pattern; FIGs. 7-8 show 13, 192 is cylindrical);
forming a second spacer layer (161 in FIG. 17) covering an upper surface of the layer to be processed (10) outside the first spacer pattern (FIG. 17 shows 161 would cover an upper surface of 10 in a top view outside the first spacer pattern 13 or 192), and covering an upper surface of the first spacer pattern (FIG. 17 shows 161 covering an upper surface of the first spacer pattern 13);
removing the second spacer layer covering the upper surface of the first spacer pattern to open the second hole pattern again (192; FIG. 18 shows the second spacer layer 161 was removed to open or expose the hole pattern 192 in the first spacer pattern 13), and removing the second spacer layer overlapping a first region (region in FIG. 16 consisting of minimum distance connecting center points of 13 or 192) consisting of a minimum distance connecting center points of the first spacer pattern to form a second spacer pattern (16 in FIG. 18 ) having a third hole pattern (195), to form a fourth hole pattern (192, 195) including the second hole pattern (192) opened in the first spacer pattern (13) and the third hole pattern (195) opened in the second spacer pattern (FIGs. 16-18 show removing the second spacer layer overlapping a first region consisting of a minimum distance connecting center points of the first spacer pattern 13 or 192 to form a second spacer pattern 16 having a third hole pattern 195, to form a fourth hole pattern 192, 195 including the second hole pattern 192 opened in the first spacer pattern 13 and the third hole pattern 195 opened in the second spacer pattern); and
transferring the fourth hole pattern to the layer to be processed (FIGs. 18-21 shows the fourth hole pattern was transferred to the layer to be processed 10).
Wan does not explicitly disclose:
the first hole pattern of the resist mask pattern was formed using lithography;
the first mask layer is a hard mask layer;
the second spacer layer covers the upper surface of the first spacer pattern so as to form a first air gap in a cylinder of the first spacer pattern.
In the same field of endeavor, Lin discloses:
A photoresist layer is then formed on the hard mask by a suitable fabrication process, for example, but not limited to, spin-on coating. The photoresist layer is then patterned by a suitable photolithography process to form a pattern of holes arranged in position corresponding to the pairs of the bottom via openings 121 to be formed, [0013].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use photolithography to form the first hole pattern of the resist mask pattern 123 as this would have been obvious to try since Wan discloses 123 is a photoresist, [0040], and photolithography is one suitable solution for forming a pattern of holes in a photoresist identified by Lin and this would have had a reasonable expectation of success, see MPEP 2143.
In the same field of endeavor, Goldstein teaches:
Because reflections occur at interfaces when there is an index of refraction mismatch between the materials on each side of the interface, in Deep UV (DUV) lithography reflections from the top and bottom resist interfaces may be so strong that prominent standing waves may be created in the resist. Photons may be absorbed in a first pass as the light enters the photoresist and in a second pass as photons are reflected from the substrate surface. To improve resolution and critical dimension (CD) control, standing waves may be minimized in DUV lithography by the use of anti-reflective hardmasks (bottom ARCS) to control the reflectivity at the interface, [0014].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the first mask layer 120 to be a hard mask layer as taught by Goldstein in order to improve resolution and critical dimension control as further taught by Goldstein.
Additionally, Wan FIG. 17 shows that a void/air gap is formed in a cylinder of the first spacer pattern 13 while the second spacer layer 161 covers an upper surface of the first spacer pattern 13 and an upper surface of the second mask layer 11, where the void/air gap is defined by 161 within the cylinder of the first spacer pattern 13. Accordingly, under one interpretation, the second spacer layer 161 covers an upper surface of the first spacer pattern 13 to form the void/air gap.
Alternatively, in the same field of endeavor, Sukekawa discloses in FIGs. 4A-7B:
a spacer layer (11 in FIG. 5B, [0026]) covers an upper surface of a spacer pattern (3 labeled in FIG. 1B, [0025]) so as to form an air gap (void 11b, [0026]) in a cylinder of the spacer pattern (3 would form a cylinder as 10 forms cylinders in FIGs. 3A-3B, and since 10 is used as a mask to dry etch layers 3 and 4, [0025], layers 3 and 4 would form cylinders after dry etching 3 and 4 using 10 as a mask).
Sukekawa further teaches The present invention provides a technique of forming densely-packed contact-hole patterns in a semiconductor device, and more particularly, a method of manufacturing a semiconductor device, in which a high-precision hole pattern is formed by a self-align double patterning technique, [0006].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the second spacer layer to cover the upper surface of the first space pattern so as to form a void/air gap in a cylinder of the first spacer pattern as taught by Sukekawa in order to form a densely packed contact hole pattern in which high precision hole pattern is formed as further taught by Sukekawa.
Claim(s) 12-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wan in view of Lin, further in view of Goldstein, further in view of Sukekawa as applied to claim 11, further in view of Shim.
RE: Claim 12, Wan in view of Lin, further in view of Goldstein, further in view of Sukekawa does not explicitly disclose The method for manufacturing a semiconductor device according to claim 11, wherein
the first hole pattern is formed to be a hexagonal close-packed arrangement in which each of the patterns is arranged at each of vertexes of a regular hexagon and a center point of the regular hexagon when viewed from a stacking direction of the layer to be processed and the first hard mask layer.
However, in the same field of endeavor, Shim discloses:
The plurality of first guide-forming holes may be arranged in a regular form. For example, the first guide-forming holes H1 may be arranged in a hexagonal array or a matrix array, [0063].
In FIG. 2A, Shim discloses:
a first hole pattern (H1) is formed to be a hexagonal close-packed arrangement in which each of the patterns is arranged at each of vertexes of a regular hexagon (vertexes of regular hexagon formed by outer holes H1 in FIG. 2A) and a center point of the regular hexagon (center hole H1) when viewed from a stacking direction of first and second mask layers (vertical stacking direction in FIG. 2B of layers 104, 106, 108, [0045]).
In FIG. 2B, Shim shows the hole pattern H1 is formed in each of the anti-reflection layer 110P, second mask pattern 108P, and first mask pattern 106P, [0062].
In FIG. 7A, Shim shows another hole pattern for 202A in a region consisting of a minimum distance connecting center points of the spacer pattern/openings for PG1 in 202B.
Shim further teaches inventive concepts provide a method of forming fine patterns, which is capable of easily forming a plurality of patterns repeatedly with a fine pitch when forming patterns necessary for manufacturing a highly integrated semiconductor device exceeding a resolution limit of a photolithography process, [0004].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the first hole pattern in the resist mask pattern 123 and the fourth hole pattern 192, 195 as hexagonal close-packed arrangements as taught by Shim in order to form a plurality of patterns with a fine pitch exceeding a resolution limit of photolithography as further taught by Shim.
RE: Claim 13, Wan in view of Lin, Goldstein, Sukekawa, Shim discloses The method for manufacturing a semiconductor device according to claim 12, wherein the first region has a shape of a substantially equilateral triangle when viewed from the stacking direction (Wan teaches 192 may be arranged in hexagonal mode, [0048]; As modified, the fourth hole pattern 192, 195 is in a hexagonal close-packed arrangement; Accordingly, the first region connecting center points of the first spacer pattern 13 or 192 in Wan FIGs. 16-18 would correspond to a region connecting three center points of the spacer pattern/openings for PG1 in 202B in Shim FIG. 7A which has a shape of a substantially equilateral triangle when viewed in a vertical stacking direction of Shim FIG. 7B), and
the third hole pattern is substantially formed at a center point of the first region (Wan FIG. 19 shows the third hole pattern 195 formed near a center point of the first region connecting three points of 13, 192; As modified by Shim, the third hole pattern 195 in Wan would correspond to the hole pattern for 202A in Shim FIG. 7A which is formed at a center point of the first region connecting three center points of holes for PG1).
RE: Claim 14, Wan in view of Lin, Goldstein, Sukekawa, Shim discloses The method for manufacturing a semiconductor device according to claim 12, wherein the fourth hole pattern substantially has the hexagonal close-packed arrangement when viewed from the stacking direction (As modified, the fourth hole pattern would have the hole pattern for PG1, 202A in 202B Shim FIG. 7A which substantially has the hexagonal close-packed arrangement when viewed in the vertical stacking direction of Shim FIG. 7B).
RE: Claim 15, Wan in view of Lin, Goldstein, Sukekawa, Shim discloses The method for manufacturing a semiconductor device according to claim 14, wherein the fourth hole pattern has a pitch that is substantially 1/√3 times a pitch of the first hole pattern (Shim teaches the first pillar-shaped guides PG1 may be arranged in a hexagonal array having a first pitch P1 that is about 1.73 times greater than a bulk cycle L0 of a block copolymer layer 202, [0071]; As modified by Shim, the first hole pattern would have a pitch corresponding to P1 in Shim FIG. 7A, and the fourth hole pattern would have a pitch corresponding to L0 in Shim FIG. 7A, therefore the fourth hole pattern would have a pitch of 1/1.73 times the pitch of the first hole pattern, which is substantially 1/√3 times the pitch of the first hole pattern).
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wan in view of Lin, further in view of Goldstein, further in view of Sukekawa as applied to claim 11, further in view of Hsu.
RE: Claim 16, Wan in view of Lin, Goldstein, Sukekawa discloses The method for manufacturing a semiconductor device according to claim 11,
wherein when the first hard mask layer is formed,
the first hard mask layer is formed by interposing a second mask layer (Wan FIG. 3: 11) between the first hard mask layer and the layer to be processed (Wan FIG. 3 shows the first mask layer 120 is formed by interposing a second mask layer 11 between the first mask layer 120 and the layer to be processed 10), and
when the fourth hole pattern is transferred to the layer to be processed (As discussed below, the fourth hole pattern is transferred to the layer to be processed by transferring the seventh hole pattern to the layer to be processed which is required by the claim),
the fourth hole pattern is transferred to the second mask layer to form a second mask pattern having a fifth hole pattern (Wan FIGs. 18-20 show the fourth hole pattern 192, 195 was transferred to the second mask layer 11 to form a second mask pattern having a fifth hole pattern).
Wan in view of Lin, Goldstein, Sukekawa does not explicitly disclose:
the second mask layer is a second hard mask layer,
a third spacer layer is formed on a side wall of the fifth hole pattern and removing the second hard mask pattern to form a third spacer pattern being cylindrical and arranged at a position of the fifth hole pattern,
a fourth spacer layer is formed covering the upper surface of the layer to be processed outside the third spacer pattern, and covering an upper surface of the third spacer pattern so as to form a second air gap in a cylinder of the third spacer pattern,
the fourth spacer layer covering the upper surface of the third spacer pattern is removed to open the fifth hole pattern again and the fourth spacer layer overlapping a second region consisting of a minimum distance connecting center points of the third spacer pattern is removed to form a fourth spacer pattern having a sixth hole pattern, to form a seventh hole pattern including the fifth hole pattern opened in the third spacer pattern and the sixth hole pattern opened in the fourth spacer pattern, and
the fourth hole pattern is transferred to the layer to be processed via the second hard mask layer by transferring the seventh hole pattern to the layer to be processed.
However, Goldstein teaches:
Because reflections occur at interfaces when there is an index of refraction mismatch between the materials on each side of the interface, in Deep UV (DUV) lithography reflections from the top and bottom resist interfaces may be so strong that prominent standing waves may be created in the resist. Photons may be absorbed in a first pass as the light enters the photoresist and in a second pass as photons are reflected from the substrate surface. To improve resolution and critical dimension (CD) control, standing waves may be minimized in DUV lithography by the use of anti-reflective hardmasks (bottom ARCS) to control the reflectivity at the interface, [0014].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the second mask layer 11 to be a hard mask layer as taught by Goldstein in order to improve resolution and critical dimension control as further taught by Goldstein.
In the same field of endeavor, Hsu discloses:
The method of the invention can repeated any number of times to create a contact hole comprised of any number of different width openings (each successive opening having a smaller width than the previous opening) that are formed using any number of spacers. The basic process of the invention--1 spacer formation (*E.g., FIGS. 3 & 4), 2 etch narrower opening (e.g., FIG. 5), and 3 spacer formation (FIGS. 3 & 4) . . . .--can be repeated any number of times to create the desired contact hole having a desired aspect ratio, Col. 2, lines 9-20.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to repeat the process of FIGs. 3-20 as taught by Hsu in order to create a hole pattern having a desired aspect ratio.
Wan as modified by Lin, Goldstein, Sukekawa, Hsu would disclose:
a third spacer layer (another 131 from Wan FIG. 6) is formed on a side wall of the fifth hole pattern (As modified, the another 131 would be formed on a side wall of the fifth hole pattern of the second mask 11 in FIG. 20 Wan) and removing the second hard mask pattern to form a third spacer pattern (another 13 or 192 in 13 from Wan FIG. 7) being cylindrical and arranged at a position of the fifth hole pattern (Wan FIG. 7 shows the first mask pattern 12 was removed to form a first spacer pattern 13 arranged at a position of the second hole pattern; FIGs. 7-8 show 13, 192 is cylindrical; Accordingly, when repeated, the process would include removing the second hard mask pattern 11 to form a third spacer pattern 13 or 192 being cylindrical and arranged at a position of the fifth hole pattern of 11),
a fourth spacer layer (another 161 from Wan FIG. 17) is formed covering the upper surface of the layer to be processed outside the third spacer pattern (Another 161 would at least cover an upper surface of 10 outside the third spacer pattern 13 or 192 as shown in Wan FIG. 17), and covering an upper surface of the third spacer pattern so as to form a second air gap in a cylinder of the third spacer pattern (Wan FIG. 17 shows that a void/air gap is formed in a cylinder of the spacer pattern 13 while the spacer layer 161 covers an upper surface of the third spacer pattern 13, where the void/air gap is defined by 161 within the cylinder of the first spacer pattern 13; Alternatively, it would have been obvious to form an air gap in a cylinder of the third spacer pattern as taught by Sukekawa in order to form a densely packed contact hole pattern in which high precision hole pattern is formed as further taught by Sukekawa),
the fourth spacer layer covering the upper surface of the third spacer pattern is removed to open the fifth hole pattern again (another 192; Wan FIG. 18 shows the fourth spacer layer 161 would be removed to open or expose the open pattern 192 in the third spacer pattern 13) and the fourth spacer layer overlapping a second region (second region in Wan FIG. 16 consisting of minimum distance connecting center points of 13 or 192) consisting of a minimum distance connecting center points of the third spacer pattern is removed to form a fourth spacer pattern (another 16 from Wan FIG. 18) having a sixth hole pattern (another 195), to form a seventh hole pattern (another 192, 195 as shown in FIG. 18) including the fifth hole pattern (the another 192) opened in the third spacer pattern and the sixth hole pattern (another 195) opened in the fourth spacer pattern, and
the fourth hole pattern is transferred to the layer to be processed via the second hard mask layer by transferring the seventh hole pattern to the layer to be processed (Wan FIGs. 18-20 show the fourth hole pattern 192, 195 would be transferred to the layer to be processed 10 via the second mask layer 11, and as modified, the fourth hole pattern 192, 195 would be transferred to the layer to be processed 10 by transferring the seventh hole pattern 192, 195 to the layer to be processed 10).
Claim(s) 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wan in view of Lin, further in view of Goldstein, further in view of Sukekawa, further in view of Hsu as applied to claim 16, further in view of Shim.
RE: Claim 17, Wan in view of Lin, Goldstein, Sukekawa, Hsu does not explicitly disclose The method for manufacturing a semiconductor device according to claim 16, wherein
the first hole pattern is formed to be a hexagonal close-packed arrangement in which each of the patterns is arranged at each of vertexes of a regular hexagon and a center point of the regular hexagon when viewed from a stacking direction of the first and second hard mask layers, and
the fourth hole pattern substantially has the hexagonal close-packed arrangement when viewed from the stacking direction.
However, in the same field of endeavor, Shim discloses:
The plurality of first guide-forming holes may be arranged in a regular form. For example, the first guide-forming holes H1 may be arranged in a hexagonal array or a matrix array, [0063].
In FIGs. 2A, 7A, Shim discloses:
a first hole pattern (H1) is formed to be a hexagonal close-packed arrangement in which each of the patterns is arranged at each of vertexes of a regular hexagon (vertexes of regular hexagon formed by outer holes H1 in FIG. 2A) and a center point of the regular hexagon (center hole H1) when viewed from a stacking direction of first and second mask layers (vertical stacking direction in FIG. 2B of first and second mask layers 106, 108, [0045]);
a fourth hole pattern (hole pattern for PG1, 202A in 202B) substantially has the hexagonal close-packed arrangement when viewed from the stacking direction.
In FIG. 2B, Shim shows the hole pattern H1 is formed in each of the anti-reflection layer 110P, second mask pattern 108P, and first mask pattern 106P, [0062].
In FIG. 7A, Shim shows another hole pattern for 202A in a region consisting of a minimum distance connecting center points of the spacer pattern/openings for PG1 in 202B.
Shim further teaches inventive concepts provide a method of forming fine patterns, which is capable of easily forming a plurality of patterns repeatedly with a fine pitch when forming patterns necessary for manufacturing a highly integrated semiconductor device exceeding a resolution limit of a photolithography process, [0004].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the first hole pattern in the resist mask pattern 123, the fourth hole pattern 192, 195, and the seventh hole pattern 192, 195 as hexagonal close-packed arrangements as taught by Shim in order to form a plurality of patterns with a fine pitch exceeding a resolution limit of photolithography as further taught by Shim.
RE: Claim 18, Wan in view of Lin, Goldstein, Sukekawa, Hsu, Shim discloses The method for manufacturing a semiconductor device according to claim 17, wherein the seventh hole pattern substantially has the hexagonal close-packed arrangement when viewed from the stacking direction (As modified by Shim, the seventh hole pattern substantially has the hexagonal close-packed arrangement when viewed from the stacking direction).
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wan in view of Lin, further in view of Goldstein, further in view of Sukekawa, further in view of Hsu, further in view of Shim as applied to claim 18, further in view of Park.
RE: Claim 19, Wan in view of Lin, Goldstein, Sukekawa, Hsu, Shim does not explicitly disclose The method for manufacturing a semiconductor device according to claim 18, wherein the seventh hole pattern has a pitch that is substantially 1/3 times a pitch of the first hole pattern.
However, in the same field of endeavor, Park discloses a method of forming a fine pattern, which may relatively easily implement a fine-pitch pattern that is necessary to manufacture a highly-integrated semiconductor device that transcends a resolution limit in a photolithography process, [0004].
Park discloses the plurality of guide patterns GP_6 are repetitively formed at a fourth guide pitch Pg_4, [0154];
Park further discloses the first block 650 a and the second block 650 b of the fine pattern layer 650 are repetitively disposed at a fourth block pitch Pb_4, [0154].
Park further discloses The first block 350 a and the second block 350 b of the fine pattern layer 350 are disposed in a contact hole pattern, [0120].
Park further discloses According to Equation 8, when n=2, the fourth guide pitch Pg_4 is about three times the fourth block pitch Pb_4, [0155], see FIGs. 6D.
Accordingly, the later pitch Pb_4 is 1/3 times the earlier pitch Pg_4.
Park further discloses in order to implement a fine-pitch pattern to manufacture a highly-integrated semiconductor device that transcends a resolution limit in a photolithography process, a pattern density is increased by adjusting a pattern pitch, [0045].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the seventh hole pattern to have a pitch that is 1/3 times the pitch of the first hole pattern as taught by Park in order to implement a fine pitch pattern with increased pattern density as further taught by Park.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wan in view of Lin, further in view of Goldstein, further in view of Hsu.
RE: Claim 20, Wan discloses A pattern forming method (pattern forming method in FIGs. 3-22, [0035], [0072]) comprising:
forming first and second mask layers (120, 11, respectively in FIG. 3, [0042]) in order of the second mask layer (11) and the first mask layer (120) from a side of a lower layer (top side of 10);
forming a resist mask pattern (123; 123 is a photoresist layer [0040]) having a first hole pattern formed above the first mask layer (FIG. 3 shows 123 having a first hole pattern above the first mask layer 120);
transferring the first hole pattern to the first mask layer to form a first mask pattern (12 in FIG. 5, [0042]) having a second hole pattern (FIG. 5 shows the first hole pattern was transferred to the first mask layer 120 to form a first mask pattern 12 having a second hole pattern 191; Wan teaches 12 is constituted by the remaining initial second mask layer 120, [0042]);
forming a first spacer layer (131 in FIG. 6) on a side wall of the second hole pattern and removing the first mask pattern to form a first spacer pattern (13 or 192 in 13 in FIG. 7) being cylindrical and arranged at a position of the second hole pattern (FIG. 7 shows the first mask pattern 12 was removed to form a first spacer pattern 13 arranged at a position of the second hole pattern; FIGs. 7-8 show 13, 192 is cylindrical);
forming a second spacer layer (161 in FIG. 17) covering an upper surface of the second mask layer (11) outside the first spacer pattern, and removing the second spacer layer overlapping a first region (region in FIG. 16 consisting of minimum distance connecting center points of 13 or 192) consisting of a minimum distance connecting center points of the first spacer pattern to form a second spacer pattern (16 in FIG. 18 ) having a third hole pattern (195), to form a fourth hole pattern (192, 195) including the first spacer pattern and the third hole pattern included in the second spacer pattern (FIGs. 16-18 show partially removing second spacer layer 161 overlapping a first region consisting of a minimum distance connecting center points of the first spacer pattern 13, 192 to form a second spacer pattern 16 having a third hole pattern 195, to form a fourth hole pattern 192, 195 including the first spacer pattern 192 and the third hole pattern 195 included in the second spacer pattern);
transferring the fourth hole pattern to the second mask layer to form a second mask pattern having a fifth hole pattern (FIG. 20 shows the fourth hole pattern 192, 195 was transferred to the second mask layer 11 to form a second mask pattern having a fifth hole pattern).
Wan does not explicitly disclose:
the first hole pattern of the resist mask pattern was formed using lithography;
the first and second mask layers are first and second hard mask layers;
forming a third spacer layer on a side wall of the fifth hole pattern, and removing the second hard mask pattern to form a third spacer pattern being cylindrical and arranged at a position of the fifth hole pattern; and
forming a fourth spacer layer covering an outside of the third spacer pattern, and removing the fourth spacer layer overlapping a second region consisting of a minimum distance connecting center points of the third spacer pattern to form a fourth spacer pattern having a sixth hole pattern, to form a seventh hole pattern including the third spacer pattern and the sixth hole pattern included in the fourth spacer pattern.
In the same field of endeavor, Lin discloses:
A photoresist layer is then formed on the hard mask by a suitable fabrication process, for example, but not limited to, spin-on coating. The photoresist layer is then patterned by a suitable photolithography process to form a pattern of holes arranged in position corresponding to the pairs of the bottom via openings 121 to be formed, [0013].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use photolithography to form the first hole pattern of the resist mask pattern 123 as this would have been obvious to try since Wan discloses 123 is a photoresist, [0040], and photolithography is one suitable solution for forming a pattern of holes in a photoresist identified by Lin and this would have had a reasonable expectation of success, see MPEP 2143.
In the same field of endeavor, Goldstein teaches:
Because reflections occur at interfaces when there is an index of refraction mismatch between the materials on each side of the interface, in Deep UV (DUV) lithography reflections from the top and bottom resist interfaces may be so strong that prominent standing waves may be created in the resist. Photons may be absorbed in a first pass as the light enters the photoresist and in a second pass as photons are reflected from the substrate surface. To improve resolution and critical dimension (CD) control, standing waves may be minimized in DUV lithography by the use of anti-reflective hardmasks (bottom ARCS) to control the reflectivity at the interface, [0014].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the first and second mask layers 120, 11 to be hard mask layers as taught by Goldstein in order to improve resolution and critical dimension control as further taught by Goldstein.
In the same field of endeavor, Hsu discloses:
The method of the invention can repeated any number of times to create a contact hole comprised of any number of different width openings (each successive opening having a smaller width than the previous opening) that are formed using any number of spacers. The basic process of the invention--1 spacer formation (*E.g., FIGS. 3 & 4), 2 etch narrower opening (e.g., FIG. 5), and 3 spacer formation (FIGS. 3 & 4) . . . .--can be repeated any number of times to create the desired contact hole having a desired aspect ratio, Col. 2, lines 9-20.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to repeat the process of FIGs. 3-20 of Wan as taught by Hsu in order to create a hole pattern having a desired aspect ratio.
Wan as modified by Lin, Goldstein, Hsu would disclose:
forming a third spacer layer (another 131 from Wan FIG. 6) on a side wall of the fifth hole pattern (As modified, the another 131 would be formed on a side wall of the fifth hole pattern of the second mask 11 in FIG. 20 Wan), and removing the second hard mask pattern to form a third spacer pattern (another 13 or 192 in 13 from Wan FIG. 7) being cylindrical and arranged at a position of the fifth hole pattern (Wan FIG. 7 shows the first mask pattern 12 was removed to form a first spacer pattern 13 arranged at a position of the second hole pattern; FIGs. 7-8 show 13, 192 is cylindrical; Accordingly, when repeated, the process would include removing the second hard mask pattern 11 to form a third spacer pattern 13 or 192 being cylindrical and arranged at a position of the fifth hole pattern of 11); and
forming a fourth spacer layer (another 161 from Wan FIG. 17) covering an outside of the third spacer pattern (Another 161 would at least cover outside the third spacer pattern 13 or 192 as shown in Wan FIG. 17), and removing the fourth spacer layer overlapping a second region (second region in FIG .16 consisting of minimum distance connecting center points of 13 or 192) consisting of a minimum distance connecting center points of the third spacer pattern to form a fourth spacer pattern (another 16 from Wan FIG. 18) having a sixth hole pattern (another 195), to form a seventh hole pattern (another 192, 195 as shown in FIG. 18) including the third spacer pattern and the sixth hole pattern included in the fourth spacer pattern (As modified, the process would include partially removing the fourth spacer layer 161 overlapping a second region consisting of a minimum distance connecting center points of the third spacer pattern 13, 192 to form a fourth spacer pattern 16 having a sixth hole pattern 195, to form a seventh hole pattern 192, 195 including the third spacer pattern 192 and the sixth hole pattern 195 included in the fourth spacer pattern).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL ANGUIANO whose telephone number is (703)756-1226. The examiner can normally be reached Monday through Friday.
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/MICHAEL ANGUIANO/Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899
Prosecution Insights