DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 1 is objected to because of the following informalities:
Claim 1, line 18 should read as, “a third insulator on a [[firth]] fifth surface of the second . . .”
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeong et al. (US 20230320066 A1; hereinafter "Jeong") in view of Sung (US 20250081427 A1).
Regarding claim 1, Jeong discloses:
a memory device (FIG. 3A: semiconductor device 100) comprising:
a first semiconductor (FIG. 3A: each structure LS includes two active layers 130—“the first semiconductor” may map to the active layer 130 highest on the z-axis within the structure LS above the structure LS nearest to the substrate 101; hereinafter, referred to as an “upper active layer 130” of the “first structure LS”);
a first memory element that is in contact with a first surface of the first semiconductor facing a first direction (FIG. 3A: capacitor structure CAP; specifically, a first electrode 171 corresponding with the upper active layer 130 of structure LS);
a first insulator on a second surface of the first semiconductor facing a second direction crossing the first direction (FIG. 3A: gate dielectric 145 corresponding with the upper active layer 130 of first structure LS);
a first conductor including a first portion (FIG. 3A: gate structure 140 (WL) corresponding with the upper active layer 130 of first structure LS);
a second insulator on a third surface of the first semiconductor facing a third direction opposite to the second direction (FIG. 3A: gate dielectric 155 corresponding with the upper active layer 130 of first structure LS);
a second semiconductor located farther in the third direction than the first semiconductor (FIG. 3A: each structure LS includes two active layers 130—“the second semiconductor” may map to an active layer lower on the z-axis; hereinafter, referred to as a “lower active layer 130”);
a second memory element that is in contact with a fourth surface of the second semiconductor facing the first direction (FIG. 3A: capacitor structure CAP corresponding with the lower active layer 130);
a third insulator on a [fifth] surface of the second semiconductor facing the third direction (FIG. 3A: gate dielectric 145 corresponding with the lower active layer 130);
a second conductor on a surface of the third insulator facing the third direction (FIG. 3A: gate structure 140 (WL) corresponding with the lower active layer 130);
a fourth insulator on a sixth surface of the second semiconductor facing the second direction (FIG. 3A: gate dielectric 155 corresponding with the lower active layer 130); and
a third conductor that is in contact with the second insulator and the fourth insulator (FIG. 3A: gate structure 150 (BG)).
However, Jeong does not disclose, a first conductor including a second portion being a portion other than the first portion, a length of the first portion of the first conductor in the first direction being larger than a length of the second portion of the first conductor in the first direction. This limitation is interpreted to be drawn to the projecting portion of the conductor 30(WL) illustrated in FIG. 5.
Sung, in the same field of endeavor, discloses:
“Referring back to FIG. 1C, each of the upper horizontal line G1 and the lower horizontal line G2 may have a width in the second direction D2, for example, the width of an overlapping portion that overlaps with the horizontal layer HL, which is greater than the width of a portion that does not overlap with the horizontal layer HL. Due to this difference in width, the second conductive line DWL may have a notch-shaped sidewall. The second conductive line DWL may include a channel overlapping portion WLP and a channel non-overlapping portion NOL. The channel overlapping portion WLP may refer to a portion that overlaps with a channel CH of the horizontal layer HL, and the channel non-overlapping portion NOL may refer to a portion that does not overlap with the horizontal layer HL. The channel overlapping portion WLP may have a cross shape or a rhombus shape.” (see para. [0029])
In other words, the conductive line DWL comprises a first portion, the overlapping portion WLP, and a second portion, the non-overlapping portion NOL, wherein the overlapping portion WLP is clearly larger in the direction D2 as depicted in FIG. 1C.
Therefore, it would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the first conductor of Jeong (gate structure 140 (WL)) with the extended, overlapping portion WLP of the conductive line DWL of Sung. One of ordinary skill in the art would have been motivated to make this modification for the benefit of increasing the overlapping surface area of the conductive line over the horizontal layer.
Regarding claim 2, Jeong discloses the first conductor and the second conductor extend in a fourth direction (FIG. 3B: gate structure 140 extends in the +y-direction) crossing the first direction and the third direction, and the third conductor extends in a fifth direction opposite to the fourth direction (FIG. 3B: gate structure 150 extends in the -y-direction).
Regarding claim 3, Jeong discloses a fourth conductor (FIG. 3B: a first contact plug 180A connected to gate structure 140 corresponding with the upper active layer 130 of structure LS) that is in contact with the first conductor at an end of the first conductor facing the fourth direction, the fourth conductor extending in the second direction (FIG. 3B: all gate plugs 180 extend in the +z-direction); a fifth conductor (FIG. 3B: first contact plug 180A connected to gate structure 140 corresponding with the lower active layer 130) that is in contact with the second conductor at an end of the second conductor on the side of the fourth direction, the fifth conductor extending in the second direction; and a sixth conductor (FIG. 3B: a second contact plug 180B connected to the gate structure 150) that is in contact with the third conductor at an end of the third conductor facing the fifth direction, the sixth conductor extending in the second direction.
Regarding claim 4, Jeong discloses a seventh conductor (FIG. 3A: vertical conductive patterns 160 (BL)) that extends in the second direction and is in contact with the first semiconductor and the second semiconductor.
Regarding claim 5, a third semiconductor located further in the second direction than the first semiconductor (FIG. 3A: the lower active layer 130 in the structure LS above the first structure LS; hereinafter “the second structure LS”); a third memory element that is in contact with a surface of the third semiconductor on the side of the first direction (FIG. 3B: capacitor structure CAP corresponding with the lower active layer 130 of the second structure LS); a fifth insulator on a surface of the third semiconductor on the side of the third direction (FIG. 3A: gate dielectric 145 corresponding with the lower active layer 130 of the second structure LS); an eighth conductor on a surface of the fifth insulator on the side of the third direction (FIG. 3A: gate structure 145 corresponding with the lower active layer 130 of the second structure LS); and a sixth insulator located between the first conductor and the eighth conductor, the sixth insulator being in contact with the first conductor and the eighth conductor (FIG. 3A: interlayer insulating layer 121 combined with gate dielectrics 145).
Regarding claim 6, Jeong discloses the first semiconductor and the second semiconductor have a first interval (FIG. 3A: the distance between the centerlines of the upper and lower active layers 130 of the first structure LS), the first semiconductor and the third semiconductor have a second interval (FIG. 3A: the distance between the centerlines of the upper active layer 130 of the first structure LS and the lower active layer 130 of the second structure LS), and the second interval is greater than the first interval (FIG. 3A: the “second” interval between the active layers 130 is clearly greater than the “first” interval).
Regarding claim 7, Jeong discloses a fourth semiconductor (FIG. 3A: the upper active layer 130 in the most lowest structure LS above the substrate 101; hereinafter the “third structure LS”) located further in the third direction than the second semiconductor; a fourth memory element that is in contact with a surface of the fourth semiconductor on the side of the first direction (FIG. 3A: the capacitor structure CAP corresponding with the upper active layer 130 of the third structure LS); a seventh insulator on a surface of the fourth semiconductor on the side of the second direction (FIG. 3A: gate dielectric 145); a ninth conductor on a surface of the seventh insulator on the side of the second direction (FIG. 3A: gate structure 145); and an eighth insulator located between the second conductor and the ninth conductor, the eighth insulator being in contact with the second conductor and the ninth conductor (FIG. 3A: interlayer insulating layer 121 combined with gate dielectrics 145).
Regarding claim 8, Jeong discloses the second semiconductor and the fourth semiconductor have a third interval (FIG. 3A: the distance between the centerlines of the lower active layer 130 of the first structure LS and the upper active layer 130 of the third structure LS), and the third interval is greater than the first interval (FIG. 3A: the “third” interval between the active layers 130 is clearly greater than the “first” interval).
Regarding claim 9, Jeong discloses the first memory element includes a capacitor, and the second memory element includes a capacitor (FIG. 3A: capacitor structure CAP).
Response to Arguments
Applicant’s arguments, see 7, filed 08/14/2026, with respect to 35 U.S.C. 112 rejection of claims 3 and 7-8 (with respect to "parallel to") have been fully considered and are persuasive. The rejections of claims 3 and 7-8 has been withdrawn.
Applicant’s arguments, see pages 8-9, filed 08/14/2026, with respect to the rejection(s) of claim(s) 1-9 under 35 U.S.C. 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Sung , necessitated by the amendment set forth by the applicant to overcome the 35 U.S.C. 102 rejection.
Allowable Subject Matter
Claims 10-13 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding independent claim 10, the prior art made of record and considered pertinent to the applicant’s disclosure, taken individually or in combination, does not teach or suggest the claimed limitation(s) of "the second semiconductor having a second length different from the first length in the first direction and containing the dopant of a second concentration different from the first concentration," in combination with the other limitations recited in the claim. Claims 11-13 depend on claim 10; and therefore, would be allowable for at least these reasons.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JUSTIN BRYCE HEISTERKAMP whose telephone number is (703)756-1095. The examiner can normally be reached M-F 0800-1700.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JUSTIN BRYCE HEISTERKAMP/Examiner, Art Unit 2827 /AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
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