DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitations "a first memory element that is in contact with a surface of the first semiconductor on a side of a first direction" (emphasis added) in lines 4-6 of page 1; “a first insulator on a surface of the first semiconductor on a side of a second direction crossing the first direction; . . . in lines 7-9; and “a second insulator on a surface of the first semiconductor on a side of a third direction opposite to the second direction; . . .” in lines 12-14. The orientations of the recited contact surfaces of the first semiconductor and the insulator is unclear because the spatial relationships of the sides of these components and their respective directions is inadequately expressed. Moreover, there should be unique designations assigned to the multiple surfaces of the semiconductor in the claim to clearly and distinctly describe the invention.
FIG. 6 shows the semiconductor 25a is in contact with the memory element CC by a surface that is perpendicular with the x-direction (the first direction). Applicant is advised to amend lines 4-6 of claim 1 to read as, “a first memory element that is in contact with a first surface of the first semiconductor , wherein the first surface of the first semiconductor is perpendicular to a first direction; . . .” Alternatively, applicant may also amend lines 4-6 to read as, ““a first memory element that is in contact with a first surface of the first semiconductor facing a first direction; . . .””
Applicant is advised to amend lines 7-9 to read as, “a first insulator on a second surface of the first semiconductor , wherein the second surface of the first semiconductor is perpendicular to a second direction crossing the first direction; . . .” (or consistent with the alternative recommendation above), because the gate insulator 26, illustrated in FIG. 6, is in contact with a surface of semiconductor 25a that is perpendicular with the +z-direction (the second direction); and to amend lines 12-14 to read as, “a second insulator on a third surface of the first semiconductor , wherein the third surface of the first semiconductor is perpendicular to a third direction opposite to the second direction; . . .” (or consistent with the alternative recommendation).
Claim 1 recites the limitation "the side of the second direction" in lines 11 and 25. There is insufficient antecedent basis for this limitation in the claim. Applicant is advised to amend this limitation consistent with the recommendations above. That is, lines 10-11 should read as, “a first conductor on a surface of the first insulator , wherein the surface of the first insulator is perpendicular to the second direction; . . .” (or consistent with the alternative recommendation).
Claim 1 contains similar defects with the limitation “the side of the first direction” in lines 18-19 and the limitation “the side of the third direction” in lines 21 and 23. Applicant is advised to amend lines 18-19, 21, and 23 consistent with the recommendation above.
Claims 2-9 are rejected because they depend on claim 1; therefore, claims 2-9 contain at least the same defect(s).
Claim 3 recites the limitations "a fourth conductor that is in contact with the first conductor at an end of the first conductor on a side of the fourth direction, . . ." (emphasis added) in lines 9-10 of page 2, and “a sixth conductor that is in contact with the third conductor at an end of the third conductor on a side of the fifth direction, . . .” (emphasis added) in lines 17-18. The orientation of the side of the fourth direction and the side of the fifth direction is unclear.
FIG. 7 illustrates word lines 30 in contact with the conductive plugs 36 on a side (at their ends) that is parallel with the +y-direction (the fourth direction) and perpendicular to (or facing) the +z-direction (the second direction), and back gates 21 in contact with conductive plugs 33 on a side that is parallel with the -y-direction (the fifth direction) and perpendicular (or facing) the +z-direction (the second direction). Applicant is advised to amend claim 3 lines 9-10 to read as, "a fourth conductor that is in contact with the first conductor at an end of the first conductor on a side parallel to the fourth direction and facing the second direction, . . ." Likewise, lines 17-18 should read as, “a sixth conductor that is in contact with the third conductor at an end of the third conductor on a side parallel to the fifth direction and facing the second direction, . . .”
Claim 3 recites the limitation "the side of the fourth direction" in lines 13-14 of page 2. There is insufficient antecedent basis for this limitation in the claim. Applicant is advised to amend the limitations in lines 12-15 in a fashion likewise to the recommended amended of lines 9-10 above.
Claim 5 recites the limitations "the side of the first direction" in lines 1-2 of page 3 and “the side of the third direction” in lines 4 and 6. There is insufficient antecedent basis for this limitation in the claim. Applicant is advised to amend claim 5 consistent with the recommendations set forth in the indefiniteness rejection of claim 1 above.
Claims 6-8 are rejected because they depend on claim 5; therefore, claims 6-8 contain at least the same defect(s).
Claim 7 recites the limitation "the side of the first direction" in lines 21-22 of page 3 and “the side of the second direction” in lines 24 and 26 of page 3. There is insufficient antecedent basis for this limitation in the claim. Applicant is advised to amend claim 7 consistent with the recommendations set forth in the indefiniteness rejection of claim 1 above.
Claim 8 is rejected because it depends on claim 7; therefore, claim 8 contains at least the same defect(s).
Claim 10 recites “a first memory element that is in contact with a surface of the first semiconductor on a side of a second direction crossing the first direction” (emphasis added) in lines 14-16 of page 4, and “a second memory element that is in contact with a surface of the second semiconductor on the side of the second direction” (emphasis added) in lines 26-27 of page 4 to line 1 of page 5. The orientations of the recited contact surfaces of the first and second semiconductor is unclear because the spatial relationships of the sides of these components and their respective directions is inadequately expressed.
FIG. 64 illustrates a plurality of semiconductors 25 (interpreted to contain the first and second semiconductors) that are in contact with the memory element CC through a surface that is perpendicular with the x-direction (the second direction). FIG. 65 illustrates the plurality of semiconductors 25 extending in the +y-direction (interpreted as a first and second length in the first direction).
Applicant is advised to amend lines 14-16 of claim 10 to read as, “a first memory element that is in contact with a surface of the first semiconductor , wherein the surface of the first semiconductor is perpendicular to a second direction crossing the first direction; . . .” Alternatively, applicant may also amend lines 14-16 to read as, “a first memory element that is in contact with a surface of the first semiconductor facing a second direction crossing the first direction; . . .” Lines 26-27 of page 4 to line 1 of page 5, should be amended accordingly.
Claim 10 recites the limitation "the side of the second direction" in Lines 26-27 of page 4 to line 1 of page 5. There is insufficient antecedent basis for this limitation in the claim. See recommendations in the indefiniteness rejection of claim 10 above.
Claims 11-13 are rejected because the depend on claim 10; therefore, claims 11-13 contain at least the same defect(s).
The term “a less concentration” in claim 12 is a relative term which renders the claim indefinite. The term “a less concentration” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. Applicant is advised amending claim 12 to read as, “. . . wherein a semiconductor among the plurality of semiconductors having a smaller length than another semiconductor among the plurality of semiconductors along the first direction contains the dopant of a [[less]] lower concentration than the another semiconductor.
Claim Objections
Claim 11 objected to because of the following informalities:
Claim 11, lines 7-9, should read as, “. . ., the plurality of semiconductors being spaced apart and arranged in the third direction, and each of the plurality of semiconductors including the dopant, . . .”
Claim 11, line 20 of page 5, should read as, “lengths of the plurality of semiconductors along the first direction . . .”
Claim 11, lines 12-14 of page 5, should read as, “a plurality of respective concentrations of the dopant are distributed throughout the plurality of semiconductors based on the varying lengths of the plurality of semiconductors along the first direction .”
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jeong et al. (US 20230320066 A1; hereinafter "Jeong").
Regarding claim 1, Jeong discloses a memory device (FIG. 3A: semiconductor device 100) comprising: a first semiconductor (FIG. 3A: each structure LS includes two active layers 130—“the first semiconductor” may map to the active layer 130 highest on the z-axis within the structure LS above the structure LS nearest to the substrate 101; hereinafter, referred to as an “upper active layer 130” of the “first structure LS”); a first memory element that is in contact with a surface of the first semiconductor on a side of a first direction (FIG. 3A: capacitor structure CAP; specifically, a first electrode 171 corresponding with the upper active layer 130 of structure LS); a first insulator on a surface of the first semiconductor on a side of a second direction crossing the first direction (FIG. 3A: gate dielectric 145 corresponding with the upper active layer 130 of first structure LS); a first conductor on a surface of the first insulator on the side of the second direction (FIG. 3A: gate structure 140 (WL) corresponding with the upper active layer 130 of first structure LS); a second insulator on a surface of the first semiconductor on a side of a third direction opposite to the second direction (FIG. 3A: gate dielectric 155 corresponding with the upper active layer 130 of first structure LS); a second semiconductor located further in the third direction than the first semiconductor (FIG. 3A: each structure LS includes two active layers 130—“the second semiconductor” may map to an active layer lower on the z-axis; hereinafter, referred to as a “lower active layer 130”); a second memory element that is in contact with a surface of the second semiconductor on the side of the first direction (FIG. 3A: capacitor structure CAP corresponding with the lower active layer 130); a third insulator on a surface of the second semiconductor on the side of the third direction (FIG. 3A: gate dielectric 145 corresponding with the lower active layer 130); a second conductor on a surface of the third insulator on the side of the third direction (FIG. 3A: gate structure 140 (WL) corresponding with the lower active layer 130); a fourth insulator on a surface of the second semiconductor on the side of the second direction (FIG. 3A: gate dielectric 155 corresponding with the lower active layer 130); and a third conductor that is in contact with the second insulator and the fourth insulator (FIG. 3A: gate structure 150 (BG)).
Regarding claim 2, Jeong discloses the first conductor and the second conductor extend in a fourth direction (FIG. 3B: gate structure 140 extends in the +y-direction) crossing the first direction and the third direction, and the third conductor extends in a fifth direction opposite to the fourth direction (FIG. 3B: gate structure 150 extends in the -y-direction).
Regarding claim 3, Jeong discloses a fourth conductor (FIG. 3B: a first contact plug 180A connected to gate structure 140 corresponding with the upper active layer 130 of structure LS) that is in contact with the first conductor at an end of the first conductor on a side of the fourth direction, the fourth conductor extending in the second direction (FIG. 3B: all gate plugs 180 extend in the +z-direction); a fifth conductor (FIG. 3B: first contact plug 180A connected to gate structure 140 corresponding with the lower active layer 130) that is in contact with the second conductor at an end of the second conductor on the side of the fourth direction, the fifth conductor extending in the second direction; and a sixth conductor (FIG. 3B: a second contact plug 180B connected to the gate structure 150) that is in contact with the third conductor at an end of the third conductor on a side of the fifth direction, the sixth conductor extending in the second direction.
Regarding claim 4, Jeong discloses a seventh conductor (FIG. 3A: vertical conductive patterns 160 (BL)) that extends in the second direction and is in contact with the first semiconductor and the second semiconductor.
Regarding claim 5, a third semiconductor located further in the second direction than the first semiconductor (FIG. 3A: the lower active layer 130 in the structure LS above the first structure LS; hereinafter “the second structure LS”); a third memory element that is in contact with a surface of the third semiconductor on the side of the first direction (FIG. 3B: capacitor structure CAP corresponding with the lower active layer 130 of the second structure LS); a fifth insulator on a surface of the third semiconductor on the side of the third direction (FIG. 3A: gate dielectric 145 corresponding with the lower active layer 130 of the second structure LS); an eighth conductor on a surface of the fifth insulator on the side of the third direction (FIG. 3A: gate structure 145 corresponding with the lower active layer 130 of the second structure LS); and a sixth insulator located between the first conductor and the eighth conductor, the sixth insulator being in contact with the first conductor and the eighth conductor (FIG. 3A: interlayer insulating layer 121 combined with gate dielectrics 145).
Regarding claim 6, Jeong discloses the first semiconductor and the second semiconductor have a first interval (FIG. 3A: the distance between the centerlines of the upper and lower active layers 130 of the first structure LS), the first semiconductor and the third semiconductor have a second interval (FIG. 3A: the distance between the centerlines of the upper active layer 130 of the first structure LS and the lower active layer 130 of the second structure LS), and the second interval is greater than the first interval (FIG. 3A: the “second” interval between the active layers 130 is clearly greater than the “first” interval).
Regarding claim 7, Jeong discloses a fourth semiconductor (FIG. 3A: the upper active layer 130 in the most lowest structure LS above the substrate 101; hereinafter the “third structure LS”) located further in the third direction than the second semiconductor; a fourth memory element that is in contact with a surface of the fourth semiconductor on the side of the first direction (FIG. 3A: the capacitor structure CAP corresponding with the upper active layer 130 of the third structure LS); a seventh insulator on a surface of the fourth semiconductor on the side of the second direction (FIG. 3A: gate dielectric 145); a ninth conductor on a surface of the seventh insulator on the side of the second direction (FIG. 3A: gate structure 145); and an eighth insulator located between the second conductor and the ninth conductor, the eighth insulator being in contact with the second conductor and the ninth conductor (FIG. 3A: interlayer insulating layer 121 combined with gate dielectrics 145).
Regarding claim 8, Jeong discloses the second semiconductor and the fourth semiconductor have a third interval (FIG. 3A: the distance between the centerlines of the lower active layer 130 of the first structure LS and the upper active layer 130 of the third structure LS), and the third interval is greater than the first interval (FIG. 3A: the “third” interval between the active layers 130 is clearly greater than the “first” interval).
Regarding claim 9, Jeong discloses the first memory element includes a capacitor, and the second memory element includes a capacitor (FIG. 3A: capacitor structure CAP).
Allowable Subject Matter
Claim 10 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
Claims 11-13 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding independent claim 10, the prior art made of record and considered pertinent to the applicant’s disclosure, taken individually or in combination, does not teach or suggest the claimed limitation(s) of "the second semiconductor having a second length different from the first length in the first direction and containing the dopant of a second concentration different from the first concentration," in combination with the other limitations recited in the claim. Claims 11-13 depend on claim 10; and therefore, would be allowable for at least these reasons.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JUSTIN BRYCE HEISTERKAMP whose telephone number is (703)756-1095. The examiner can normally be reached M-F 0800-1700.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JUSTIN BRYCE HEISTERKAMP/Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
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