Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
In response to the Communications dated September 10, 2024, claims 1-18 are active in
this application.
Specification
If there are cross-reference to related applications, please include the
respective patent numbers, if known.
Foreign Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)
(d), which papers have been placed of record in the file.
Information Disclosure Statement
The information disclosure statements filed September 10, 2024 have been considered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claim 1, the phrase 'capable of' is indefinite because it is functional language that does not inherently limit the structural features of the apparatus, rendering the claim scope unclear. Additionally, it has been held that the recitation that an element is “capable of” performing a function is not a positive limitation but only requires the ability to so perform. It does not constitute a limitation in any patenable sense. In re Hutchison, 69 USPQ 138.
In claim 1, the claim requires alternating between a positive first voltage and a negative second voltage. However, it does not define the number of cycles, the duration of each pulse, or the interval between them. If the switching behavior is highly sensitive to the pulse timing, it would require “undue experimentation” to find out the particular point of which the switching would occur. Similar issues are found in claim 7.
In claim 1, the phrase "At the end of the write process": This timing is vague. Does it mean the final microsecond, the last pulse, or after the voltage is entirely removed? Similar issues are found in claim 7.
In claim 1, the phrase requires "alternately applying" a first and second voltage, but then states the second voltage is applied "at the end." If it is alternating, it is unclear if the sequence ends on the first or second voltage. If the final state must be the second voltage, then the action is not truly "alternating" at the very last step, but rather terminating, which creates ambiguity in the scope of the claim. Similar issues are found in claim 7.
In claim 1, the recitation describes two separate processes for the write process: Process A: apply V1 AND V2, with V2 at the end; and Process B: apply V3 and V4, with V4 at the end. It is unclear if these two are distinct phases of one write process, or two alternative options. Similar issues are found in claim 7.
In claim 1, the recitation states that a second (negative) voltage is applied "at the end of the write process" to switch to the second state. However, later in the same sentence, it states that a fourth (positive) voltage is applied "at the end of the write process" to perform that same switching action. If both a negative voltage and a positive voltage are applied at the "end," it is unclear which one actually finishes the process. Similar issues are found in claim 7.
Claims 2-15 are rejected because they depend on the indefiniteness of the claims from which they depend.
Claims 16 and 17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claim 16, the claim requires alternating between a positive first voltage and a negative second voltage. However, it does not define the number of cycles, the duration of each pulse, or the interval between them. If the switching behavior is highly sensitive to the pulse timing, it would require “undue experimentation” to find out the particular point of which the switching would occur.
In claim 16, the phrase "At the end of the write process": This timing is vague. Does it mean the final microsecond, the last pulse, or after the voltage is entirely removed?
In claim 16, the phrase requires "alternately applying" a first and second voltage, but then states the second voltage is applied "at the end." If it is alternating, it is unclear if the sequence ends on the first or second voltage. If the final state must be the second voltage, then the action is not truly "alternating" at the very last step, but rather terminating, which creates ambiguity in the scope of the claim.
In claim 16, the recitation describes two separate processes for the write process: Process A: apply V1 AND V2, with V2 at the end; and Process B: apply V3 and V4, with V4 at the end. It is unclear if these two are distinct phases of one write process, or two alternative options.
In claim 16, the recitation states that a second (negative) voltage is applied "at the end of the write process" to switch to the second state. However, later in the same sentence, it states that a fourth (positive) voltage is applied "at the end of the write process" to perform that same switching action. If both a negative voltage and a positive voltage are applied at the "end," it is unclear which one actually finishes the process.
Claim 17 is rejected because it depends on the indefiniteness of the claim from which it depends.
Claim 18 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claim 18, the claim requires alternating between a positive first voltage and a negative second voltage. However, it does not define the number of cycles, the duration of each pulse, or the interval between them. If the switching behavior is highly sensitive to the pulse timing, it would require “undue experimentation” to find out the particular point of which the switching would occur. Similarly, the claim also has the same alternating process with regards to the claimed “third voltage having negative polarity and a fourth voltage having positive polarity”, “a fifth voltage having positive polarity and a sixth voltage having negative polarity”, and “a seventh voltage having negative polarity and an eighth voltage having positive polarity”.
In claim 18, the recitation describes four separate processes for the write process: Process A: apply V1 AND V2; Process B: apply V3 and V4; Process C: apply V5 AND V6; and Process D: apply V7 AND V8. It is unclear if these four are distinct phases of one write process, or four alternative options.
Claim Rejections- 35 U.S.C. § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 8, 9 and 12-15 is/are rejected, as understood, under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al. [US Patent Application # 20190206489].
With respect to claim 1, Wang et al. disclose a storage device comprising: a memory cell including a first conductive layer, a second conductive layer, and a memory layer that is between the first and second conductive layers and can switch between a plurality of states, the states including a first state and a second state in which electrical resistance of the memory layer is higher than the first state ["...memory cell 105..." – pars. 0025-0027, 0056-0059, and 0098 (205-a maybe considered as first conductive layer, 205-b maybe considered as second conductive layer, and 220 maybe considered as memory layer)]; and a control circuit capable of executing a write process by which the states of the memory cell are switched ["...write operation having a first sequence of different polarities..." – par. 0098 (Wang et al. authorizes the alternation and reversal of polarities, which is the mechanism behind the claimed recitation’s specific alternating voltage sequence.], wherein the control circuit is configured to: in the write process to switch the memory layer from the second state to the first state, alternately apply to the second conductive layer a first voltage having positive polarity and a second voltage having negative polarity , an absolute value of the second voltage being larger than an absolute value of the first voltage ["(e.g., as illustrated by the timing diagram 300)" – par. 0098 (Wang et al. points to a "timing diagram" (implied specification), which is the standard place where specific amplitude differences (like those in the claimed recitation) are defined.)], and the second voltage being applied to the second conductive layer at the end of the write process ["first write operation having a first sequence... forward write operation" – par. 0098 (Wang et al. establishes that the sequence of voltages matters and is controlled, allowing for specific ending voltages as detailed in the claimed recitations.)], and in the write process to switch the memory layer from the first state to the second state, alternately apply to the second conductive layer a third voltage having negative polarity and a fourth voltage having positive polarity ["second write operation having a second sequence of polarities opposite from the first" – par. 0098 (Wang et al. directly describes a "reverse" process (switching to opposite state) involving opposing polarities, as detailed in claimed recitation.)], an absolute value of the fourth voltage being larger than an absolute value of the third voltage, and the fourth voltage being applied to the second conductive layer at the end of the write process [“…applying a voltage to one or both of the access line 110-a or the access line 115-a. The write voltage may be applied with a positive polarity or a negative polarity across the memory cell 105-a.” – par. 0060].
With respect to claim 8, Wang et al. disclose the memory layer is in contact with the first and second conductive layers. See fig. 2.
With respect to claim 9, Wang et al. disclose the memory layer is a single layer. See fig. 2.
With respect to claim 12, Wang et al. disclose the memory layer includes: an oxide or oxynitride of a first element that is at least one element selected from the group consisting of zirconium, aluminum, yttrium, tantalum, lanthanum, cerium, titanium, hafnium, magnesium, scandium, vanadium, and niobium, antimony, and a second element that is at least one element selected from the group consisting of carbon, boron, nitrogen, silicon, and tin. See par. 0203.
With respect to claim 13, Wang et al. disclose the first conductive layer includes tungsten, and the second conductive layer includes carbon. See par. 0203.
With respect to claim 14, Wang et al. disclose the memory layer has a nonlinear current-voltage characteristic in which a current rises at a specific threshold voltage, and the threshold voltage changes by application of a predetermined voltage [“a ferroelectric memory cell 105 may include a capacitor with a ferroelectric material as a dielectric material, which may support non-linear polarization properties. In some examples, different levels of charge of a capacitor may represent different logic states (e.g., supporting more than two logic states in a respective memory cell 105)”. See par. 0019.
With respect to claim 15, Wang et al. disclose a plurality of first wirings [110]; and a plurality of second wirings [115] that intersect the plurality of first wirings, wherein the memory cell is provided in a region where one of the plurality of first wirings and one of the plurality of second wirings intersect each other. See fig. 1.
Claim(s) 16 is/are rejected, as understood, under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al. [US Patent Application # 20190206489].
With respect to claim 16, Wang et al. disclose a method of controlling a storage device including a memory cell including a first conductive layer, a second conductive layer, and a memory layer that is between the first and second conductive layers and can switch between a plurality of states, the states including a first state and a second state in which electrical resistance of the memory layer is higher than the first state ["...memory cell 105..." – pars. 0025-0027, 0056-0059, and 0098 (205-a maybe considered as first conductive layer, 205-b maybe considered as second conductive layer, and 220 maybe considered as memory layer)], the method comprising: performing a write process by which the states of the memory cell are switched ["...write operation having a first sequence of different polarities..." – par. 0098 (Wang et al. authorizes the alternation and reversal of polarities, which is the mechanism behind the claimed recitation’s specific alternating voltage sequence.], the write process including: for switching the memory layer from the second state to the first state, alternately applying to the second conductive layer a first voltage having positive polarity and a second voltage having negative polarity, an absolute value of the second voltage being larger than an absolute value of the first voltage ["(e.g., as illustrated by the timing diagram 300)" – par. 0098 (Wang et al. points to a "timing diagram" (implied specification), which is the standard place where specific amplitude differences (like those in the claimed recitation) are defined.)], and the second voltage being applied to the second conductive layer at the end of the write process ["first write operation having a first sequence... forward write operation" – par. 0098 (Wang et al. establishes that the sequence of voltages matters and is controlled, allowing for specific ending voltages as detailed in the claimed recitations.)], and for switching the memory layer from the first state to the second state, alternately applying to the second conductive layer a third voltage having negative polarity and a fourth voltage having positive polarity ["second write operation having a second sequence of polarities opposite from the first" – par. 0098 (Wang et al. directly describes a "reverse" process (switching to opposite state) involving opposing polarities, as detailed in claimed recitation.)], an absolute value of the fourth voltage being larger than an absolute value of the third voltage, and the fourth voltage being applied to the second conductive layer at the end of the write process [“…applying a voltage to one or both of the access line 110-a or the access line 115-a. The write voltage may be applied with a positive polarity or a negative polarity across the memory cell 105-a.” – par. 0060].
Conclusion
For applicant’s benefit portions of the cited reference(s) have been cited to aid in
the review of the rejection(s). While every attempt has been made to be thorough and consistent within the rejection it is noted that the PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS. See MPEP 2141.02 VI.
When responding to the Office action, Applicants are advised to provide
the Examiner with line and page numbers of the application and/or references cited to assist the Examiner in the prosecution of this case.
Any inquiry concerning this communication or earlier communications
from the Examiner should be directed to Michael T. Tran whose telephone number is (571) 272-1795. Interview agendas may be emailed to Michael.tran@uspto.gov. The Examiner can normally be reached on Monday-Thursday from 6:00AM-4:30 P.M.
Any inquiry of a general nature or relating to the status of this application.
should be directed to the Group receptionist whose telephone number is (571) 272-1650.
/MICHAEL T TRAN/Primary Examiner, Art Unit 2827 February 25, 2026