DETAILED ACTION
This Final Office Action is responsive to communications: 06/11/2026.
Applicant amended claims 1, 11, and 14; no other claims are cancelled or, added. Claims 1-20 are pending. Claims 1, 11 and 14 are independent.
Examiner Notes
A) Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. B) Per MPEP 2173.04 “If the claim is too broad because it reads on the prior art, a rejection under either 35 U.S.C. 102 or 103 would be appropriate”. C) Examiner cites particular paragraphs or columns and lines in the references as applied to Applicant's claims for the convenience of the Applicant. Other passages and figures may apply as well. Per MPEP 2141.02 VI prior art must be considered in its entirety. D) Per MPEP 2112 and 2112 V, express, implicit, and inherent disclosures of a prior art reference may be relied upon in the rejection of claims under 35 U.S.C. 102 or 103.
Notice of Pre-AIA or AIA Status
3. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
No Priority
4. See ADS, no priority is in the record.
Drawings
5. The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following claim language must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Regarding claims 1, 11, and 14, "... discharging…bitline… to a base voltage during charging the corresponding plate-line to a predefined plate line read voltage value..." must be shown in the drawings, or cancelled from the claims. Timing diagrams associated with the relevant biasing scheme do not show this feature. Such drawings e.g. Fig. 4, Fig. 7, Fig. 8 pertinent to the limitation do not show this feature.
Corrected drawing sheets in compliance with 37 CFR 1.121 (d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as "amended." If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either "Replacement Sheet" or "New Sheet" pursuant to 37 CFR 1.121 (d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
6. The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL. — The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
7. Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claims 1, 11, and 14 recite "... discharging...bitline… to a base voltage during charging the corresponding plate-line to a predefined plate line read voltage value...". The drawings illustrate that the discharging feature happens prior to plate line charging but not "during" plate line charging. For example, supporting para [0052] (supporting para admitted by applicant in page 8 of Remarks) teaches that "...During this read-out operation, the corresponding bitline BL(n*) may be first discharged to the base voltage, VB, (e.g., ground). Then, the corresponding patelline PL(n*) is charged (at a plateline charging time step tpL) to a plateline voltage, VPL, read, having a predefined plateline read voltage value..." So, the language constitutes new matter. While the specification provides disclosure for discharging, it does not provide disclosure for the “…during charging the corresponding plate-line...”. This language is not supported by the original disclosure and therefore constitutes new matter. (See also 37 C.F.R. 1.121(f), MPEP 608.04, 706.03(o)). All dependent claims inclusive of claims 1-20 are rejected under this category.
For prior art rejection, it is interpreted that the discharging happens during the over-all readout process.
Claim Rejections - 35 USC § 112
8. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. — The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
9. Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 11, and 14 recite "... discharging...bitline… to a base voltage during charging the corresponding plate-line to a predefined plate line read voltage value...". which is are not clear and are not readable on Figures e.g. Fig. 4, Fig. 7, and Fig. 8 and disclosure para [0052]. The limitation is vague, unclear, subject to multiple interpretation due to inconsistency in claim language and disclosure. All dependent claims inclusive of claims 1-20 are rejected under this category. Appropriate correction is required.
For prior art rejection, it is interpreted that the discharging happens during the over-all readout process.
Claim Rejections - 35 USC § 103
10. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
11. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
12. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
13. Claims 1-5, 7-9, and 11-19 is/are rejected under 35 U.S.C. 103 as being obvious over Kitagawa (US 2024/0212735 A1), in view of Jahne et al. (US 11,081,159 B1) and Kim et al. (US 2019/0027204 A1).
Regarding independent claim 1, Kitagawa teaches a memory cell arrangement (para [0027], Fig. 1: 100 “ferroelectric memory array” and memory device. See Fig. 1-Fig. 8 for illustrated components and functionality. See Examiner’s Markup version of Kitagawa Figure 5), comprising:
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a plurality of bitlines (Fig. 1: 115’s “data-line”);
a plurality of wordlines (Fig. 1: 110’s “word line”);
a plurality of plate lines (Fig. 1: 120 “plate line”);
a plurality of capacitive memory cells (Fig. 1: 105’s “ferroelectric” memory cell), wherein each capacitive memory cell (see e.g., Fig. 1: 105-1) of the plurality of capacitive memory cells is connected to and selectively addressable (row address, column address for a cell) via a corresponding bitline (Fig. 1: 115-1) of the plurality of bitlines, a corresponding wordline (Fig. 1: WL1) of the plurality of wordlines, and a corresponding plate line (Fig. 1: PL) of the plurality of plate-lines (para [0033]);
a read-out circuit (Fig. 1: 155, 150, 160 combined) configured to carry out a read-out operation to read out a memory state of a capacitive memory cell of the plurality of capacitive memory cells by addressing (row address, column address for a cell) the capacitive memory cell (Fig. 1: 105-1) via its corresponding bitline (Fig. 1: 115-1), corresponding wordline (Fig. 1: WL1), and corresponding plate line ((Fig. 1: PL. see para [0033]-para [0034]),
the read-out operation (Fig. 5: 505 “sensing”, para [0074]) comprising:
discharging the corresponding bitline to a base voltage during charging the corresponding plate-line to a predefined plate line read voltage value (See Fig 5);
after the plate line voltage is charged to the predefined plate-line read voltage value (at Fig. 5: t1y), applying a wordline voltage at the corresponding wordline (Fig. 5: selected WL is applied with 520-1 voltage. Para [0080]) to thereby charge the corresponding bitline to a characteristic voltage (Fig. 5: 500/ 495 chart; para [0084], para [0085]: storage node changes to “1” and “0” characteristic levels during t2-t4 and storage node is coupled to bit line via access transistor); and
determining (para [0023]: using “sense component”) the memory state of the capacitive memory cell based on sensing the characteristic voltage (“…sensing the current memory state stored on the target memory cell…”, see e.g., para [0023], para [0080]).
Kitagawa is silent with respect to-
discharging the corresponding bitline to a base voltage during charging the corresponding plate-line to a predefined plate line read voltage value.
a plurality of plate lines in array and plate lines being addressable.
Jahne teaches discharging the corresponding bitline to a base voltage during charging the corresponding plate-line to a predefined plate line read voltage value (col. 8, lines 55-63; and col. 10, lines 42-53: “…charge/discharge the bitline 112 to the characteristic voltage, Vchar…”. See also Fig. 1A, Fig. 1B disclosure: 102 upper conductor coupled to PL is charged and bitline 112 is discharged/ discharged)
Kim teaches a plurality of plate lines employed in FeRAM array of Fig. 1 and plate lines or plate line segments are addressable (“segmented plate”, see e.g. para [0017], para [0019], para [0050], para [0058]).
Kitagawa, Jahne and Kim are in the same field of endeavor of sensing operation method of ferroelectric memory and they are in analogous field of art. Jahne teaches sensing ferroelectric memory, biasing scheme during sense of such memory. Kim teaches a memory cell arrangement (Fig. 1), comprising: a plurality of bitlines (Fig. 1: DL’s); a plurality of wordlines (Fig. 1: WL’s); a plurality of plate lines (“segmented plate”, see e.g. para [0017], para [0019], para [0050]), a plurality of capacitive memory cells (para [0019], para [0024]: ferroelectric cells). Kim Fig. 5 further teaches sense operation and biasing of DL, WL, PL lines.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine Jahne and Kim’s teachings into the memory apparatus of Kitagawa such that array with sense biasing scheme and plate line structure can be employed in order to reduce remnant polarization related read error (Jahne col. 6, lines 9-10) and mitigate/ reduce power consumption problem (Kim para [0017]).
Regarding claim 2, Kitagawa, Jahne and Kim teach the memory cell arrangement according to claim 1. Kitagawa teaches wherein the read-out circuit (Fig. 1: 155, 150, 160) comprises a sense amplifier (Fig. 1: 155) for sensing the characteristic voltage and determining the memory state based on the characteristic voltage (para [0023]).
Regarding claim 3, Kitagawa, Jahne and Kim teach the memory cell arrangement according to claim 1. Kitagawa teaches wherein the read-out operation (Fig. 5) comprises that the corresponding plate line is charged to the predefined plate line read voltage value by applying a plate line voltage having the predefined plate line read voltage value for a predefined plate line charging time interval (limitation taken as t1-t1y charging time when PL voltage is 515-1), and
that the wordline voltage is applied after the predefined plate line charging time interval (Fig. 5: at t1y WL is applied with voltage 520-1).
Regarding claim 4, Kitagawa, Jahne and Kim teach the memory cell arrangement according to claim 1. Kitagawa teaches wherein the read-out circuit comprises a pull-down transistor (Fig. 1: 160 nmos) coupled to the corresponding bitline (Fig. 1: DL’s) and
configured to connect the corresponding bitline to the base voltage (para [0078]: applied 0V) in the case that an activation signal (Fig. 5: control signal for 160) is applied at the pull-down transistor (Fig. 1: when 160 gate path is open);
wherein the read-out operation comprises that the base voltage (Fig. 5 and para [0078]: applied 0V) is applied at the corresponding bitline (Fig. 5: DL’s) during the charging of the corresponding plate line (Fig. 5: during t1-t1y) by providing the activation signal to the pull-down transistor (Fig. 5: control signal for 160).
Regarding claim 5, Kitagawa, Jahne and Kim teach the memory cell arrangement according to claim 1. Kitagawa is silent with respect to bringing the bitline into a floating state prior to applying the wordline voltage at the wordline.
Kim teaches wherein the read-out operation further comprises bringing the corresponding bitline into a floating state prior to applying the wordline voltage at the corresponding wordline (Fig. 5 in context of para [0036]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Kim into the teachings of Kitagawa such that claimed limitation can be implemented in order to reduce disturbance.
Regarding claim 7, Kitagawa, Jahne and Kim teach the memory cell arrangement according to claim 1. Kitagawa teaches wherein the base voltage is a ground voltage (para [0078], Fig. 5: DL is applied with 0V).
Regarding claim 8, Kitagawa, Jahne and Kim teach the memory cell arrangement according to claim 1. Kitagawa teaches wherein each capacitive memory cell of the plurality of capacitive memory cells is a remanent-polarizable memory cell (FIG. 2, FIG.3 shows hysteresis curves of a remanent-polarizable memory cell).
Regarding claim 9, Kitagawa, Jahne and Kim teach the memory cell arrangement according to claim 1. Kitagawa teaches wherein the read-out circuit comprises:
one or more sense amplifiers (Fig. 1: each set of 150, 160, 155 taken as a sense amplifier), wherein each sense amplifier of the one or more sense amplifiers is coupled between two neighboring bitlines of the plurality of bitlines (see Fig. 1),
wherein the one or more sense amplifiers are connected to a precharge line (connected to PL terminal which supply 0V); and
a pull-down transistor (Fig. 1: 160) coupled to the precharge line (Fig. 1: connected to PL terminal which supply 0V) and configured to selectively connect the precharge line to the base voltage (Fig. 1: connected to PL terminal which selectively supply 0V based on gate 160).
Regarding independent claim 11, Kitagawa teaches a memory cell arrangement (para [0027], Fig. 1: 100 “ferroelectric memory array” and memory device. See Fig. 1-Fig. 8 for illustrated components and functionality. See Examiner’s Markup version of Kitagawa Figure 5), comprising:
a bitline (Fig. 1: 115’s “data-line”), a wordline (Fig. 1: 110’s “word line”), and a plate line (Fig. 1: 120 “plate line”);
a capacitive memory cell (Fig. 1: 105’s “ferroelectric” memory cell) connected to and addressable (row address, column address for cell addressing) via the bitline (Fig. 1: DL), the wordline (Fig. 1: WL), and the plate line (Fig. 1: PL);
a read-out circuit (Fig. 1: 155, 150, 160 combined) configured to carry out a read-out operation to read out a memory state of the capacitive memory cell (see para [0033]-para [0034]),
the read-out operation (Fig. 5: 505 “sensing”, para [0074]) comprising:
discharging the corresponding bitline to a base voltage during charging the corresponding plate line to a predefined plate line read voltage value (Fig. 5);
after the plate line voltage is charged to the predefined plate line read voltage value (at Fig. 5: t1y), applying a wordline voltage at the wordline (Fig. 5: selected WL is applied with 520-1 voltage. Para [0080]) to thereby charge the bitline to a characteristic voltage (see Fig. 5: 500/ 495 chart; para [0084], para [0085]: storage node changes to “1” and “0” characteristic levels during t2-t4 and storage node is coupled to bit line via access transistor operated by word line); and
determining (para [0023]: using “sense component”) the memory state of the capacitive memory cell based on sensing the characteristic voltage (“…sensing the current memory state stored on the target memory cell…”, see e.g., para [0023], para [0080]).
Kitagawa is silent with respect to-
discharging the corresponding bitline to a base voltage during charging the corresponding plate-line to a predefined plate line read voltage value.
a plurality of plate lines in array and plate lines being addressable.
Jahne teaches discharging the corresponding bitline to a base voltage during charging the corresponding plate-line to a predefined plate line read voltage value (col. 8, lines 55-63; and col. 10, lines 42-53: “…charge/discharge the bitline 112 to the characteristic voltage, Vchar…”. See also Fig. 1A, Fig. 1B disclosure: 102 upper conductor coupled to PL is charged and bitline 112 is discharged/ discharged)
Kim teaches a plurality of plate lines employed in FeRAM array of Fig. 1 and plate lines or plate line segments are addressable (“segmented plate”, see e.g. para [0017], para [0019], para [0050], para [0058]).
Kitagawa, Jahne and Kim are in the same field of endeavor of sensing operation method of ferroelectric memory and they are in analogous field of art. Jahne teaches sensing ferroelectric memory, biasing scheme during sense of such memory. Kim teaches a memory cell arrangement (Fig. 1), comprising: a plurality of bitlines (Fig. 1: DL’s); a plurality of wordlines (Fig. 1: WL’s); a plurality of plate lines (“segmented plate”, see e.g. para [0017], para [0019], para [0050]), a plurality of capacitive memory cells (para [0019], para [0024]: ferroelectric cells). Kim Fig. 5 further teaches sense operation and biasing of DL, WL, PL lines.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine Jahne and Kim’s teachings into the memory apparatus of Kitagawa such that array with sense biasing scheme and plate line structure can be employed in order to reduce remnant polarization related read error (Jahne col. 6, lines 9-10) and mitigate/ reduce power consumption problem (Kim para [0017]).
Regarding claim 12, Kitagawa, Jahne and Kim teach the memory cell arrangement according to claim 11. Kitagawa teaches wherein the read-out circuit comprises a sense amplifier (Fig. 1: each set of 150, 160, and associated sese component 155 taken as a sense amplifier) for sensing the characteristic voltage (ferroelectric cell sensing) and determining the memory state based on the characteristic voltage (para [0023]),
wherein the sense amplifier is connected to a precharge line (Fig. 1: connected via 160 to PL terminal and precharge supply that provides 0V shown in Fig. 5), and
wherein the read-out circuit further comprises a pull-down transistor (Fig. 1: 160 nmos) coupled to the precharge line (Fig. 1) and configured to selectively connect the precharge line to the base voltage (Fig. 5: based on gate control voltage 160 connects PL terminal and precharge supply that provides 0V shown in Fig. 5).
Regarding claim 13, Kitagawa, Jahne and Kim teach the memory cell arrangement according to claim 11. Kitagawa teaches wherein the base voltage is a ground voltage (para [0078]: 0V).
Regarding independent claim 14, Kitagawa teaches a method of reading (method of reading “ferroelectric memory array” and memory device. See Fig. 1-Fig. 8 for illustrated components and functionality. See Examiner’s Markup version of Kitagawa Figure 5) a capacitive memory cell (Fig. 1: 105’s “ferroelectric” memory cell) which is connected to a bitline (Fig. 1: DL), a plate line (Fig. 1: PL), and a wordline (Fig. 1: WL),
the method comprising:
discharging the bitline to a base voltage during charging the plate line to a predefined plate line read voltage value (See Fig. 5);
after the plate line voltage is charged to the predefined plate line read voltage value (at Fig. 5: t1y), applying a wordline voltage at the wordline Fig. 5: selected WL is applied with 520-1 voltage. Para [0080]) to thereby charge the bitline to a characteristic voltage (Fig. 5: 500/ 495 chart; para [0084], para [0085]: storage node changes to “1” and “0” levels during t2-t4 and storage node is coupled to bit line via access transistor); and
determining (para [0023]: using “sense component”) a memory state of the capacitive memory cell based on sensing the characteristic voltage (“…sensing the current memory state stored on the target memory cell…”, see e.g., para [0023], para [0080]).
Kitagawa is silent with respect to-
discharging the corresponding bitline to a base voltage during charging the corresponding plate-line to a predefined plate line read voltage value.
a plurality of plate lines in array and plate lines being addressable.
Jahne teaches discharging the corresponding bitline to a base voltage during charging the corresponding plate-line to a predefined plate line read voltage value (col. 8, lines 55-63; and col. 10, lines 42-53: “…charge/discharge the bitline 112 to the characteristic voltage, Vchar…”. See also Fig. 1A, Fig. 1B disclosure: 102 upper conductor coupled to PL is charged and bitline 112 is discharged/ discharged)
Kim teaches a plurality of plate lines employed in FeRAM array of Fig. 1 and plate lines or plate line segments are addressable (“segmented plate”, see e.g. para [0017], para [0019], para [0050], para [0058]).
Kitagawa, Jahne and Kim are in the same field of endeavor of sensing operation method of ferroelectric memory and they are in analogous field of art. Jahne teaches sensing ferroelectric memory, biasing scheme during sense of such memory. Kim teaches a memory cell arrangement (Fig. 1), comprising: a plurality of bitlines (Fig. 1: DL’s); a plurality of wordlines (Fig. 1: WL’s); a plurality of plate lines (“segmented plate”, see e.g. para [0017], para [0019], para [0050]), a plurality of capacitive memory cells (para [0019], para [0024]: ferroelectric cells). Kim Fig. 5 further teaches sense operation and biasing of DL, WL, PL lines.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine Jahne and Kim’s teachings into the memory apparatus of Kitagawa such that array with sense biasing scheme and plate line structure can be employed in order to reduce remnant polarization related read error (Jahne col. 6, lines 9-10) and mitigate/ reduce power consumption problem (Kim para [0017]).
Regarding claim 15, Kitagawa, Jahne and Kim teach the method according to claim 14. Kitagawa teaches wherein charging the corresponding plate line to the predefined plate line read voltage value comprises applying a plate line voltage having the predefined plate line read voltage value for a predefined plate line charging time interval (limitation taken as t1-t1y charging time when PL voltage is 515-1); and
wherein the wordline voltage is applied after the predefined plate line charging time interval (Fig. 5: at t1y WL is applied with voltage 520-1).
Regarding claim 16, Kitagawa, Jahne and Kim teach the method according to claim 14. Kitagawa is silent with respect to bringing the bitline into a floating state prior to applying the wordline voltage at the wordline.
Kim teaches method of bringing the bitline into a floating state prior to applying the wordline voltage at the wordline (Fig. 5 in context of para [0036]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Kim into the teachings of Kitagawa such that claimed limitation can be implemented in order to reduce disturbance.
Regarding claim 17, Kitagawa, Jahne and Kim teach the method according to claim 14. Kitagawa teaches wherein the base voltage is applied at the bitline (para [0078]: applied 0V to DL) using a pull-down transistor (Fig. 1: 16) which is connected to precharge line associated with a sense amplifier (Fig. 1: connected to PL terminal which supply 0V) for sensing the characteristic voltage and determining the memory state based on the characteristic voltage (para [0023]).
Regarding claim 18, Kitagawa, Jahne and Kim teach the method according to claim 14. Kitagawa teaches wherein the base voltage is a ground voltage (para [0078], Fig. 5: DL is applied with 0V).
Regarding claim 19, Kitagawa, Jahne and Kim teach the method according to claim 14. Kitagawa teaches wherein the capacitive memory cell is a remanent-polarizable memory cell (FIG. 2, FIG.3 shows hysteresis curves of a remanent-polarizable memory cell).
Art rejection not provided for all claims, see 112(a), 112b(b) rejections.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 11, and 14 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. In general, Applicant's arguments filed have been fully considered but they are not persuasive: see new formulated rejections.
Prior Art Not Relied Upon
The prior art made of record and not relied upon (MPEP § 707.05) is considered pertinent to applicant's disclosure: Watanabe (US 20060114740 A1): disclosure applicable for all claims. Madan et al. (US 2007/0211510 A1) is applicable for all claims.
It is suggested that applicant consider all prior arts made of record.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUSHFIQUE SIDDIQUE whose telephone number is (571)270-0424. The examiner can normally be reached 7:00 am-4:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander George Sofocleous can be reached at (571) 272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MUSHFIQUE SIDDIQUE/Primary Examiner, Art Unit 2825
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