Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
Claim(s) 1-10 are rejected under 35 U.S.C. 103 as being unpatentable over Wu (US Patent No. 11424194).
Regarding claim 1, Wu teaches a semiconductor package, comprising: a plurality of semiconductor chips stacked in a first direction (Fig. 7A; A” – D”); a plurality of chip connection terminals disposed between two semiconductor chips disposed adjacent to each other in the first direction among the plurality of semiconductor chips and electrically connecting the two adjacent semiconductor chips (Figs. 7A-7B; 28B” – 28D”); and a plurality of chip support structures disposed between the two adjacent semiconductor chips, wherein the plurality of chip support structures do not electrically connect the two adjacent semiconductor chips, and are spaced apart from the plurality of chip connection terminals in a second direction crossing the first direction (Id.; 50B” – 50D”), wherein a thickness of each of the plurality of chip support structures is greater than a thickness of each of the plurality of chip connection terminals (Fig. 2A points to an alternative embodiment of a die D’ comprising warpage resulting in an edge height that is greater than a height at the center of the die. It is thus considered obvious that one of ordinary skill in the art would form the outer support structures 50B” – 50D” with a greater height/thickness that the bonding structures 28A” – 28D” in order to maintain adequate bonding in accordance with the warped die(s) structure.).
Regarding claim 2, Wu teaches wherein each of the plurality of semiconductor chips includes a substrate (Fig. 3A; 20A’), a front protective layer disposed on a lower surface of the substrate (Id.; 21A’), and a rear protective layer disposed on an upper surface of the substrate (Id.; 29A’), and the plurality of chip support structures extend into a rear protective layer of a semiconductor chip disposed on a lower side among the plurality of semiconductor chips (It is considered obvious that one of ordinary skill in the art would extend the chip support structures into the rear protective layer in order to improve bonding between the chip(s) and said structures.).
Regarding claim 3, Wu teaches wherein the rear protective layer has a groove extending inwardly from an upper surface of the rear protective layer, the groove does not pass through the rear protective layer, and a lower portion of each of the plurality of chip support structures fills the groove (It is considered obvious that one of ordinary skill in the art would form a groove in the rear protective layer in order to improve bonding between the chip(s) and chip support structures while avoiding unnecessary exposure of the underlying electrical structure/connections.).
Regarding claim 4, Wu teaches wherein the lower portion of each of the plurality of chip support structures and the groove extend from an upper side to a lower side and have a tapered shape with a decreasing horizontal width (One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized the shape of the interface between the groove(s) and chip support structure(s) to be a result effective variable. Thus, it would have been obvious to modify the device of Wu to have the claimed shape in order to ease alignment/insertion during fabrication, and since optimum or workable ranges of such variables are discoverable through routine experimentation. See MPEP 2144.05(II)(B) and 2143.).
Regarding claim 5, Wu teaches wherein the lower portion of each of the plurality of chip support structures is downwardly convex, and the groove is inwardly concave from the upper surface of the rear protective layer (One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized the shape of the interface between the groove(s) and chip support structure(s) to be a result effective variable. Thus, it would have been obvious to modify the device of Wu to have the claimed shape in order to ease create a larger contact area with a lower stress concentration and a more gradual load transfer, and since optimum or workable ranges of such variables are discoverable through routine experimentation. See MPEP 2144.05(II)(B) and 2143.).
Regarding claim 6, Wu teaches wherein each of the plurality of chip connection terminals includes a chip conductive pillar and a chip conductive cap covering a lower surface of the chip conductive pillar (Figs. 7A-7B; 22A”, 23A”), and a horizontal width of each of the plurality of chip support structures is greater than a horizontal width of the chip conductive pillar of each of the plurality of chip connection terminals (One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized the horizontal width(s) of each of the plurality of chip support structures to be a result effective variable. Thus, it would have been obvious to modify the device of Wu to have the horizontal width(s) within the claimed range in order to better balance physical stability with electrical conductivity, and since optimum or workable ranges of such variables are discoverable through routine experimentation. See MPEP 2144.05(II)(B) and 2143. Furthermore, it has also been held that the applicant must show that a particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936, (Fed. Cir. 1990). Note that the law is replete with cases in which when the mere difference between the claimed invention and the prior art is some dimensional limitation or other variable within the claims, patentability cannot be found. The instant disclosure does not set forth evidence ascribing unexpected results due to the claimed dimensions. See Gardner v. TEC Systems, Inc., 725 F.2d 1338 (Fed. Cir. 1984), which held that the dimensional limitations failed to point out a feature which performed and operated any differently from the prior art.).
Regarding claim 7, Wu teaches a package substrate disposed below the plurality of semiconductor chips (Figs. 1 and 7A; 100/100”); a plurality of substrate connection terminals disposed between a lowermost semiconductor chip among the plurality of semiconductor chips and the package substrate and electrically connecting the lowermost semiconductor chip to the package substrate (Fig. 7A; 28A”); and a plurality of substrate support structures disposed between the lowermost semiconductor chip and the package substrate, wherein the plurality of substrate support structures do not electrically connect the lowermost semiconductor chip to the package substrate, and are spaced apart from the plurality of substrate connection terminals in the second direction (Id.; 50A”), wherein a thickness of each of the plurality of substrate support structures is greater than a thickness of each of the plurality of substrate connection terminals (Fig. 2A points to an alternative embodiment of a die D’ comprising warpage resulting in an edge height that is greater than a height at the center of the die. It is thus considered obvious that one of ordinary skill in the art would form the outer support structures 50B” – 50D” with a greater height/thickness that the bonding structures 28A” – 28D” in order to maintain adequate bonding in accordance with the warped die(s) structure.).
Regarding claim 8, Wu teaches wherein a horizontal width of each of the plurality of substrate support structures is greater than a horizontal width of each of the plurality of substrate connection terminals (It is considered obvious that one of ordinary skill in the art would form each of the plurality of substrate support structures to have a greater width than each of the plurality of substrate connection terminals in order to redirect any mechanical stress towards the support structures and away from the electrical pathways of the connection terminals.).
Regarding claim 9, Wu teaches wherein a number of the plurality of substrate support structures is greater than a number of the plurality of chip support structures disposed between the two adjacent semiconductor chips in the first direction (It is considered obvious that one of ordinary skill in the art would form a greater number of substrate support structures than chip support structures between the two adjacent semiconductor chips due to the higher physical strain that would naturally form along the substrate support structures as a result of their position on the bottommost/foundational layer of the stacked structure.).
Regarding claim 10, Wu teaches wherein a horizontal width of each of the plurality of substrate support structures has a greater value than a horizontal width of each of the plurality of chip support structures (It is considered obvious that one of ordinary skill in the art would form the substrate support structures to have a greater width than each of the plurality of chip support structures due to the higher physical strain that would naturally form along the substrate support structures as a result of their position on the bottommost/foundational layer of the stacked structure.).
Claim(s) 11-16 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Wu in further view of Noguchi (PGPub No. 20240113030).
Regarding claim 11, Wu teaches a semiconductor package, comprising: a package substrate including a package base insulating layer (Figs. 1 and 7A; 100/100”); a plurality of semiconductor chips (Fig. 7A; A” – D”) each including a substrate (Fig. 3A; 20A’), a front protective layer disposed on a lower surface of the substrate (Id.; 21A’), and a rear protective layer disposed on an upper surface of the substrate (Id.; 29A’), wherein the plurality of semiconductor chips includes a first semiconductor chip disposed on the package substrate and a plurality of second semiconductor chips sequentially stacked on the first semiconductor chip in a first direction (Fig. 7A; A” – D”); a plurality of first chip connection terminals disposed between the package substrate and the first semiconductor chip and electrically connecting the package substrate to the first semiconductor chip (Fig. 7A; 28A”); a plurality of first chip support structures disposed between the package substrate and the first semiconductor chip, wherein the plurality of first chip support structures are spaced apart from the plurality of first chip connection terminals in a second direction (Id.; 50A”); a plurality of second chip connection terminals disposed between two semiconductor chips disposed adjacent to each other in the first direction among the plurality of semiconductor chips, wherein the plurality of second chip connection terminals electrically connect the two adjacent semiconductor chips, and the second direction crosses the first direction (Figs. 7A-7B; 28B” – 28D”); and a plurality of second chip support structures disposed between the two adjacent semiconductor chips, wherein the plurality of second chip support structures extend into the rear protective layer included in a lower semiconductor chip among the two adjacent semiconductor chips (Id.; 50B” – 50D”).
Wu fails to teach a lower solder resist layer covering a lower surface of the package base insulating layer, and an upper solder resist layer covering an upper surface of the package base insulating layer; and wherein the plurality of first chip support structures extend into the upper solder resist layer.
Noguchi teaches a lower solder resist layer covering a lower surface of the package base insulating layer (Fig. 2D-2E; 110b), and an upper solder resist layer covering an upper surface of the package base insulating layer (Id.; 110a); and wherein the plurality of first chip support structures extend into the upper solder resist layer (Fig. 2D; O110a.). Thus, it would have been obvious to a person of ordinary skill in the art (POSITA) prior to the filing date of the claimed invention to combine the teachings of Wu and Noguchi, such that solder resist layers are formed along the lower and upper surfaces of the package base insulating layer in order to better control connections between the overall package substrate and external components by properly separating adjacent connections and preventing undue interference.
Regarding claim 12, Wu in combination with Noguchi teaches wherein the plurality of first chip support structures extend into the upper solder resist layer and do not penetrate through the upper solder resist layer (Fig. 7A of Wu; 50A”. Fig. 2D of Noguchi; O110a. It is considered obvious that one of ordinary skill in the art would form the openings such that they extend into but do not penetrate the solder resist layer 110a of Noguchi in order to improve bonding between the package substrate and chip support structures while avoiding unnecessary exposure of the underlying electrical structure/connections.), and the plurality of second chip support structures extend into the rear protective layer and do not penetrate through the rear protective layer (It is considered obvious that one of ordinary skill in the art would extend the chip support structures into, but not through, the rear protective layer in order to improve bonding between the chip(s) and said structures while avoiding unnecessary exposure of the underlying electrical structure/connections.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Wu and Noguchi, such that the first and second chip support structures extend into, but do not penetrate through, the upper solder resist layer and the rear protective layer respectively in order to the physical stability of the overall device while still protecting the electrical connections found within the package substrate and/or semiconductor chips that do not require any kind of contact with the chip support structures.
Regarding claim 13, Wu in combination with Noguchi teaches wherein each of the plurality of first chip support structures extends into a first groove extending inwardly from an upper surface of the upper solder resist layer (Fig. 7A of Wu; 50A”. Fig. 2D of Noguchi; O110a. It is considered obvious that one of ordinary skill in the art would form the openings O110a into grooves such that they extend into but do not penetrate the solder resist layer 110a of Noguchi in order to improve bonding between the package substrate and chip support structures while avoiding unnecessary exposure of the underlying electrical structure/connections.), each of the plurality of second chip support structures extends into a second groove extending inwardly from an upper surface of the rear protective layer (It is considered obvious that one of ordinary skill in the art would form a groove in the rear protective layer in order to improve bonding between the chip(s) and chip support structures while avoiding unnecessary exposure of the underlying electrical structure/connections.), a horizontal width of the first groove is greater than a horizontal width of each of the plurality of first chip support structures, and a horizontal width of the second groove is greater than a horizontal width of each of the plurality of second chip support structures (It is considered obvious one of ordinary skill in the art would form each of the horizontal widths of the first and second grooves such that their widths are greater than those of the first chip and second chip support structures, respectively, in order to better accommodate each of the pluralities as a whole in the event of defects that may otherwise cause misalignment.).
Regarding claim 14, Wu teaches wherein each of the plurality of first chip connection terminals includes a first chip conductive pillar and a first chip conductive cap covering a lower surface of the first chip conductive pillar (Figs. 7A-7B; 22A”, 23A”), and each of the plurality of second chip connection terminals includes a second chip conductive pillar and a second chip conductive cap covering a lower surface of the second chip conductive pillar (Id.; 22B-D”, 23B-D”), and a horizontal width of each of the plurality of first chip support structures is greater than a horizontal width of the first chip conductive pillar, and a horizontal width of each of the plurality of second chip support structures is greater than a horizontal width of the second chip conductive pillar (One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized the horizontal widths of each of the first and second chip support structures to be a result effective variable. Thus, it would have been obvious to modify the device of Wu to have the horizontal widths within the claimed range in order to better balance physical stability with electrical conductivity, and since optimum or workable ranges of such variables are discoverable through routine experimentation. See MPEP 2144.05(II)(B) and 2143. Furthermore, it has also been held that the applicant must show that a particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936, (Fed. Cir. 1990). Note that the law is replete with cases in which when the mere difference between the claimed invention and the prior art is some dimensional limitation or other variable within the claims, patentability cannot be found. The instant disclosure does not set forth evidence ascribing unexpected results due to the claimed dimensions. See Gardner v. TEC Systems, Inc., 725 F.2d 1338 (Fed. Cir. 1984), which held that the dimensional limitations failed to point out a feature which performed and operated any differently from the prior art.).
Regarding claim 15, Wu teaches wherein the horizontal width of the first chip conductive pillar is about equal to the horizontal width of the second chip conductive pillar (Fig. 2A; 22D’. It is considered obvious that one of ordinary skill in the art would form each conductive pillar to have about the same horizontal width in order to, for example, create a uniform structure that would ensure electrical alignment across all components and/or simplify the fabrication process.), and the horizontal width of the first chip support structure is greater than the horizontal width of the second chip support structure (It is considered obvious that one of ordinary skill in the art would form the first chip support structure to have a greater width than the second chip support structure due to the higher physical strain that would naturally form along the first chip support structures as a result of their position on the bottommost/foundational layer of the stacked structure.).
Regarding claim 16, Wu teaches wherein a number of the plurality of first chip support structures is greater than a number of the plurality of second chip support structures (It is considered obvious that one of ordinary skill in the art would form a greater number of first chip support structures than second chip support structures due to the higher physical strain that would naturally form along the first chip support structures as a result of their position on the bottommost/foundational layer of the stacked structure.).
Regarding claim 18, Wu teaches a semiconductor package, comprising: a package substrate including a package base insulating layer (Figs. 1 and 7A; 100/100”), a plurality of package upper pads disposed on an upper surface of the package base insulating layer (Figs. 6A and 7A; 26S), a plurality of package lower pads disposed on a lower surface of the package base insulating layer (Figs. 1 and 7A; 110), a plurality of connection pads electrically connecting the plurality of package upper pads to the plurality of package lower pads (Id.; 40); a plurality of semiconductor chips including a first semiconductor chip and a plurality of second semiconductor chips sequentially stacked on the package substrate in a first direction (Fig. 7A; A” – D”), wherein the first semiconductor chip and the plurality of second semiconductor chips each include a substrate (Id.), a plurality of rear connection pads disposed on an upper surface of the substrate (Figs. 7A-7B; 26A”-D”), a plurality of front connection pads disposed on a lower surface of the substrate (Id.; 24A”-D”), a plurality of through-electrodes vertically penetrating through at least a portion of the substrate and electrically connecting the plurality of rear connection pads to the plurality of front connection pads (Id.; 40A”-C”), a front protective layer disposed on the lower surface of the substrate and not covering at least a portion of a lower surface of each of the plurality of front connection pads (Fig. 3A; 21A’), and a rear protective layer disposed on the upper surface of the substrate and not covering at least a portion of an upper surface of each of the plurality of rear connection pads (Id.; 29A’); a plurality of first chip connection terminals disposed between the plurality of package upper pads of the package substrate and the plurality of front connection pads of the first semiconductor chip (Fig. 7A; 28A”); a plurality of first chip support structures disposed between the package substrate and the first semiconductor chip, wherein the plurality of first chip support structures are spaced apart from the plurality of first chip connection terminals in a second direction (Id.; 50A”); a plurality of second chip connection terminals disposed between two semiconductor chips disposed adjacent to each other in the first direction among the plurality of semiconductor chips and disposed between the plurality of rear connection pads and the plurality of front connection pads facing each other included in the two adjacent semiconductor chips, wherein the second direction crosses the first direction(Figs. 7A-7B; 28B” – 28D”); and a plurality of second chip support structures disposed between the two adjacent semiconductor chips, wherein the plurality of second chip support structures extend into the rear protective layer included in a lower semiconductor chip among the two adjacent semiconductor chips and do not penetrate through the rear protective layer (Id.; 50B” – 50D”. It is considered obvious that one of ordinary skill in the art would extend the chip support structures into, but not through, the rear protective layer in order to improve bonding between the chip(s) and said structures while avoiding unnecessary exposure of the underlying electrical structure/connections.).
Wu fails to teach an upper solder resist layer covering the upper surface of the package base insulating layer and not covering at least a portion of an upper surface of each of the plurality of package upper pads, and a lower solder resist layer covering the lower surface of the package base insulating layer and not covering at least a portion of a lower surface of each of the plurality of package lower pads; and wherein the plurality of first chip support structures extend into the upper solder resist layer, and do not penetrate through the upper solder resist layer.
Wu in combination with Noguchi teaches an upper solder resist layer covering the upper surface of the package base insulating layer and not covering at least a portion of an upper surface of each of the plurality of package upper pads (Fig. 2D-2E of Noguchi; 110a), and a lower solder resist layer covering the lower surface of the package base insulating layer and not covering at least a portion of a lower surface of each of the plurality of package lower pads (Id.; 110b); and wherein the plurality of first chip support structures extend into the upper solder resist layer, and do not penetrate through the upper solder resist layer (Fig. 7A of Wu; 50A”. Fig. 2D of Noguchi; O110a. It is considered obvious that one of ordinary skill in the art would form the openings such that they extend into but do not penetrate the solder resist layer 110a of Noguchi in order to improve bonding between the package substrate and chip support structures while avoiding unnecessary exposure of the underlying electrical structure/connections.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Wu and Noguchi, such that solder resist layers are formed along the lower and upper surfaces of the package base insulating layer in order to better control connections between the overall package substrate and external components by properly separating adjacent connections and preventing undue interference.
Claim(s) 17, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. in further view of Jo (PGPub No. 20160093598).
Regarding claim 17, Jo teaches wherein the first chip conductive pillar, the second chip conductive pillar, the first chip support structure, and the second chip support structure include a same material (Fig. 1; 116a, 116b). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Wu et al. and Jo, such that the first chip conductive pillar, the second chip conductive pillar, the first chip support structure, and the second chip support structure include a same material in order to create layers of uniform material between the package substrate and each chip which in turn would simplify the manufacturing process and/or reduce costs.
Regarding claim 19, Wu teaches wherein each of the plurality of first chip connection terminals includes a first chip conductive pillar and a first chip conductive cap covering a lower surface of the first chip conductive pillar (Figs. 7A-7B; 22A”, 23A”), and each of the plurality of second chip connection terminals includes a second chip conductive pillar and a second chip conductive cap covering a lower surface of the second chip conductive pillar (Id.; 22B-D”, 23B-D”).
Wu fails to teach each of the first chip conductive pillar, the second chip conductive pillar, the first chip support structure, and the second chip support structure includes a metal.
Jo teaches each of the first chip conductive pillar, the second chip conductive pillar, the first chip support structure, and the second chip support structure includes a metal (Fig. 1; second connection ports 116a and 116b. In light of [0066-67] and [0069], which point to both the external and first connection ports comprising bumps or solder balls, it is considered obvious that one of ordinary skill in the art would form the connection ports 116a and 116b of the same material.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Wu et al. and Jo, such that the first chip conductive pillar, the second chip conductive pillar, the first chip support structure, and the second chip support structure include a same material in order to create layers of uniform material between the package substrate and each chip which in turn would simplify the manufacturing process and/or reduce costs.
Regarding claim 20, Wu teaches wherein a horizontal width of each of the first chip conductive pillar and the second chip conductive pillar is between about 15 μm and about 40 μm (One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized the width of each of the first chip and second chip conductive pillars to be a result effective variable. Thus, it would have been obvious to modify the device of Wu to have the horizontal widths of each conductive pillar within the claimed range in order to create stable electrical pathways according to the critical dimensions of the overall structure, and since optimum or workable ranges of such variables are discoverable through routine experimentation. See MPEP 2144.05(II)(B) and 2143. Furthermore, it has also been held that the applicant must show that a particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936, (Fed. Cir. 1990). Note that the law is replete with cases in which when the mere difference between the claimed invention and the prior art is some dimensional limitation or other variable within the claims, patentability cannot be found. The instant disclosure does not set forth evidence ascribing unexpected results due to the claimed dimensions. See Gardner v. TEC Systems, Inc., 725 F.2d 1338 (Fed. Cir. 1984), which held that the dimensional limitations failed to point out a feature which performed and operated any differently from the prior art.), and a horizontal width of the first chip support structure is about 5% to about 20% greater than the horizontal width of the first chip conductive pillar, and a horizontal width of the second chip support structure is about 5 % to about 20 % greater than the horizontal width of the second chip conductive pillar (One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized the horizontal widths of each of the first and second chip support structures to be a result effective variable. Thus, it would have been obvious to modify the device of Wu to have the horizontal widths within the claimed range in order to better balance physical stability with electrical conductivity, and since optimum or workable ranges of such variables are discoverable through routine experimentation. See MPEP 2144.05(II)(B) and 2143. Furthermore, it has also been held that the applicant must show that a particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936, (Fed. Cir. 1990). Note that the law is replete with cases in which when the mere difference between the claimed invention and the prior art is some dimensional limitation or other variable within the claims, patentability cannot be found. The instant disclosure does not set forth evidence ascribing unexpected results due to the claimed dimensions. See Gardner v. TEC Systems, Inc., 725 F.2d 1338 (Fed. Cir. 1984), which held that the dimensional limitations failed to point out a feature which performed and operated any differently from the prior art.).
Conclusion
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/PATRICK CULLEN/Assistant Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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