DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 07/23/2024 and 07/08/2025 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4 and 6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kobayashi (WO Pub No WO2014102979A1). (see attached translation for [line] citations)
Regarding claim 1, Koyabashi teaches a semiconductor device (Q) fig. 1 [line 239-245], comprising:
a semiconductor substrate (EP with 1) fig. 1 [lines 247-262] (n-type / p-type SiC semiconductor);
an electrode (10) fig. 1 [lines 297-301], at least a part of which protrudes (EPP) [see annotated fig. 1 below] to an upper side (upper side of 11) (vertically away) from a reference surface (RS; top of EP comprising top of 4 and 5 [lines 295-262] used as reference level) [see annotated fig. 1 below] of the semiconductor substrate (EP with 1); and
an insulating film (12) fig. 1 [lines 292-295, lines 303-305] (silicon oxide) covering the reference surface (RS) of the semiconductor substrate (EP with 1) and the electrode (10), wherein the insulating film (12) includes a first upper surface (US1) [see annotated fig. 1 below] and a protrusion part (PP) [see annotated fig. 1 below] protruding (horizontally away) from the first upper surface (US1) corresponding to (vertically corresponding to / overlapping with) the reference surface (RS) of the semiconductor substrate (EP with 1) and the at least the part (EPP) of the electrode (10) protruding (vertically away) from the reference surface (RS), respectively, and
h1/h2, which is a ratio of h1 as a distance from the reference surface (RS) of the semiconductor substrate to a connection part (CP) (portion of CP defined at level below) connecting (partially connecting) the first upper surface (US1) of the insulating film (12) and a surface of the protrusion part (PP) to h2 as a distance from the reference surface (RS) of the semiconductor substrate (EP with 1) to a second upper surface (top of 10) of the electrode (10), is equal to 1 and smaller than 1.5 (equal to 1, based on distances H1, H2 defined at co-planar points of CP and top of 10 to RS, as defined in fig. 1 below).
[AltContent: ][AltContent: ][AltContent: arrow][AltContent: connector][AltContent: arrow][AltContent: textbox (H2v)][AltContent: textbox (H1v)][AltContent: connector][AltContent: textbox (H1, H2 both defined at this level to RS)][AltContent: arrow][AltContent: connector][AltContent: arrow][AltContent: arrow][AltContent: textbox (EPP)][AltContent: textbox (PP)][AltContent: textbox (CP)][AltContent: arrow][AltContent: arrow][AltContent: rect][AltContent: textbox (US1)][AltContent: textbox (RS)][AltContent: rect][AltContent: arrow]
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Annotated fig. 1 of Koyabashi
Regarding claim 2, Koyabashi teaches the semiconductor device (Q) fig. 1 [line 239-245] according to claim 1. Koyabashi also teaches wherein the electrode (10) fig. 1 [lines 297-301] is wholly disposed on (supported by) an upper side of the reference surface (RS) [see annotated fig. 1 above] of the semiconductor substrate (EP with 1) fig. 1 [lines 247-262].
Regarding claim 3, Koyabashi teaches the semiconductor device (Q) fig. 1 [line 239-245] according to claim 1. Koyabashi also teaches wherein the electrode includes:
a first electrode part (left half of EPP) [see annotated fig. 1 above] protruding (vertically away) from the reference surface (RS) [see annotated fig. 1 above] of the semiconductor substrate (EP with 1) fig. 1 [lines 247-262]; and
a second electrode part (right half of EPP) [see annotated fig. 1 above] provided in a trench (trench in 7 and 11, hosting 10) fig. 1 [lines 292-299] provided to (reaching to) the reference surface (RS) [see annotated fig. 1 above] of the semiconductor substrate (EP with 1) fig. 1 [lines 247-262].
Regarding claim 4, Koyabashi teaches the semiconductor device (Q) fig. 1 [line 239-245] according to claim 1. Koyabashi also teaches wherein a ratio of an angle between the reference surface (RS) [see annotated fig. 1 above] of the semiconductor substrate (EP with 1) fig. 1 [lines 247-262] and a second side surface (sidewall of 12 bordering 10) of a lower part of the insulating film (12) fig. 1 [lines 292-295, lines 303-305] (silicon oxide) on (supported by) a lower side of the first upper surface (US1) to an angle between the reference surface (RS) [see annotated fig. 1 above] of the semiconductor substrate (EP with 1) fig. 1 [lines 247-262] and a first side surface (right sidewall) of the protrusion part (PP) [see annotated fig. 1 above] of the insulating film (12) is equal to one (both sidewall of 12 bordering 10 and right sidewall of PP as defined in annotated fig. 1 above are oriented substantially vertically such that they both form an approximately right / 90-degree angle with the horizontal reference surface RS, thus, ratio of angles approximately equal to 1).
Regarding claim 6, Koyabashi teaches the semiconductor device (Q) fig. 1 [line 239-245] according to claim 1. Koyabashi also teaches wherein a material (SiC) [lines 247-250] of the semiconductor device (Q) includes wide bandgap semiconductor (SiC) [lines 247-250] (SiC is a wide bandgap semiconductor because SiC is widely-known to have a wide bandgap relative to silicon).
As further evidence that SiC is considered a wide bandgap material relative to silicon in the art, see [0004] of Kobayashi-II (U.S. PG Pub No US2020/0083369A1), which discloses that [0004 Koyabashi-II] “… a wide bandgap semiconductor material (semiconductor material having a bandgap wider than that of silicon, e.g., silicon carbide (SiC)) …”. Moreover, [0011] of the instant application refers to “silicon carbide (SiC) as wide bandgap semiconductor”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi (WO Pub No WO2014102979A1), as applied in claim 1 above, in view of Zundel (U.S. PG Pub No US2017/0170286A1).
Regarding claim 5, Koyabashi teaches the semiconductor device (Q) fig. 1 [line 239-245] according to claim 1. However, Koyabashi does not explicitly disclose wherein an outer edge of the protrusion part (PP of 12) [see annotated fig. 1 above] includes a curved part in a cross section, and a connection part between a straight part and the curved part in a cross section of an upper surface of the protrusion part (PP) is located immediately above an end portion of the electrode (10) fig. 1 [lines 297-299] or immediately above an outer side of the end portion.
Zundel teaches a semiconductor device (300) fig. 3A [0109] wherein an outer edge of the protrusion part (PP of insulating material [0045-0046, 0107], not explicitly labeled) [see annotated fig. 3A below] includes a curved part (see below) in a cross section, and a connection part (see below) between a straight part (see below) and the curved part (see below) in a cross section of an upper surface of the protrusion part (PP) is located immediately above (directly overlaps) an end portion (top) of the electrode (104, S) fig. 3A [0111].
[AltContent: textbox (Line indicating overlap )][AltContent: arrow][AltContent: connector][AltContent: arrow][AltContent: arrow][AltContent: textbox (PP = insulating layer in this area )][AltContent: arrow][AltContent: arrow][AltContent: textbox (Straight Part)][AltContent: textbox (Connecting Part)][AltContent: textbox (Curved part )][AltContent: oval][AltContent: rect][AltContent: oval][AltContent: oval]
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Annotated fig. 3A of Zundel
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the semiconductor device of Koyabashi such that the protruding insulating material above the electrodes is curved [0041-0046, 0107] in order to carefully control/alter the degree of electrical insulation [0041-0042] provided by the insulating material relative to other adjacent components according to the geometry of the trench insulating layer [0041-0045, 0107, 0111], as taught by Zundel.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi (WO Pub No WO2014102979A1), as applied in claim 1 above, in view of Kagawa (U.S. PG Pub No US2019/0259872A1).
Regarding claim 7, Koyabashi does not explicitly disclose a main conversion circuit including the semiconductor device semiconductor device (Q) fig. 1 [line 239-245] according to claim 1, converting electrical power which has been input, and outputting the electrical power; and
a control circuit outputting a control signal for controlling the main conversion circuit to the main conversion circuit.
Kagawa teaches a main conversion circuit (601) fig. 16 [0080] including the semiconductor device semiconductor device (600) fig. 16 [0080] according to claim 1, converting electrical power (DC input [0080]) which has been input, and outputting (AC output [0080]) the electrical power; and
a control circuit (comprising 602 with 603) fig. 16 [0080] outputting a control signal [0080] for controlling (controlling and driving [0080]) the main conversion circuit (601) to the main conversion circuit (601).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the semiconductor device of Koyabashi to include the power conversion and control circuitry [0080] of Kagawa in order to desirably convert the power type and levels [0079-0085] of the semiconductor device to enhance the utility of the semiconductor device for a variety of application contexts [0081], as taught by Kagawa.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Remaining references made available on the PTO-892 form are each considered relevant to the present disclosure because they all feature wide bandgap semiconductor devices with protruding layers above trench electrodes.
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/SEAN AYERS WINTERS/Examiner, Art Unit 2892 07/23/2026
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