DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
However, should applicant desire to obtain the benefit of foreign priority under 35
U.S.C. 119(a)-(d) prior to declaration of an interference, a certified English translation of
the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and
41.202(e).
Failure to provide a certified translation may result in no benefit being accorded
for the non-English application.
Information Disclosure Statement
The information disclosure statement (IDS) filed on January 10, 2025 is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is a possible suggestion: Storage Device with Connecting Plug Electrode in Contact with a Top and Side Surface of a Source or Drain Electrode.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-13 are rejected under 35 U.S.C. 103 as being unpatentable over Yakubo et al., WIPO WO2020/234689 A1 (hereinafter referred to as Yakubo; both a machine translation of the WIPO published application as well as the US PGPub of the national stage published application have been provided).
Regarding Claim 1, Yakubo discloses a storage device comprising:
a first insulator (FIG. 41C, insulator 214),
a second insulator over the first insulator (FIG. 41C, insulator 280),
and a memory cell comprising a first transistor and a first capacitor (FIG. 41C, transistors 200M and capacitors 292B taken together comprise a memory cell),
wherein the first transistor comprises: an oxide over the first insulator (FIG. 41C, oxide 230 over insulator 214);
a first conductor and a second conductor over the oxide (FIG. 41C, conductor 242b, conductor 242a);
a third insulator over the oxide (FIG. 41C, insulator 250);
And a third conductor over the third insulator (FIG. 41C, conductor 260),
wherein the second insulator is over the first conductor and the second conductor (FIG. 41C, insulator 280),
wherein the second insulator comprises a first opening comprising a region overlapping with the oxide and a second opening comprising a region overlapping with the second conductor (FIG. 41C, insulator 280 with first opening overlapping with oxide 230 and second opening overlapping with conductor 242a),
wherein the third insulator and the third conductor are located in the first opening (FIG. 41C, insulator 250 and conductor 260 in first opening overlapping with oxide 230),
wherein the first capacitor comprises a fourth conductor in contact with a top surface of the second conductor (FIG. 41C, capacitor 292B, conductor 276, conductor 242a),
a fourth insulator over the fourth conductor (FIG. 41C, insulator 277),
and a fifth conductor over the fourth insulator (FIG. 41C, conductor 278),
wherein the fourth conductor, the fourth insulator and the fifth conductor are located in the second opening (FIG. 41C, conductor 276, insulator 277, conductor 278 of capacitor 292B are in the second opening overlapping with conductor 242a),
wherein a third opening is located in the first insulator, the second insulator, and the first conductor (FIG. 41C, opening in insulator 214, insulator 280, and conductor 242b),
wherein a sixth conductor is located in the third opening (FIG. 41C, conductor 424),
Yakubo does not explicitly show in the disclosed drawings that and wherein the sixth conductor is in contact with a top surface and a side surface of the first conductor. However, FIG. 41C merely discloses a potential modification wherein insulator 241 is provided on a side surface of 424--e.g., [0268] ““in the case where the insulator 241 is provided on the side surface of the conductor 424,” and provides an example modification of the memory cell for such (see, e.g., FIGs. 44A-44C). One of ordinary skill in the art would recognize that there then exists, therefore, a case wherein the insulator 241 is not provided on the side surface of the conductor 424, and so the conductor 424 would be in contact with a top surface and a side surface of conductor 242b. Indeed, one of ordinary skill would recognize that while such an insulator film might be beneficial, the case where it is not present and so conductor 424 and conductor 242b are in contact allows for a simpler manufacturing process (i.e., no need for an extraneous layer) as well as increased contact between the conductor 242b and conductor 424, which would be beneficial for reducing leakage current and contact resistance.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the teaching of Yakubo of the case with no insulator 241 on the side surface of conductor 424 so that and wherein the sixth conductor is in contact with a top surface and a side surface of the first conductor (FIG. 41C, conductor 424 in contact with a top and side surface of conductor 242b; [0268]) for the benefit of simplified manufacturability of the desired structure and increasing contact between the two conductors.
Regarding Claim 8, Yakubo discloses the storage device according to claim 1 as discussed above.
Yakubo further discloses wherein a part of the fourth conductor, a part of the fourth insulator and a part of the fifth conductor are located above a top surface of the third conductor (FIG. 41C, conductor 276, insulator 277, and conductor 278 have upper portions located above a top surface of conductor 260).
Regarding Claim 9, Yakubo discloses the storage device according to claim 8 as discussed above.
Yakubo further discloses wherein the third insulator is in contact with a top surface and a side surface of the oxide and a sidewall of the first opening in the second insulator (FIG. 41C, insulator 250 in contact with top and side surfaces of oxide 230 (oxide 230a, 230b, 230c); [0215] “although not shown, the conductor 260 that functions as a gate in the channel width direction has a structure in which the side surfaces and the upper surface of the oxide 230b in the channel forming region are covered with the oxide 230c and the insulator 250, whereby the conductor 260 is formed”).
Regarding Claim 10, Yakubo discloses the storage device according to claim 8 as discussed above.
Yakubo further discloses wherein each of the first conductor and the second conductor is in contact with a top surface and a side surface of the oxide (FIG. 41C, conductors 242b, 242a in contact with a top surface of oxide 230; [0284] teaches that the “oxide 243 is not necessarily provided” in which case, conductors 242b, 242a are in contact with a top surface and side surface of oxide 230); [0254]).
Regarding Claim 11, Yakubo discloses the storage device according to claim 8 as discussed above.
Yakubo further discloses wherein the fourth conductor is in contact with a sidewall of the second opening in the second insulator (FIG. 41C, conductor 276 in contact with a sidewall of opening in insulator 280).
Regarding Claim 12, Yakubo discloses the storage device according to claim 8, as discussed above.
Yakubo further discloses wherein in the third opening, the side surface of the first conductor protrudes from a side surface of the first insulator and a side surface of the second insulator (FIG. 41C, the side surface of conductor 242b protrudes farther than, i.e., from, a side surface of insulator 214, insulator 280).
Regarding Claim 13, Yakubo discloses the storage device according to claim 8 as discussed above.
Yakubo further discloses further comprising a seventh conductor between the sixth conductor and the third opening (FIG. 41C, conductor 424 clearly shows two layers to 424, although Yakubo does not explicitly label such in this figure),
Yakubo does not explicitly disclose wherein the sixth conductor comprises tungsten, and wherein the seventh conductor comprises titanium and nitrogen. However, Yakubo does disclose explicit possible material compositions of similar conductors, used for the same purposes, and further uses such language in the disclosure as “materials that can be used for conductors 205, 242, 260, 424, etc., can be used,” which one of ordinary skill would reasonably understand to mean that the material composition disclosed for one of the conductors can readily be applied to another ([0184-0185, 0251, 0266]. (FIGs. 40A, 41C, conductor 240 and conductor 424; [0184] a similar plug (e.g., conductor 240 which functions as a plug and connector) uses tungsten).
Therefore, one of ordinary skill in the art before the effective filing date of the claimed invention would have used the disclosed conductor material teachings of Yakubo and modified the structure of conductor 424 to be of a laminated structure, wherein the sixth conductor comprises tungsten, and wherein the seventh conductor comprises titanium and nitrogen (FIG. 41C, conductor 424; [0185, 0237, 0251, 0266]) with a laminate of titanium nitride and tungsten, as such would be beneficial for increased oxidation resistance.
Regarding Claim 2, Yakubo discloses a storage device comprising:
a plurality of layers each comprising a first insulator (FIGs. 39, 41C, plurality of memory device layers 415_1 to 415_n, insulator 214),
a second insulator over the first insulator (FIGs. 39, 41C, insulator 280),
and a memory cell comprising a first transistor and a first capacitor (FIGs. 39, 41C, transistors 200M and capacitors 292B taken together comprise a memory cell, memory device 420B),
wherein the plurality of layers are stacked (FIG. 39, memory device layers 415_1 to 415_n are stacked vertically),
wherein the first transistor comprises: an oxide over the first insulator (FIGs. 39, 41C, oxide 230 over insulator 214),
a first conductor and a second conductor over the oxide (FIGs. 39, 41C, conductor 242b, conductor 242a);
a third insulator over the oxide (FIGs. 39, 41C, insulator 250);
And a third conductor over the third insulator (FIGs. 39, 41C conductor 260),
wherein the second insulator is over the first conductor and the second conductor (FIGs. 39, 41C, insulator 280 over conductors 242b, 242a),
wherein the second insulator comprises a first opening comprising a region overlapping with the oxide and a second opening comprising a region overlapping with the second conductor (FIGs. 39, 41C, insulator 280 with first opening overlapping with oxide 230 and second opening overlapping with conductor 242a),
wherein the third insulator and the third conductor are located in the first opening (FIGs. 39, 41C, insulator 250 and conductor 260 in first opening overlapping with oxide 230),
wherein a third opening is provided in the plurality of layers (FIGs. 39, 41C, opening in insulator 214, insulator 280, and conductor 242b seen through all memory device layers 415_1 to 415_n),
wherein each part of the third opening in the plurality of layers overlaps with the other parts (FIGs. 39, 41C, all openings in insulator 214, insulator 280, conductor 242b overlap through device layers 415_1 to 415_n),
wherein a sixth conductor is located in the third opening (FIGs. 39, 41C, conductor 424).
Yakubo further discloses a modification of the capacitor structure of FIG. 39 in FIG. 41C, i.e., capacitor 292B of memory device 420B (as compared to capacitor 292 of memory device 420 in FIG. 39) that is located in the opening in insulator 280 overlapping with 242a and so has a U-shaped profile, rather than the overlapping metal-insulator-metal profile of capacitor 292 and “the capacitance 292B is preferable because it is greater than the capacitance obtained by the area where the conductors 276 and 278 overlap,” i.e., in capacitor 292.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the modification detailed in FIG. 41C of a capacitor 292B over the capacitor 292 shown in FIG. 39 for the benefit of increased capacitance, such that
wherein the first capacitor comprises a fourth conductor in contact with a top surface of the second conductor (FIGs. 39, 41C, capacitor 292B, conductor 276, conductor 242a),
a fourth insulator over the fourth conductor (FIGs. 39, 41C, insulator 277),
and a fifth conductor over the fourth insulator (FIGs. 39, 41C, conductor 278),
wherein the fourth conductor, the fourth insulator, and the fifth conductor are located in the second opening (FIGs. 39, 41C, conductor 276, insulator 277, conductor 278 of capacitor 292B are in the second opening overlapping with conductor 242a).
Yakubo does not explicitly disclose and wherein, in each of the plurality of layers, the sixth conductor is in contact with a top surface of and a side surface of the first conductor. However, as discussed above with regards to Claim 1, FIG. 41C merely discloses a potential modification wherein insulator 241 is provided on a side surface of 424 ([0268]). One of ordinary skill in the art would recognize that there then exists a case wherein the insulator 241 is not provided on the side surface of the conductor 424, and so the conductor 424 would be in contact with a top surface and a side surface of conductor 242b. Indeed, one of ordinary skill would recognize that while such an insulator film might be beneficial, the case where it is not present and so conductor 424 and conductor 242b are in contact allows for a simpler manufacturing process (i.e., no need for an extraneous layer) as well as increased contact between the conductor 242b and conductor 424, which would be beneficial for reducing leakage current and contact resistance.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the teaching of Yakubo of the case without insulator 241 on the side surface of conductor 424 so that and wherein, in each of the plurality of layers, the sixth conductor is in contact with a top surface of and a side surface of the first conductor. (FIGs. 39, 41C, conductor 424 in contact with a top and side surface of conductor 242b; [0268]) for the benefit of simplified manufacturability of the desired structure and increasing contact between the two conductors.
Regarding Claim 3, Yakubo discloses the storage device according to claim 2 as discussed above.
Yakubo further discloses wherein each of the plurality of layers further comprises a second transistor and a second capacitor, wherein the first transistor and the second transistor are line-symmetric with respect to the sixth conductor as a symmetric axis, wherein the first transistor and the second transistor have a same structure, wherein the first capacitor and the second capacitor are line-symmetric with respect to the sixth conductor as a symmetric axis, and wherein the first capacitor and the second capacitor have a same structure (FIGs. 39, 41C, transistor 200M and capacitor 292B, “symmetrically arranged with the conductor 424 sandwiched between them” [0267]).
Regarding Claim 4, Yakubo discloses a storage device comprising:
a layer comprising a first insulator (FIGs. 39, 41C, memory device layer 415_1, insulator 214),
a second insulator over the first insulator (FIGs. 39, 41C, insulator 280),
and a memory cell comprising a first transistor and a first capacitor (FIGs. 39, 41C, transistors 200M and capacitors 292B taken together comprise a memory cell, memory device 420B);
a substrate provided with a driver circuit configured to drive the memory cell (FIGs. 39, 41C, semiconductor substrate 311, element layer 411 with transistor 300 which can “function as a circuit of a semiconductor device … [including] … driver circuits ….” [0143]);
a functional layer comprising a functional circuit, the functional layer over the driver circuit (FIGs. 39, 41C, transistor layer 413 with transistor 200T which “can function as a circuit for controlling each memory unit 470” and which is over element layer 411, [0144]);
and a wiring (FIGs. 39, 41C, conductor 426),
wherein the layer is over the functional layer (FIGs. 39, 41C, memory device layers 415_1 stacked vertically above transistor layer 413),
wherein the first transistor comprises: an oxide over the first insulator (FIGs. 39, 41C, oxide 230 over insulator 214);
a first conductor and a second conductor over the oxide (FIGs. 39, 41C, conductor 242b, conductor 242a);
a third insulator over the oxide (FIGs. 39, 41C, insulator 250);
and a third conductor over the third insulator (FIGs. 39, 41C, conductor 260),
wherein the second insulator is located over the first conductor and the second conductor (FIGs. 39, 41C, insulator 280 over conductors 242b, 242a),
wherein the second insulator comprises a first opening comprising a region overlapping with the oxide and a second opening comprising a region overlapping with the second conductor (FIGs. 39, 41C, insulator 280 with first opening overlapping with oxide 230 and second opening overlapping with conductor 242a),
wherein the third insulator and the third conductor are located in the first opening (FIGs. 39, 41C, insulator 250 and conductor 260 in first opening overlapping with oxide 230),
wherein the layer comprises a third opening (FIGs. 39, 41C, memory device layer 415_1 with an opening in insulator 214, insulator 280, and conductor 242b),
wherein a sixth conductor is located in the third opening (FIG. 41C, conductor 424),
wherein the driver circuit is electrically connected to the functional circuit via the wiring (FIG. 39, element layer 411 with transistor 300 connected to conductor 426; [0143, 0147]),
wherein the functional circuit further comprises a second transistor (FIG. 39, transistor layer 413_1 comprising transistor 200T which “can function as a circuit for controlling each memory unit 470”; [0144]),
wherein a gate of the second transistor is electrically connected to the sixth conductor (FIG. 39, transistor layer 413_1, transistor 200T, wherein the gate is electrically connected to conductor 424; [0144, 0147]),
wherein the functional circuit is configured to transmit a signal to the wiring, and wherein the signal corresponds to a potential of the sixth conductor (FIG. 39, conductor 426, transistor 200T, conductor 428, transistor layer 413_1; “it is preferable that the conductor 426 is electrically connected to the transistor 200T via a conductor 428 which is electrically connected to any one of the source, drain and gate of the transistor 200T” [0147], i.e., a signal from the gate of transistor 200T, i.e., a signal or potential (voltage) from conductor 424).
Yakubo further discloses a modification of the capacitor structure of FIG. 39 in FIG. 41C, i.e., capacitor 292B of memory device 420B (as compared to capacitor 292 of memory device 420 in FIG. 39). The capacitor 292B is located in the opening in insulator 280 overlapping with 242a and so has a U-shaped profile, rather than the overlapping metal-insulator-metal profile of capacitor 292, where “the capacitance 292B is preferable because it is greater than the capacitance obtained by the area where the conductors 276 and 278 overlap,” i.e., in capacitor 292.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the modification detailed in FIG. 41C of a capacitor 292B over the capacitor 292 shown in FIG. 39 for the benefit of increased capacitance, such that
wherein the first capacitor comprises a fourth conductor in contact with a top surface of the second conductor (FIGs. 39, 41C, capacitor 292B, conductor 276, conductor 242a),
a fourth insulator over the fourth conductor (FIGs. 39, 41C, insulator 277),
and a fifth conductor over the fourth insulator (FIGs. 39, 41C, conductor 278),
wherein the fourth conductor, the fourth insulator, and the fifth conductor are located in the second opening (FIGs. 39, 41C, conductor 276, insulator 277, conductor 278 of capacitor 292B are in the second opening overlapping with conductor 242a).
Yakubo does not explicitly disclose and wherein the sixth conductor is in contact with a top surface of and a side surface of the first conductor.
However, FIG. 41C merely discloses a potential modification wherein insulator 241 is provided on a side surface of 424 ([0268]). One of ordinary skill in the art would recognize that there then exists a case wherein the insulator 241 is not provided on the side surface of the conductor 424, and so the conductor 424 would be in contact with a top surface and a side surface of conductor 242b. Indeed, one of ordinary skill would recognize that while such an insulator film might be beneficial, the case where it is not present and so conductor 424 and conductor 242b are in contact allows for a simpler manufacturing process (i.e., no need for an extraneous layer) as well as increased contact between the conductor 242b and conductor 424, which would be beneficial for reducing leakage current and contact resistance.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the teaching of Yakubo of the case without insulator 241 on the side surface of conductor 424 such that
and wherein, in each of the plurality of layers, the sixth conductor is in contact with a top surface of and a side surface of the first conductor. (FIGs. 39, 41C, conductor 424 in contact with a top and side surface of conductor 242b; [0268]) for the benefit of simplified manufacturability of the desired structure and increasing contact between the two conductors.
Regarding Claim 5, Yakubo discloses the storage device according to claim 4 as discussed above.
Yakubo further discloses wherein the layer further comprises a third transistor and a second capacitor, wherein the first transistor and the third transistor are line-symmetric with respect to the sixth conductor as a symmetric axis, wherein the first transistor and the third transistor have a same structure, wherein the first capacitor and the second capacitor are line-symmetric with respect to the sixth conductor as a symmetric axis, and wherein the first capacitor and the second capacitor have a same structure (FIGs. 39, 41C, transistor 200M and capacitor 292B, “symmetrically arranged with the conductor 424 sandwiched between them” [0267]).
Regarding Claim 6, Yakubo discloses a storage device comprising:
a plurality of layers each comprising a first insulator (FIG. 39, 41C, memory device layers 415_1 to 415_n, insulator 214),
a second insulator over the first insulator (FIGs. 39, 41C, insulator 280 over insulator 214),
and a memory cell comprising a first transistor and a first capacitor (FIGs. 39, 41C, transistors 200M and capacitors 292B taken together comprise a memory cell, memory device 420B);
a substrate provided with a driver circuit configured to drive the memory cell (FIG. 39, semiconductor substrate 311, element layer 411 with transistor 300 which can “function as a circuit of a semiconductor device…[including]…driver circuits….” [0143]);
a functional layer comprising a functional circuit, the functional layer over the driver circuit (FIG. 39, transistor layer 413 with transistor 200T which “can function as a circuit for controlling each memory unit 470” and which is over element layer 411; [0144]);
and a wiring (FIG. 39, conductor 426),
wherein the plurality of layers are stacked over the functional layer (FIG. 39, memory device layers 415_1 to 415_n are stacked vertically),
wherein the first transistor comprises: an oxide over the first insulator (FIGs. 39, 41C, oxide 230 over insulator 214);
a first conductor and a second conductor over the oxide (FIGs. 39, 41C, conductor 242b, conductor 242a);
a third insulator over the oxide (FIGs. 39, 41C, insulator 250);
and a third conductor over the third insulator (FIGs. 39, 41C conductor 260),
wherein the second insulator is over the first conductor and the second conductor (FIGs. 39, 41C, insulator 280 over conductors 242b, 242a),
wherein the second insulator comprises a first opening comprising a region overlapping with the oxide and a second opening comprising a region overlapping with the second conductor (FIGs. 39, 41C, insulator 280 with first opening overlapping with oxide 230 and second opening overlapping with conductor 242a),
wherein the third insulator and the third conductor are located in the first opening (FIGs. 39, 41C, insulator 250 and conductor 260 in first opening overlapping with oxide 230),
wherein a third opening is provided in the plurality of layers (FIGs. 39, 41C, opening in insulator 214, insulator 280, and conductor 242b seen through all memory device layers 415_1 to 415_n),
wherein each part of the third opening in the plurality of layers overlaps with the other parts (FIGs. 39, 41C, all openings in insulator 214, insulator 280, conductor 242b overlap through device layers 415_1 to 415_n),
wherein a sixth conductor is located in the third opening (FIGs. 39, 41C, conductor 424),
wherein the sixth conductor is electrically connected to the memory cell (FIGs. 39, 41C, conductor 424 runs vertically through the entire memory unit 470 (e.g., through all stacked memory device layers); [0147]);
wherein the driver circuit is electrically connected to the functional circuit via the wiring (FIG. 39, element layer 411 with transistor 300 connected to conductor 426; [0143, 0147]),
wherein the functional circuit further comprises a second transistor (FIG. 39, transistor layer 413_1 comprising transistor 200T which “can function as a circuit for controlling each memory unit 470”; [0144]),
wherein a gate of the second transistor is electrically connected to the sixth conductor (FIG. 39, transistor layer 413_1, transistor 200T, wherein the gate is electrically connected to conductor 424; [0144, 0147]);
wherein the functional circuit is configured to transmit a signal to the wiring, and wherein the signal corresponds to a potential of the sixth conductor (FIG. 39, conductor 426, transistor 200T, conductor 428, transistor layer 413_1; “it is preferable that the conductor 426 is electrically connected to the transistor 200T via a conductor 428 which is electrically connected to any one of the source, drain and gate of the transistor 200T” [0147], i.e., a signal from the gate of transistor 200T, i.e., a signal or potential (voltage) from conductor 424).
Yakubo further discloses a modification of the capacitor structure of FIG. 39 in FIG. 41C, i.e., capacitor 292B of memory device 420B (as compared to capacitor 292 of memory device 420 in FIG. 39). The capacitor 292B is located in the opening in insulator 280 overlapping with 242a and so has a U-shaped profile, rather than the overlapping metal-insulator-metal profile of capacitor 292, where “the capacitance 292B is preferable because it is greater than the capacitance obtained by the area where the conductors 276 and 278 overlap,” i.e., in capacitor 292.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the modification detailed in FIG. 41C of a capacitor 292B over the capacitor 292 shown in FIG. 39 for the benefit of increased capacitance, such that
wherein the first capacitor comprises a fourth conductor in contact with a top surface of the second conductor (FIGs. 39, 41C, capacitor 292B, conductor 276, conductor 242a),
a fourth insulator over the fourth conductor (FIGs. 39, 41C, insulator 277),
and a fifth conductor over the fourth insulator (FIGs. 39, 41C, conductor 278),
wherein the fourth conductor, the fourth insulator, and the fifth conductor are located in the second opening (FIGs. 39, 41C, conductor 276, insulator 277, conductor 278 of capacitor 292B are in the second opening overlapping with conductor 242a).
Yakubo does not explicitly disclose wherein, in each of the plurality of layers, the sixth conductor is in contact with a top surface of and a side surface of the first conductor.
However, FIG. 41C merely discloses a potential modification wherein insulator 241 is provided on a side surface of 424 ([0268]). One of ordinary skill in the art would recognize that there then exists a case wherein the insulator 241 is not provided on the side surface of the conductor 424, and so the conductor 424 would be in contact with a top surface and a side surface of conductor 242b. Indeed, one of ordinary skill would recognize that while such an insulator film might be beneficial, the case where it is not present and so conductor 424 and conductor 242b are in contact allows for a simpler manufacturing process (i.e., no need for an extraneous layer) as well as increased contact between the conductor 242b and conductor 424, which would be beneficial for reducing leakage current and contact resistance.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the teaching of Yakubo of the case without insulator 241 on the side surface of conductor 424 so that
and wherein, in each of the plurality of layers, the sixth conductor is in contact with a top surface of and a side surface of the first conductor. (FIGs. 39, 41C, conductor 424 in contact with a top and side surface of conductor 242b; [0268]) for the benefit of simplified manufacturability of the desired structure and increasing contact between the two conductors.
Regarding Claim 7, Yakubo discloses the storage device according to claim 6 as discussed above.
Yakubo further discloses wherein each of the plurality of layers further comprises a third transistor and a second capacitor, wherein the first transistor and the third transistor are line-symmetric with respect to the sixth conductor as a symmetric axis, wherein the first transistor and the third transistor have a same structure, wherein the first capacitor and the second capacitor are line-symmetric with respect to the sixth conductor as a symmetric axis, and wherein the first capacitor and the second capacitor have a same structure (FIGs. 39, 41C, transistors 200M and capacitors 292B, “symmetrically arranged with the conductor 424 sandwiched between them” [0267]).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Yakubo as applied to Claim 8 above, and further in view of Miyairi, US PGPub 2015/0255490 A1 (hereinafter referred to as “Miyairi”).
Regarding Claim 14, Yakubo discloses the storage device according to claim 8 as discussed above.
Yakubo further discloses further comprising a fifth insulator in contact with a top surface of the second insulator and the top surface of the third conductor (FIG. 41C, insulator 282, insulator 275 in contact with a top surface of insulator 280 and top surface of 260),
wherein the second opening is further formed in the fifth insulator (FIG. 41C, second opening overlapping with conductor 242a, in insulator 282 and insulator 280),
and a part of the fourth insulator is in contact with a top surface of the fifth insulator (FIG. 41C, conductor 276, insulator 277, insulator 277 in contact with a top surface of insulator 282, 275).
Yakubo does not explicitly disclose and wherein each of a part of the fourth conductor is in contact with a top surface of the fifth insulator.
However, Miyairi, which is directed to a similar multi-tiered storage device with memory cells containing transistors and capacitors, does disclose a capacitor structure wherein the lower metal layer, electrode 181 of capacitor 150, is in contact with a top surface of a top insulator, insulating film 129, which would be beneficial for increased surface area (thus, increasing capacitance of the capacitor), and increased reliability from multiple contact points for the electrode 181/conductor 276 (Miyairi FIGs. 18B, 19B, electrode 181, capacitor 150, insulating film 129; [0315]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the storage device of Yakubo with the capacitor electrode teachings of Miyairi wherein and wherein each of a part of the fourth conductor and a part of the fourth insulator is in contact with a top surface of the fifth insulator (Yakubo FIG. 41C, conductor 276, insulator 277, insulator 277 in contact with a top surface of insulator 282, 275; Miyairi FIGs. 18B, 19B, electrode 181 of capacitor 150 in contact with a top surface of insulating film 129, [0315]) for increased reliability and capacitance benefits.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kurokawa et al., US PGPub 2023/0317176 A1, which is directed to a similar semiconductor device with a plurality of memory layers, a connecting plug or via electrode linking the layers together vertically and, much like Yakubo and the instant invention, teaching an increased contact between the source/drain electrodes and connecting plug electrode.
Yamazaki et al., US PGPub 2022/0278235 A1, which is directed to a similar semiconductor device with stacked memory layers, a similar transistor and capacitor design for individual memory cells with a symmetric layout arranged around a connecting plug electrode.
Onuki et al., US PGPub 2022/0238491 A1, which is directed to a semiconductor device with a stacked plurality of memory layers above a peripheral circuit and a driving circuit in a silicon substrate.
Atsumi et al., US PGPub 2015/0255139 A1, which is directed to a similar storage device of a plurality of memory device layers atop a peripheral circuit and with source/drain electrodes in contact with the top and side surfaces of the oxide semiconductor layer.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Austin T. Woodard whose telephone number is (571)270-1958. The examiner can normally be reached M-F, 8am to 5pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Austin T Woodard/Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
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