DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5 & 9-10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hisanori (US Pub no. 2013/0193496 A1).
Regarding claim 1, Hisanori et al discloses A vertical transistor (fig. 6)including a vertical gate electrode (1251)[0127]comprising: a first gate electrode layer(1192a) formed on a side wall and a bottom portion of a trench(114) and having a first impurity concentration[0128][0130]; and a second gate electrode layer (1191a)formed on the first gate electrode layer (1192a)and having a second impurity concentration different from the first impurity concentration[0130].
Regarding claim 2, Hisanori et al discloses wherein the second impurity concentration is lower than the first impurity concentration[0130].
Regarding claim 3, Hisanori et al discloses wherein the second gate electrode layer(1191a) is also formed inside the first gate electrode layer(1192a) in the
trench(114) fig. 6.
Regarding claim 4, Hisanori et al discloses wherein the first gate electrode layer(1192a) and the second gate electrode layer(1191a) are laminated in contact with each other[0128-0130].
Regarding claim 5, Hisanori et al discloses wherein the vertical transistor (1251)is a transfer transistor that transfers electric charge generated by a photodiode (108)to a floating diffusion[0142].
Regarding claim 9, Hisanori et al discloses A light detection apparatus (600) [0127]including a vertical transistor(1251) including a vertical gate electrode fig. 6 [0127]comprising: a first gate electrode layer(1192a) formed on a side wall and a bottom portion of a trench(114) and having a first impurity concentration[0128][0130]; and a second gate electrode layer(1191a) formed on the first gate electrode layer(1192a) and having a second impurity concentration different from the first impurity concentration[0130].
Regarding claim 10, Hisanori et al discloses An electronic device(2000) [0185][0188] including a light detection apparatus (600)including a vertical transistor (1251) including a vertical gate electrode comprising: a first gate electrode layer (1192a) formed on a side wall and a bottom portion of a trench(114) and having a first
impurity concentration[0128][0130]; and a second gate electrode layer (1191a) formed on the first gate electrode layer (1192a)and having a second impurity
concentration different from the first impurity concentration[0130].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s)6-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hisanori (US Pub no. 2013/0193496 A1) in view of Manda (US Pub no. 20100308385 A1).
Regarding claim 6, Hisanori et al discloses all the claim limitations of claim 1 but fails to teach wherein a planar transistor having a same conductivity type as the vertical transistor is formed on a same plane.
However, Manda et al discloses a planar transistor (22) having a same conductivity type as a vertical transistor(21) and formed on a same plane(fig. 4c)[0092-0094]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the invention of Hisanori et al with the teachings of Manda et al such that a planar transistor having a same conductivity type as the vertical transistor is formed on a same plane results because incorporating the planar transistor enhances the sensitivity of the device by increasing the area available for the photodiode.
Regarding claim 7, Hisanori et al discloses all the claim limitations of claim 1 but fails to teach wherein a planar transistor having a conductivity type different from the vertical transistor is formed on a same plane.
Manda et al discloses wherein a planar transistor (24)having a conductivity type different from the vertical transistor (21)is formed on a same plane fig. 4c[0092-0094]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Hisanori et al with the teachings of Manda et al such that a planar transistor having a conductivity type different from the vertical transistor is formed on a same plane results because applying the known planar transistor (PMOS) in the logic portion provides complimentary logic function and ensure peripheral operation of the device.
Regarding claim 8, Manda et al discloses wherein the planar transistor (22)includes a lower first gate electrode layer(15) and an upper second gate
electrode layer(16)[0092-0094] but fails to teach impurity concentrations of the first gate electrode layer and the second gate electrode layer of the planar transistor are same as the second gate electrode layer of the vertical gate electrode. Manda et al teaches that by controlling the thickness electrode layers 15 and 16 in the laminated structure of the planar NMOS transistor (22)and controlling the phosphorus concentration of the electrode layer 15, a desired doping concentration can be achieved [0105]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to adjust the impurity concentrations of the first gate electrode
layer and the second gate electrode layer of the planar transistor are same as the second gate electrode layer of the vertical gate electrode through routine experimentation to optimize device performance and conductivity characteristics. In re Antonie, 559 F.2d 618, 195 USPQ 6 (CCPA 1977)
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LATANYA N CRAWFORD EASON whose telephone number is (571)270-3208. The examiner can normally be reached Monday-Friday 8:30 AM-4:30 PM.
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/LATANYA N CRAWFORD EASON/Primary Examiner, Art Unit 2813
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