DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “33” has been used to designate both the first PTAT current and the second current in figure 3 (e.g., see paragraph 53 of the published application). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: “163” shown in figure 8. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The specification is objected to because of the following informalities:
The specification does not include reference character “163” shown in figure 8.
Appropriate correction is required.
Claim Objections
Claims 1, 8-10, 14-16, 23-25, and 28 are objected to because of the following informalities:
In claim 1, “,” should be deleted from lines 2, 5-7, and 9; and --temperature-dependent-- should be added after “first” in line 3.
In claims 8 and 10, “,” should be deleted from line 3.
In claim 9, “resistance, to allow” should be changed to --resistance to allow a-- in line 3.
In claim 14, “,” should be deleted from lines 2 and 5; and --a-- should be added before “variation” in the last line.
In claim 15, “,” should be deleted from lines 3, 5, and 7; and --a-- should be added before “variation” in line 8.
In claim 16, “,” should be deleted from line 2.
In claim 23, “claim 15” should be changed to --claim 16-- in line 1 (there is lack of antecedent basis in the claim for “the at least one thermal output signal” in line 2 and for “the output circuit” in lines 2-3); and “,” should be deleted from line 3. For examination purposes, claim 23 is considered to be dependent on claim 16.
In claim 24, “resistance, to allow” should be changed to --resistance to allow a-- in line 3.
In claim 25, “claim 15” should be changed to --claim 16-- in line 1 (there is lack of antecedent basis in the claim for “the at least one thermal output signal” in line 2 and for “the output circuit” in lines 2-3); and “,” should be deleted from line 3. For examination purposes, claim 23 is considered to be dependent on claim 16.
In claim 28, --from external-- should be changed to --externally from-- in line 3; “thermal sensor” should be changed to --one or more local thermal sensors-- in line 3 (it is not clear which one of the thermal sensors is being referred to by ‘the thermal sensor’); “providing” should be changed to --provide-- in line 4; and the last “and” should be deleted from line 3.
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1 and 7-11 of the instant application are rejected on the ground of nonstatutory double patenting as being unpatentable over respective claims 1 and 7-11 of U.S. Patent 11,619,551 [hereinafter ‘551].
Referring to claim 1 of the instant application, claim 1 of ‘551 claims a thermal sensor for an integrated circuit, comprising:
a Proportional To Absolute Temperature (PTAT) circuit comprising two series-connected n-type MOS transistors configured to receive a current source output (first) and to provide a first voltage;
a voltage generator circuit configured to provide a second voltage;
a reference voltage generation circuit configured to generate a reference voltage based on the first voltage and the second voltage; and
an output circuit configured to generate at least one thermal output signal based on the reference voltage together with the first voltage or (and/or) with the second voltage.
Claim 1 of ‘551 does not claim that the second voltage is a second temperature-dependent voltage.
However, claim1 claims that the device is a thermal sensor for generating a thermal output signal based on the reference voltage together with the first voltage or (and/or) with the second voltage.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify claim 1 of ‘551 by claiming that the second voltage is a second temperature-dependent voltage in order to allow the thermal sensor to generate a thermal output signal based on the reference voltage together with the first voltage or with the second voltage, as recited by claim 1 of ‘551.
Referring to claim 7 of the instant application, claim 7 of ‘551 claims a thermal sensor for an integrated circuit having all of the limitations of claim 7 of the instant application, as stated above with respect to claim 1 of the instant application, and further claims that the series-connected n-type MOS transistors of the PTAT circuit comprise a first n-type MOS transistor having a source connected to ground and a drain connected to a common point; and a second n-type MOS transistor having a source connected to the common point and a drain connected to a gate of the first n-type MOS transistor and to a gate of the second n-type MOS transistor, wherein the drain of the second n-type MOS transistor is further configured to receive the first current source output.
Referring to claim 8 of the instant application, claim 8 of ‘551 claims a thermal sensor for an integrated circuit having all of the limitations of claim 8 of the instant application, as stated above with respect to claim 1 of the instant application, and further claims that the at least one thermal output signal comprises a thermal trip signal and the output circuit comprises a thermal trip circuit configured to generate the thermal trip signal by comparing a threshold voltage with a sensed voltage that is based on the first voltage or (and/or) the second voltage, the threshold voltage being generated from the reference voltage and based on a configuration signal.
Referring to claim 9 of the instant application, claim 9 of ‘551 claims a thermal sensor for an integrated circuit having all of the limitations of claim 9 of the instant application, as stated above with respect to claim 8 of the instant application, and further claims a resistive divider, wherein the threshold voltage is generated by applying the reference voltage to the resistive divider, the resistive divider comprising a selectable resistance to allow selection of the threshold voltage, wherein the resistive divider outputs the threshold voltage.
Referring to claim 10 of the instant application, claim 10 of ‘551 claims a thermal sensor for an integrated circuit having all of the limitations of claim 10 of the instant application, as stated above with respect to claim 1 of the instant application, and further claims that the at least
one thermal output signal comprises a digital thermal signal and the output circuit comprises an
analog-to-digital convertor configured to convert a sensed voltage based on the first voltage
or (and/or) the second voltage to the digital thermal signal, the analog-to-digital convertor using the reference voltage to generate the digital thermal signal.
Referring to claim 11 of the instant application, claim 11 of ‘551 claims a thermal sensor for an integrated circuit having all of the limitations of claim 11 of the instant application, as stated above with respect to claim 10 of the instant application, and further claims that the analog-to-digital convertor comprises a sigma-delta modulator.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 14 and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Patent 8,072,259 to Isik (as evidenced by “A low-voltage CMOS Bandgap Reference” to Vittoz et al., IEEE Journal of Solid-State Circuits, Vol SC-14, No. 3, pages 573-579, June 1979) (IDS filed 10/21/24) [hereinafter Vittoz]).
Referring to claim 14, Isik discloses an integrated circuit (column 1, lines 8 and 14-15) comprising:
a power routing arrangement providing a power supply core voltage (VDD) to operate functional circuitry on the integrated circuit (figures 1-8, 10; column 5, lines 55-58; column 5, line 67-column 6, line 3; column 6, lines 64-67); and
one or more local thermal sensors located on the integrated circuit, each comprising a Proportional-To-Absolute Temperature (PTAT) circuit comprising MOS transistors (110) (figures 1-8, 10; column 1, lines 38-42) configured to use the power supply core voltage to generate at least one temperature-dependent voltage (PTAT0-PTAT4) (figure 8; column 12, lines 63-65) that varies independently of variation in the power supply core voltage (column 5, lines 29-50) (Isik states that an N-PTAT cell is as described in Vittoz, which states that the supply voltage Vo is independent on a supply current (and hence its corresponding voltage) (page 576, Section V, 1st and 2nd paragraphs); and paragraphs 65 and 66 of the instant specification, which describes such voltage of Vittoz as not being dependent on the power supply voltage).
Referring to claim 15, Isik discloses that each of the one or more local thermal sensors comprises a PTAT circuit (110) configured to use n-type MOS transistors to generate a first temperature-dependent voltage of the at least one temperature-dependent voltage (figures 1-5; column 1, lines 38-42; column 5, lines 30-33); a voltage generator circuit (120/220) configured to use a p-type MOS transistor to generate a second temperature-dependent voltage of the at least one temperature dependent voltage (figures 1-5; column 5, lines 59-61; column 6, lines 41-50); and a reference voltage generation circuit (130) configured to use the first and second temperature-dependent voltages to generate a reference voltage (OUT) that is independent of variation in temperature (figures 1-5; column 6, lines 4-10 (a bandgap voltage reference signal is mentioned as an output OUT); column 6, lines 53-57).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 7-9, 16, 23, 24, 28, 29, and 33 are rejected under 35 U.S.C. 103 as being unpatentable over Isik in view of Aota.
Referring to claim 1, Isik discloses a thermal sensor for an integrated circuit (column 1, lines 8 and 14-15) comprising:
a Proportional To Absolute Temperature (PTAT) circuit (110) comprising two series-connected n-type MOS transistors (figures 1-8, 10; column 1, lines 38-42; column 5, lines 30-34) configured to receive a first current source output (Vdd) and to provide a first voltage (figures 1-8, 10; column 1, lines 38-42) (PTAT0-PTAT4) (figure 8; column 12, lines 63-65);
a voltage generator circuit (120/220) configured to provide a second temperature-dependent voltage (figures 1-5; column 5, lines 59-61; column 6, lines 41-50); and
a reference voltage generation circuit (130) configured to generate a reference voltage (OUT) based on the first voltage and the second voltage (figures 1-5; column 6, lines 4-10, 53-57).
Isik does not disclose an output circuit configured to generate at least one thermal output signal based on the reference voltage together with the first voltage or with the second voltage.
However, Aota discloses an integrated circuit (figures 3, 4; paragraphs 60, 77-79) comprising an output circuit (C) configured to generate at least one thermal output signal (Tout) based on a reference voltage (Tvref) together with a first temperature-dependent voltage (Tvptat) (proportional to temperature) in order to protect the integrated circuit (e.g., from overheating) (paragraphs 78, 79).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Isik by providing an output circuit configured to generate at least one thermal output signal based on the reference voltage together with the first voltage (the reference voltage is based on the first voltage), as suggested by Aota, in order to protect the integrated circuit.
Referring to claim 7, Isik in view of Aota disclose a sensor having all of the limitations of claim 7, as stated above with resect to claim 1, wherein Isik discloses (figure 6; column 5, lines 40-47, 57-58; column 8, lines 3-11) that the series-connected n-type MOS transistors of the PTAT circuit comprise:
a first n-type MOS transistor (T4b) having a source connected to ground and a drain
connected to a common point (n1); and
a second n-type MOS transistor (T4a) having a source connected to the common point (n1) and a drain connected to a gate of the first n-type MOS transistor (T4b) and to a gate of the second n-type MOS transistor (T4a), wherein the drain of the second n-type MOS transistor (T4a) is further configured to receive the first current source output (from T23).
Referring to claim 8, Isik in view of Aota disclose a sensor having all of the limitations of claim 8, as stated above with respect to claim 1, wherein Aoya discloses (figures 4, 5; paragraphs 64, 66, 67, 78, 79) that the at least one thermal output signal (Tout) comprises a thermal trip signal (High/Low) and the output circuit comprises a thermal trip circuit (figure 5) configured to generate the thermal trip signal by comparing a threshold voltage (Tvref) with a sensed voltage that is based on the first voltage (Tvptat), the threshold voltage being generated from the reference voltage (Tvref) and based on a configuration signal (adjusted desired temperature T) (paragraph 78, 79).
Referring to claim 9, Isik in view of Aota disclose a sensor having all of the limitations of claim 9, as stated above with respect to claim 8, wherein Aoya discloses (figure 4) a resistive divider (R3, R4) (paragraph 80); wherein the threshold voltage (Tvref) being generated by applying the reference voltage to the resistive divider (R3, R4) (paragraph 80), the resistive divider (R3, R4) comprising a selectable resistance to allow a selection of the threshold voltage (paragraph 82), wherein the resistive divider outputs the threshold voltages (Tvref) (figure 4).
Referring to claim 16, Isik discloses a circuit having all of the limitations of claim 16, as stated above with respect to claim 15, except for an output circuit configured to generate at least one thermal output signal based on the reference voltage together with the first temperature-dependent voltage or with the second temperature-dependent voltage.
However, Aota discloses an integrated circuit (figures 3, 4; paragraphs 60, 77-79) comprising an output circuit (C) configured to generate at least one thermal output signal (Tout) based on a reference voltage (Tvref) together with a first temperature-dependent voltage (Tvptat) (proportional to temperature) in order to protect the integrated circuit (e.g., from overheating) (paragraphs 78, 79).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Isik by providing an output circuit configured to generate at least one thermal output signal based on the reference voltage together with the first temperature-dependent voltage, as suggested by Aota, in order to protect the integrated circuit.
Referring to claim 23, Isik in view of Aota disclose a circuit having all of the limitations of claim 23, as stated above with respect to claim 16, wherein Aoya discloses (figure 5; paragraphs 64, 66, 67, 78, 79) that the at least one thermal output signal (Tout) comprises a thermal trip signal (High/Low) and the output circuit comprises a thermal trip circuit (figure 5) configured to generate the thermal trip signal by comparing a threshold voltage (Tvref) with a sensed voltage that is based on the first temperature-dependent voltage (Tvptat), the threshold voltage being generated from the reference voltage (Tvref).
Referring to claim 24, Isik in view of Aota disclose a circuit having all of the limitations of claim 24, as stated above with respect to claim 23, wherein Aoya discloses (figure 4) the threshold voltage (Tvref) being generated by applying the reference voltage to a resistive divider (R3, R4) (paragraph 80), the resistive divider (R3, R4) comprising a selectable resistance to allow selection of the threshold voltage (paragraph 82).
Referring to claim 28, Isik in view of Aota disclose a circuit having all of the limitations of claim 28, as stated above with respect to claim 16, except for Isik disclosing an external voltage input configured to receive a voltage from external to the thermal sensor and provide a measurement voltage; and the output circuit being further configured to generate at least one voltage measurement output, the voltage measurement output being based on the measurement voltage and the reference voltage.
However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Isik in view of Aota by providing Isik with an external voltage input configured to receive a voltage from external to the thermal sensor and provide a measurement voltage and configuring the output circuit of Isik in view of Aota such that it generates at least one voltage measurement output that is based on the measurement voltage and the reference voltage in order to provide measurement voltages and generate measurement voltage outputs from additional thermal sensors at different locations in order to protect additional integrated circuits, which Aota suggests is desirable; and since it has been held that the mere duplication of the essential working parts of a device involves only routine skill in the art. See St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
Referring to claim 29, Isik discloses a method of operating a thermal sensor on an integrated circuit (column 1, lines 8 and 14-15), the method comprising:
obtaining a first temperature-dependent voltage (figures 1-8, 10; column 1, lines 38-42) (PTAT0-PTAT4) (figure 8; column 12, lines 63-65) using two series-connected n-type MOS transistors (figures 1-8, 10; column 1, lines 38-42; column 5, lines 30-34) receiving a first current source output (Vdd);
obtaining a second temperature-dependent voltage (figures 1-5; column 5, lines 59-61; column 6, lines 41-50); and
using the first temperature-dependent voltage and the second temperature-dependent voltage to generate a reference voltage (OUT) (figures 1-5; column 6, lines 4-10, 53-57).
Isik does not disclose generating at least one thermal output signal based on the reference voltage together with the first temperature-dependent voltage or with the second temperature-dependent voltage.
However, Aota discloses an integrated circuit (figures 3, 4; paragraphs 60, 77-79) comprising an output circuit (C) configured to generate at least one thermal output signal (Tout) based on a reference voltage (Tvref) together with a first temperature-dependent voltage (Tvptat) (proportional to temperature) in order to protect the integrated circuit (e.g., from overheating) (paragraphs 78, 79).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Isik by generating at least one thermal output signal based on the reference voltage together with the first temperature-dependent voltage (the reference voltage is based on the first voltage), as suggested by Aota, in order to protect the integrated circuit.
Referring to claim 33, Isik in view of Aota disclose a method having all of the limitations of claim33, as stated above with respect to claim 29, wherein Aoya discloses (figures 4, 5; paragraphs 64, 66, 67, 78, 79) that the step of generating the at least one thermal output signal (Tout) comprises generating a thermal trip signal (High/Low) by comparing a threshold voltage (Tvref) with a sensed voltage that is based on the first voltage (Tvptat), the threshold voltage being generated by applying the reference voltage to the resistive divider (R3, R4) (paragraph 80) having a selectable resistance (paragraph 82); and calibrating (adjusting) the thermal trip signal by setting the selectable resistance (paragraph 82).
Claims 10, 11, 25 and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Isik in view of Aota, as applied to corresponding claims 1 and 15 above, and further in view of view of “Architecture and Cells for Micropower Temperature Sensors” to Pablo Aguirre et al., Methodology Sensors, 1 January 2004 (IDS filed 10/21/24) [hereinafter Aguirre].
Referring to claim 10, Isik in view of Aota disclose a sensor having all of the limitations of claim 10, as stated above with respect to claim 1, except for Isik in view of Aota disclosing the at least one thermal output signal comprising a digital thermal signal and the output circuit comprises an analog-to-digital converter configured to convert a sensed voltage based on the first voltage to the digital thermal signal, the analog-to-digital converter using the reference voltage to generate the digital thermal signal.
However, Aguirre discloses an integrated circuit (page 2; figure 1; and the paragraphs above and below figure 1) having an output circuit comprising an analog-to-digital converter (A/D) configured to use a reference voltage (Vref) and a temperature-dependent voltage (Vptat) to generate a digital thermal signal (digital output) in order to simplify analog circuitry and allow low consumption (abstract).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Isik in view of Aota such that the at least one thermal output signal comprises a digital thermal signal and the output circuit comprises an analog-to-digital converter configured to convert a sensed voltage based on the first voltage to the digital thermal signal, the analog-to-digital converter using the reference voltage to generate the digital thermal signal, as suggested by Aguirre, in order to simplify analog circuitry and allow low consumption.
Referring to claim 11, Isik in view of Aota and Aguirre disclose a sensor having all of the limitations of claim 11, as stated above with respect to claim 10, except for Isik in view of Aota and Aguirre explicitly disclosing that the analog-to-digital converter comprises a sigma-delta modulator.
However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Isik in view of Aota and Aguirre by using a sigma-delta modulator as the analog-to-digital converter in order to provide a desired accuracy of the digital thermal signal while simplifying the analog circuitry and allowing low consumption, which Aguirre suggests is desirable; and since the use of the particular type of analog-to-digital converter claimed by the applicant is considered to be nothing more than a choice of engineering skill, choice, or design, because the use of the particular analog-to-digital converter claimed by the applicant is considered to be the use of numerous alternate types of analog-to-digital converters that a person having ordinary skill in the art before the effective filing date of the claimed invention would have been able to provide using routine experimentation in order to provide an analog-to-digital converter as already suggested by Aguirre.
Referring to claim 25, Isik in view of Aota disclose a circuit having all of the limitations of claim 25, as stated above with respect to claim 15, except for Isik in view of Aota disclosing the at least one thermal output signal comprising a digital thermal signal and the output circuit comprises an analog-to-digital converter configured to convert a sensed voltage based on the first temperature-dependent voltage to the digital thermal signal, the analog-to-digital converter using the reference voltage to generate the digital thermal signal.
However, Aguirre discloses an integrated circuit (page 2; figure 1; and the paragraphs above and below figure 1) having an output circuit comprising an analog-to-digital converter (A/D) configured to use a reference voltage (Vref) and a temperature-dependent voltage (Vptat) to generate a digital thermal signal (digital output) in order to simplify analog circuitry and allow low consumption (abstract).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Isik in view of Aota such that the at least one thermal output signal comprises a digital thermal signal and the output circuit comprises an analog-to-digital converter configured to convert a sensed voltage based on the first temperature-dependent voltage to the digital thermal signal, the analog-to-digital converter using the reference voltage to generate the digital thermal signal, as suggested by Aguirre, in order to simplify analog circuitry and allow low consumption.
Referring to claim 26, Isik in view of Aota and Aguirre disclose a circuit having all of the limitations of claim 26, as stated above with respect to claim 25, except for Isik in view of Aota and Aguirre explicitly disclosing that the analog-to-digital converter comprises a sigma-delta modulator.
However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Isik in view of Aota and Aguirre by using a sigma-delta modulator as the analog-to-digital converter in order to provide a desired accuracy of the digital thermal signal while simplifying the analog circuitry and allowing low consumption, which Aguirre suggests is desirable; and since the use of the particular type of analog-to-digital converter claimed by the applicant is considered to be nothing more than a choice of engineering skill, choice, or design, because the use of the particular analog-to-digital converter claimed by the applicant is considered to be the use of numerous alternate types of analog-to-digital converters that a person having ordinary skill in the art before the effective filing date of the claimed invention would have been able to provide using routine experimentation in order to provide an analog-to-digital converter as already suggested by Aguirre.
Conclusion
The references made of record and not relied upon by the examiner are considered pertinent to applicant's disclosure by disclosing a thermal sensor for an integrated circuit.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIRELLYS JAGAN whose telephone number is (571)272-2247. The examiner can normally be reached Tuesday-Friday 8-6.
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/MIRELLYS JAGAN/
Primary Examiner
Art Unit 2855
6/17/26
Prosecution Insights