CTNF 18/833,079 CTNF 86395 DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-30-03-h AIA Claim Interpretation The following is a quotation of 35 U.S.C. 112(f): (f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. 07-30-05 The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) is invoked. As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f): (A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function; (B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and (C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function. Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function. Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function. Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) except as otherwise indicated in an Office action. This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: an information acquisition device in claim 10. Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof. A review of the specification shows that no corresponding structure for performing the claimed function is described. Therefore the claim scope is indefinite. If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f). Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. Claims 4-11 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. Claim 4 recites “a chip holder configured to hold the multiple chips” in line 6 and “a pickup device configured to separate the chip held by the chip holder” in lines 7-8. It is unclear from these limitations whether the chip holder holds multiple chips or a single chip. For examination purposes, the claim has been construed as reciting “a pickup device configured to separate the a single chip held by the chip holder.” Claim 6 recites “the chip whose bonding state is determined to be bad” in line 5. There is insufficient antecedent basis for this limitation in the claim. For examination purposes, the claim has been construed as reciting “ a the chip whose bonding state is determined to be bad.” Claim 7 recites “the chip whose bonding state is determined to be bad” in lines 6-7. There is insufficient antecedent basis for this limitation in the claim. For examination purposes, the claim has been construed as reciting “ a the chip whose bonding state is determined to be bad.” Claim 8 recites the limitation “the chip” in line 2 and line 4. It is unclear which chip is being referred to in these limitations because multiple chips are previously recited. For examination purposes, the claim has been construed as reciting “the chip whose bonding state is determined to be bad ” in each instance. Claim 10 recites “an information acquisition device” in line. This limitation meets the three prong test for analysis under 35 U.S.C. 112(f) because it uses the nonce term “device” for performing a claimed function of “information acquisition” but does not recite sufficient structure, material, or acts for performing the function. The limitation is therefore interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof. However the instant specification provides no corresponding structure for performing the claimed function. Therefore the claims are indefinite, and one of ordinary skill in the art is not reasonably apprised of the metes and bounds of the claim. For examination purposes, any apparatus which can inspect a bond region will be considered to meet the claim. Claim 10 recites “a device” in each bonding region. The term “device” is generic and does not adequately describe what structure is present in each bonding region. Claim 10 recites the limitations “the device whose state is good” and ”the device whose state is bad.” There is insufficient antecedent basis for these limitations in the claim. Claim 11 recites the limitation “the chip” in line. It is unclear which chip is being referred to in these limitations because multiple chips are previously recited. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-20-02-aia AIA This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. 07-21-aia AIA Claim s 1-2, 7, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Kang (US 2023/0092257) in view of Yamauchi (US 2023/0307284) . Kang teaches a bonding apparatus (10) comprising a cleaner (400A) having a first cleaning area (410A) for a die supply wafer (W1) with a plurality of dies (D) thereon and a second cleaning area (410B) for a substrate wafer (W2), a first bonding device (200A) configured to bond a die from the die supply wafer to a surface of the substrate wafer, a first transferer (300A) adjacent to the cleaner and the first bonding device and comprising a plurality of mobile robots (310) configured to hold and transfer the die supply wafer and the substrate wafer between wafer suppliers (100A), the cleaner, and the bonding device (See Figures; [0042]-[0053]; [0071]-[0081]). The first cleaning area, second cleaning area, substrate wafer, first transferer, bonding device, and dies read on the instantly claimed chip cleaning device, substrate cleaning device, substrate, transfer section, chip bonding device, and multiple chips, respectively. The mobile robots of Kang move the die supply wafers and substrate wafers and read on the instantly claimed first substrate transfer arm and first frame transfer arm. Regarding the limitation “a chip bonding device configured to bond the multiple chips to different bonding regions of a main surface of the substrate,” Kang shows a plurality of dies on a single surface of the substrate wafer in Fig. 4 and states that “the bonding device may perform a bonding process until dies (D) are bonded to all areas to be bonded on the substrate wafer (W2)” (See [0058]), both of which satisfy the limitation. Kang shows a die supply wafer (W1) having multiple dies and that such a wafer may include a tape (See Figures; [0045]-[0050]). Kang does not expressly disclose a die supply wafer comprising multiple dies attached to a frame via the tape as claimed. Yamauchi teaches a chip bonding system which includes a cleaning device (85) which cleans a substrate (WT) and also cleans multiple chips (CP) attached to a sheet (TE) which is held on a ring frame (RI), a bonding device (30) which bonds the chips to the substrate, and a transportation device (70) comprising a robot arm which can transport the substrate and the ring frame to move them between the cleaning device and the bonding device (See Figures; [0050]-[0060]). It would have been obvious to one of ordinary skill in the art at the time of filing to provide the dies of Kang on a tape supported by a ring frame since Yamauchi teaches that a frame-supported tape was recognized in the prior art as being suitable for transporting and processing a plurality of chips (See Figures; [0050]-[0060]). Regarding claim 2, Kang shows a supporter (211) which exerts an upward pressure on the die supply wafer (W1) (See Fig. 3 and its description). While Kang does not expressly disclose that the supporter acts as an expander, it is well known in the art that exertion of an upward force on a die-containing sheet expands the shape to create a gap between the dies. Yamauchi teaches a frame support (411) which exerts upward pressure which radially stretches a sheet (TE) and thereby creates space between chips (CP) contained on the sheet (See Figs. 6A-6B; [0058]). Regarding claim 7, Kang teaches an inspection member (231) which checks for mounting precision or foreign materials after bonding (See [0062]-[0064]). Regarding claim 12, Kang teaches a pretreatment device (600A) which activates a bonding surface of the substrate wafer with plasma, wherein the pretreatment device is located adjacent to the first transferer, and the substrate wafer is transferred to the pretreatment device with one of the mobile robots (See Figures; [0082]-[0084]) . 07-22-aia AIA Claim s 3 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Kang (US 2023/0092257) in view of Yamauchi (US 2023/0307284) , as applied to claim 1 above, and further in view of Tamura (US 2020/0234990) . Kang and Yamauchi combine to teach a bonding apparatus, as detailed above. Regarding claim 3, Kang and Yamauchi do not expressly disclose guide rails for mounting the frame containing the tape with multiple chips. Tamura teaches accommodation plates (46) which support two ends of a frame (19) during processing (See Figs. 17-18; [0075]; [0188]-[0189]). The plates read on the instantly claimed guide rails on which the frame is mounted. It would have been obvious to one of ordinary skill in the art at the time of filing to use accommodation plates in the first cleaning area of the apparatus taught by the combination of Kang and Yamuchi in order to support the die supporting wafer during cleaning since Tamura teaches that such plates were recognized in the prior art as being suitable for supporting frames in a processing apparatus (See Figs. 17-18; [0075]; [0188]-[0189]). Regarding claim 13, Kang teaches a first wafer supplier (100A) comprising load ports (LP1-LP4) for the die supply wafers and the substrate wafers (See Figs.; [0045]-[0046]). The first wafer supplier reads on the instantly claimed placing table on which substrates and frame-supported tapes with chips are placed. Kang and Yamauchi do not expressly disclose cassettes on the placing table which are configured to carry substrate wafers and die supply wafers as claimed. Tamura teaches cassettes (35) which support stacks of substrates (10) ahead of processing (See Fig. 12; [0071]-[0073]). It would have been obvious to one of ordinary skill in the art at the time of filing to use cassettes as the load ports in the apparatus taught by the combination of Kang and Yamauchi. The rationale to do so would have been the motivation provided by the teaching of Tamura that to do so would predictably allow for multiple wafers to be accommodated in a vertical stack ahead of processing (See [0071]) . 07-22-aia AIA Claim s 4-6 and 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Kang (US 2023/0092257) in view of Yamauchi (US 2023/0307284) , as applied to claim 1 above, and further in view of Oh (US 2019/0025700) . Kang and Yamauchi combine to teach a bonding apparatus, as detailed above. Regarding claim 4, Kang and Yamauchi do not expressly disclose an interface block having a buffer module and storage holders for the substrate wafers and die supply wafers. Oh teaches a substrate treating apparatus comprising a first buffer module (300) comprising first and second buffers (320,330) which temporarily store a plurality of wafers (W) (See Figs. 1-2; [0045]-[0049]). It would have been obvious to one of ordinary skill in the art at the time of filing to incorporate a buffer module and corresponding buffers in the apparatus taught by the combination of Kang and Yamauchi. The rationale to do so would have been the motivation provided by the teaching of Oh that to do so would predictably allow a plurality of wafers (W) to be temporarily preserved for processing (See [0047]). Regarding claim 5, the use of different chips describes the material worked upon by the apparatus and does not further limit the structure of the apparatus itself. Therefore the limitations pertaining to the differences in the chips have not been given patentable weight. The addition of a further buffer module for storing wafers ahead of processing would have been obvious in view of the teachings of Oh for the same reasons detailed above with respect to claim 4. Regarding claims 6-9, Kang teaches an inspection member (231) which checks for mounting precision or foreign materials after bonding (See [0062]-[0064]). The inspection member reads on the instantly claimed inspection device. The limitations in claims 8-9 detailing the bonding steps which may or may not be performed by the chip bonding device describe the intended use of the apparatus and do not impart any additional structure to the apparatus itself. Therefore such limitations pertaining to the particular steps performed by the chip bonding device and materials used during such steps have not been given patentable weight. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CARSON GROSS whose telephone number is (571)270-7657. The examiner can normally be reached Monday-Friday 9am-5pm Eastern. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Michael Orlando can be reached at (571)270-5038. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CARSON GROSS/ Primary Examiner, Art Unit 1746 Application/Control Number: 18/833,079 Page 2 Art Unit: 1746 Application/Control Number: 18/833,079 Page 3 Art Unit: 1746 Application/Control Number: 18/833,079 Page 4 Art Unit: 1746 Application/Control Number: 18/833,079 Page 5 Art Unit: 1746 Application/Control Number: 18/833,079 Page 6 Art Unit: 1746 Application/Control Number: 18/833,079 Page 7 Art Unit: 1746 Application/Control Number: 18/833,079 Page 8 Art Unit: 1746 Application/Control Number: 18/833,079 Page 9 Art Unit: 1746 Application/Control Number: 18/833,079 Page 10 Art Unit: 1746 Application/Control Number: 18/833,079 Page 11 Art Unit: 1746
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